WO2012139261A1 - 本导体器件及其制造方法 - Google Patents

本导体器件及其制造方法 Download PDF

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Publication number
WO2012139261A1
WO2012139261A1 PCT/CN2011/001314 CN2011001314W WO2012139261A1 WO 2012139261 A1 WO2012139261 A1 WO 2012139261A1 CN 2011001314 W CN2011001314 W CN 2011001314W WO 2012139261 A1 WO2012139261 A1 WO 2012139261A1
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WIPO (PCT)
Prior art keywords
layer
gate stack
substrate
epitaxial layer
semiconductor device
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PCT/CN2011/001314
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English (en)
French (fr)
Inventor
尹海洲
朱慧珑
骆志炯
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to US13/378,996 priority Critical patent/US20120261772A1/en
Priority to CN201190000081.5U priority patent/CN203205398U/zh
Publication of WO2012139261A1 publication Critical patent/WO2012139261A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/258—Source or drain electrodes for field-effect devices characterised by the relative positions of the source or drain electrodes with respect to the gate electrode
    • H10D64/259—Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/0698—Local interconnections

Definitions

  • the present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and a method of fabricating the same. Background technique
  • a semiconductor device (such as a transistor) including a source region and a drain region is a contact structure of a commonly required electrical connection in an integrated circuit and is one of important components in the circuit.
  • Figure 1 shows an example of a prior art contact structure.
  • a contact structure 130 is formed on a source region and a drain region of a semiconductor device including a gate, a source region, and a drain region.
  • the top 131 of the contact structure is larger than the bottom 133 thereof.
  • Such a contact structure has the following problems. Since the bottom of the contact structure is small, the contact area of the contact structure with the source and drain regions is small, and as the size of the semiconductor device is gradually reduced, the influence on the contact resistance is gradually increased. Moreover, the distance between the top of such a contact structure and the top of the gate of the semiconductor device is small, which increases the likelihood of a short between the contact structure and the gate. Summary of the invention
  • a semiconductor device including a gate stack, a source region, a drain region, a contact plug, and an interlayer dielectric, the gate stack being formed on a substrate, the source region and the drain region Located on both sides of the gate stack and embedded in the substrate, the contact plug In the interlayer medium, wherein the contact plug includes a first portion, the contact plug is connected to the source region and/or the drain region with the first portion, the first portion The upper surface is flush with the upper surface of the gate stack, and the angle between the sidewall of the first portion and the bottom wall is less than 90°.
  • the angle between the side wall of the first portion and the bottom wall is less than 90°, so that the top of the first portion can be smaller than the bottom portion thereof.
  • the semiconductor device including the first portion has a smaller top area and a larger bottom area than other semiconductor devices of the same size. Therefore, the contact area of the first portion with the source region and/or the drain region can be increased to facilitate reducing the contact resistance; and the distance between the top of the first portion and the top of the gate stack can be increased. It is beneficial to reduce the possibility of short circuit between the first portion and the gate stack.
  • a method of fabricating a semiconductor device including:
  • the contact hole is filled with a conductive material.
  • the epitaxial layer is formed by a facet epitaxial process on a source region and/or a drain region formed on the (100) substrate such that an angle between a sidewall of the epitaxial layer and a bottom wall thereof is less than 90.
  • the semiconductor device including the first portion has a smaller top area and a larger bottom area than other semiconductor devices of the same size.
  • the contact area of the first portion with the source region and/or the drain region can be increased to reduce the contact resistance; and the distance between the top of the first portion and the top of the gate stack can be increased. It is beneficial to reduce the possibility of short circuit between the first portion and the gate stack.
  • Figure 1 shows a schematic cross-sectional view of a prior art contact structure.
  • Fig. 2 shows a cross-sectional schematic view of a semiconductor device in accordance with an exemplary embodiment of the present invention.
  • FIG. 3A illustrates a first step of fabricating a semiconductor device by which an epitaxial layer is formed in accordance with an exemplary embodiment of the present invention.
  • FIG. 3B illustrates a second step of fabricating a semiconductor device in which an interlayer dielectric is formed in accordance with an exemplary embodiment of the present invention.
  • FIG. 3C illustrates a third step of fabricating a semiconductor device by which a planarized interlayer dielectric is formed in accordance with an exemplary embodiment of the present invention.
  • a contact hole is formed in this step.
  • the fifth step through which the contact layer is formed.
  • Fig. 3F shows a sixth step of fabricating a semiconductor device in which a contact hole is filled with a conductive material in accordance with an exemplary embodiment of the present invention.
  • the seventh step in which a flattened first portion is formed.
  • a semiconductor device according to an exemplary embodiment of the present invention will be described in detail with reference to FIG.
  • a first portion 280 of a contact plug 230 in accordance with an exemplary embodiment of the present invention is formed on a source region 241 and/or a drain region 242 of a semiconductor device.
  • FIG. 2 shows that the first portion 280 is formed on both the source region 241 and the drain region 242 of the semiconductor device, as is known to those skilled in the art, the first portion 280 may be formed only at the source as needed.
  • the first portion 280 material may be a first metal material (ie, a metal layer).
  • the first metal material may include, but is not limited to, a material or a combination of materials selected from the group consisting of: W, Al, TiAl, Cu o
  • the outer portion of the first portion 280 may be provided with a liner (ie barrier layer, not shown).
  • the liner is formed from a second metallic material.
  • the second metallic material may include, but is not limited to, a material or combination of materials selected from the group consisting of Ti, TiN, Ta, TaN, or Ru.
  • the top portion of the first portion 280 is smaller than the bottom portion thereof. Since the bottom portion of the first portion 280 has a large area, it is advantageous to reduce the contact resistance between the first portion 280 and the source region 241 and the drain region 242 of the semiconductor device.
  • the upper surface of the first portion 280' is flush with the upper surface of the gate stack 210 (in this document, the term "flush" means that the height difference between the two is in the process.
  • the side wall of the first portion 280 is less than 90° from the bottom wall thereof. In particular, the angle between the side wall of the first portion 280 and the bottom wall may range from 50° to 60°.
  • a semiconductor device 200 includes: a substrate 201; a gate stack 210 formed on a substrate 201; and a source region 241 in the bottom of each of the gate stacks 210 And a drain region 242; a first portion 280 of the contact plug 230 formed on at least one of the source region 241 and the drain region 242; and an interlayer dielectric 260 in which the contact plug 230 is embedded.
  • ⁇ "Bottom 201 can be silicon or germanium, silicon-on-insulator (SOI) or silicon-on-insulator, or any semiconductor material formed on a semiconductor substrate, such as SiC, etc., or even III-V a compound semiconductor (such as GaAs, InP, etc.) or a II-VI compound semiconductor (such as ZnSe, ZnS) or the like.
  • the gate stack 210 may include a gate dielectric 211 and a gate dielectric 211 Gate electrode 212.
  • the gate stack 210 further includes a spacer spacer 220 (the spacer, the spacer spacer may be a single layer or a multi-layer structure, and when the sidewall spacer is a multi-layer structure, adjacent layers
  • the material may be different, in other embodiments, the sidewall spacers may also be included, which are disposed on the sidewalls of the gate dielectric 211 and the gate electrode 212.
  • the gate dielectric 211 may be made of silicon oxide, silicon oxynitride or a high-k dielectric material (eg, ⁇ 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, A1 2 0 3 , La 2 0 3 , Zr0 2 , LaAlO).
  • a high-k dielectric material eg, ⁇ 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, A1 2 0 3 , La 2 0 3 , Zr0 2 , LaAlO.
  • the gate electrode 212 may be formed of a conductive material such as a metal or a doped semiconductor material, a doped semiconductor material such as doped polysilicon.
  • the source region 241 and the drain region 242 may be formed by an ion implantation process (injecting doping particles into the substrate 201) or by first forming trenches on both sides of the gate stack 210 and then epitaxially growing the semiconductor material on the exposed substrate 201, Let me repeat.
  • the interlayer dielectric 260 material may be a doped or undoped vitreous silica such as one of SiOF, SiCOH, SiO, SiCO, SiCON, SiON, PSG (phosphorus silicate glass) or BPSG (borophosphosilicate glass) or Its combination.
  • the angle between the side wall of the first portion 280 and the bottom wall thereof is less than 90°, so that the top of the first portion 280 can be smaller than the bottom portion thereof.
  • the semiconductor device including the first portion 280 has a smaller top area and a larger bottom area than other semiconductor devices of the same size. Therefore, the contact area of the first portion 280 with the source region 241 and/or the drain region 242 can be increased to reduce the contact resistance; and the top of the first portion 280 and the top of the gate stack 210 can also be The increased distance facilitates reducing the likelihood of a short between the first portion 280 and the gate stack 210.
  • the first step Through this step, an epitaxial layer is formed. More specifically, as shown in FIG. 3A, a gate stack substrate is formed on the (100) substrate, and a source region 241 and a drain region 242 are formed on both sides of the gate stack substrate, and in the source region and the The epitaxial layer 250 is formed by a faceted epitaxial growth on the drain region such that an angle between the sidewall of the epitaxial layer 250 and the bottom wall thereof is less than 90°.
  • the height of the epitaxial layer 250 is less than the height of the gate stack substrate; the components of the gate stack substrate are the same as the foregoing gate stack 210, but differ in height, undergoing subsequent planarization to expose After operation of the epitaxial layer 250 and an optional replacement gate process, the gate stack substrate becomes the gate stack 210.
  • the crystal face epitaxial process means that the semiconductor material has a different growth rate in different directions when the semiconductor material is epitaxially grown on the substrate, and the substrate material is (100) silicon as an example, when the semiconductor material is epitaxially grown thereon.
  • the semiconductor material has a faster growth rate on (100) and a slower growth rate on (11), which in turn causes the epitaxial layer in the structure shown in Fig. 3 to have an inverted pyramid structure.
  • the epitaxial layer 250 material is SiGe, Ge,
  • the epitaxial layer 250 may be a single layer or a plurality of layers (in this case, the adjacent two layers of materials are different).
  • the second step In this step, an interlayer dielectric 260 is formed. More specifically, the formed interlayer shield 260 covers the epitaxial layer 250 and the gate stack substrate.
  • FIG. 3C illustrates a third step of a method of fabricating a semiconductor device in accordance with an exemplary embodiment of the present invention.
  • a planarized interlayer dielectric 260 is formed. More specifically, after planarizing the interlayer dielectric 260, the epitaxial layer 250 is exposed. As an example, a chemical mechanical polishing (CMP) process can be utilized to planarize the interlayer dielectric 260.
  • CMP chemical mechanical polishing
  • the fourth step In this step, a contact hole is formed. More specifically, at least a portion of the height of the epitaxial layer 250 is removed to form a contact hole 251.
  • FIG. 3D shows the case where the epitaxial layer 250 is partially removed. In other embodiments, epitaxial layer 250 can also be completely removed.
  • removing at least a portion of the height of the epitaxial layer is performed by selective etching, such as the epitaxial layer including a first layer (such as Si) and a second layer (such as SiGe) and the second layer is formed on
  • the step of removing at least a portion of the epitaxial layer is to remove the second layer.
  • the contact layer 270 may be formed by: first, forming a metal material to cover the bottom wall and the sidewall of the contact hole 251, the metal material may be, for example, a metal material containing Ni, Co or Ti; and then annealing The process is to form a contact layer 270 (such as a metal silicide such as NiSi, CoSi or TiSi); finally, the unreacted metal material is removed.
  • the sixth step In this step, the contact hole 251 is filled with a conductive material to form the first portion 280 of the contact plug 230. Wherein, the top area of the first portion 280 is smaller than the bottom area thereof.
  • the step of filling the contact hole with a conductive material includes: first, forming a barrier layer covering a sidewall and a bottom wall of the contact hole, the barrier layer material being Ta, TaN, Ti, TiN or Ru One or a combination thereof; Then, a metal layer is formed, and the metal layer is formed on the barrier layer, and the metal layer material is one of W, Al, Cu, TiAl or a combination thereof.
  • the first portion 280 is planarized.
  • the first portion 280 can be planarized using a chemical mechanical polishing (CMP) process.
  • CMP chemical mechanical polishing
  • an epitaxial layer by a facet epitaxial process on a source region and/or a drain region formed on a (100) substrate such that an angle between a sidewall of the epitaxial layer and a bottom wall thereof is less than 90°
  • a contact hole is formed after removing at least a portion of the epitaxial layer, and the contact hole is filled with a conductive material, thereby forming a first portion, and an angle between a sidewall of the first portion and a bottom wall thereof is less than 90. That is, the top of the first portion is made smaller than the bottom thereof.
  • the semiconductor device including the first portion has a smaller top area and a larger bottom area than other semiconductor devices of the same size.
  • the contact area of the first portion with the source region and/or the drain region can be increased to reduce the contact resistance; and the distance between the top of the first portion and the top of the gate stack can be increased. It is beneficial to reduce the possibility of short circuit between the first portion and the gate stack.

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Description

半导体器件及其制造方法 本申请要求了 2011年 4月 15日提交的、申请号为 201 110094967.7、 发明名称为"半导体器件及其制造方法"的中国专利申请的优先权，其全 部内容通过引用结合在本申请中。 技术领域
本发明涉及半导体制造技术领域， 特别涉及一种半导体器件及其 制造方法。 背景技术
包括源区和漏区的半导体器件 （比如晶体管）是集成电路中的常 所需电连接的接触结构， 是电路中的重要组成部分之一。
图 1示出了现有的接触结构的实例。 如图 1所示， 接触结构 130 形成在包括栅极、 源区和漏区的半导体器件的源区和漏区上。 该接触 结构的顶部 131大于其底部 133。
然而， 这样的接触结构具有以下问题。 由于该接触结构的底部较 小， 所以该接触结构与源区和漏区的接触面积较小， 随着半导体器件 尺寸的逐渐缩小， 其对接触电阻的影响逐渐增大。 此外， 这种接触结 构的顶部与半导体器件的栅极顶部之间的距离较小， 这增大了接触结 构与栅极之间短路的可能性。 发明内容
本发明的其中一个目的是克服以上缺点中的至少一个， 并提供一 种改进的半导体器件及其制造方法。
根据本发明的一个方面， 提供了一种半导体器件， 包括栅堆叠、 源区、 漏区、 接触塞和层间介质， 所述栅堆叠形成于衬底上， 所述源 区和所述漏区位于所述栅堆叠两侧且嵌于所述衬底中， 所述接触塞嵌 于所述层间介质中， 其中， 所述接触塞包括第一部， 所述接触塞以所 述第一部接于所述源区和 /或所述漏区上， 所述第一部的上表面与所述 栅堆叠的上表面齐平，且所述第一部的侧壁与其底壁的夹角小于 90° 。
所述第一部的侧壁与其底壁的夹角小于 90° ， 可使所述第一部的 顶部小于其底部。 换言之， 包含该第一部的半导体器件与其他同尺寸 的半导体器件相比， 该第一部的顶部面积较小而底部面积较大。 因此， 既可使该第一部与源区和 /或漏区的接触面积增大，利于减小接触电阻； 也可使该第一部的顶部与栅堆叠的顶部之间的距离增大， 利于降低该 第一部与栅堆叠之间短路的可能性。
根据本发明的再一方面， 提供了一种半导体器件的制造方法， 包 括：
在（ 100 )衬底上形成栅堆叠基体， 并在所述栅堆叠基体两侧形成 源区和漏区；
在所述源区和 /或所述漏区上以晶面外延工艺形成外延层， 以使所 述外延层的侧壁与其底壁的夹角小于 90° ；
形成平坦化的层间介质， 以暴露所述外延层；
至少去除部分高度的所述外延层， 以形成接触孔；
以导电材料填充所述接触孔。
通过先在形成于 （ 100 ) 衬底上的源区和 /或漏区上以晶面外延工 艺形成外延层， 以使所述外延层的侧壁与其底壁的夹角小于 90。 ， 再 在至少去除部分高度的所述外延层后形成接触孔， 再以导电材料填充 所述接触孔， 进而可形成第一部， 且使所述第一部的侧壁与其底壁的 夹角小于 90° ， 即， 使所述第一部的顶部小于其底部。 换言之， 包含 该第一部的半导体器件与其他同尺寸的半导体器件相比， 该第一部的 顶部面积较小而底部面积较大。 因此， 既可使该第一部与源区和 /或漏 区的接触面积增大， 利于减小接触电阻； 也可使该第一部的顶部与栅 堆叠的顶部之间的距离增大， 利于降低该第一部与栅堆叠之间短路的 可能性。 附图说明
本发明的这些和其它目的、 特征和优点将会从结合附图对于本发 明示例性实施例的以下详细描述中变得更为清楚明了。 在附图中： 图 1 示出了现有的接触结构的横截面示意图。
图 2示出了根据本发明示例性实施例的半导体器件的横截面示意 图。
图 3A 示出了根据本发明的示例性实施例制造半导体器件的第一 步骤， 通过该步骤形成了外延层。
图 3B 示出了根据本发明的示例性实施例制造半导体器件的第二 步骤， 在该步骤中形成了层间介质。
图 3C 示出了根据本发明的示例性实施例制造半导体器件的第三 步骤， 通过该步驟形成了平坦化的层间介质。 步骤， 在该步骤中形成了接触孔。 的第五步骤， 通过该步骤形成了接触层。
图 3F 示出了根据本发明的示例性实施例制造半导体器件的第六 步骤， 在该步骤中利用导电材料填充了接触孔。 的第七步骤， 在该步骤中形成了平坦化的第一部。 具体实施方式
以下将结合附图详细描述本发明的示例性实施例。 附图是示意性 的， 并未按比例绘制， 且只是为了说明本发明的实施例而并不意图限 制本发明的保护范围。 为了使本发明的技术方案更加清楚， 本领域熟 知的工艺步骤及器件结构在此省略。
首先， 参照图 2详细描述根据本发明示例性实施例的半导体器件。 如图 2所示，根据本发明示例性实施例的接触塞 230的第一部 280 形成在半导体器件的源区 241和 /或漏区 242上。 尽管图 2示出了第一 部 280形成在半导体器件的源区 241和漏区 242这两者上， 但正如本 领域技术人员所知， 也可以根据需要， 使第一部 280仅形成在源区 241 和漏区 242之一上。
作为示例， 所述第一部 280材料可以为第一金属材料（即为金属 层） 。 所述第一金属材料可以包括但不限于从以下材料构成的组中选 取的材料或材料组合： W、 Al、 TiAl、 Cu o 可选地， 所述第一部 280 的外部可以设置有衬层 （即为阻挡层， 未示出） 。 在一个示例中， 该 衬层由第二金属材料形成。 所述第二金属材料可以包括但不限于从以 下材料构成的组中选取的材料或材料组合： Ti、 TiN、 Ta、 TaN或 Ru。
第一部 280的顶部面积小于其底部面积。 由于第一部 280的底部 面积较大， 因此利于减小第一部 280与半导体器件的源区 241和漏区 242之间的接触电阻。 在图 2 所示的示例性实施例中， 所述第一部 280 '的上表面与栅堆叠 210 的上表面齐平 （本文件中， 术语 "齐平" 意指 二者的高度差在工艺允许的误差范围内） ， 且所述第一部 280 的侧壁 与其底壁的夹角小于 90° 。 特别地， 所述第一部 280的侧壁与其底壁 的夹角范围可为 50° ~ 60° 。
如图 2所示， 根据本发明示例性实施例的半导体器件 200包括： 衬底 201 ; 形成在衬底 201上的栅堆叠 210; 分别位于栅堆叠 210两侧 的^"底中的源区 241和漏区 242;形成在源区 241和漏区 242中的至少 一个上的接触塞 230的第一部 280; 以及， 嵌有所述接触塞 230的层间 介质 260。
^"底 201可以为硅或锗， 还可以为绝缘体上硅 ( SOI )或绝缘体上 硅锗， 也可以是形成于半导体衬底上的任意半导体材料， 如 SiC等， 甚至可以是 III-V族化合物半导体 （如 GaAs、 InP等）或 II-VI族化合 物半导体 (如 ZnSe、 ZnS ) 等。
栅堆叠 210可以包括栅极电介质 211和位于栅极电介质 211上的 栅电极 212。在本实施例中，栅堆叠 210还包括侧墙隔离层 220( spacer, 所述侧墙隔离层可为单层或多层结构， 所述侧墙隔离层为多层结构时， 相邻层之间的材料可不同， 在其他实施例中， 也可以不包括侧墙隔离 层） ， 其设置在栅极电介质 211和栅电极 212的侧壁上。 作为示例， 栅极电介质 211可以由氧化硅、 氮氧化硅或高 k电介质材料（如 ΗίΌ2、 HfSiO、 HfSiON, HfTaO、 HfTiO、 HfZrO、 A1203、 La203、 Zr02、 LaAlO 中的一种或其组合） 形成， 栅电极 212 可以由导电材料（如金属或掺 杂的半导体材料， 掺杂的半导体材料例如为掺杂的多晶硅） 形成。
源区 241和漏区 242可经由离子注入工艺 （向衬底 201 中注入掺 杂粒子）或者先在栅堆叠 210两侧形成沟槽再在暴露的衬底 201上外 延生长半导体材料后形成， 不再赘述。 层间介质 260材料可为掺杂或 未掺杂的氧化硅玻璃， 如 SiOF、 SiCOH、 SiO、 SiCO、 SiCON、 SiON、 PSG (磷硅玻璃）或 BPSG (硼磷硅玻璃） 中的一种或其组合。
所述第一部 280的侧壁与其底壁的夹角小于 90° , 可使所述第一 部 280的顶部小于其底部。 换言之， 包含该第一部 280的半导体器件 与其他同尺寸的半导体器件相比， 该第一部 280 的顶部面积较小而底 部面积较大。 因此， 既可使该第一部 280与源区 241和 /或漏区 242的 接触面积增大， 利于减小接触电阻； 也可使该第一部 280 的顶部与栅 堆叠 210的顶部之间的距离增大，利于降低该第一部 280与栅堆叠 210 之间短路的可能性。
下面， 参照图 3A至 3G详细描述根据本发明示例性实施例的制造 半导体器件的方法。 的第一步骤。通过该步骤， 形成了外延层。 更具体而言， 如图 3A所示， 在（ 100 )衬底上形成栅堆叠基体， 并在所述栅堆叠基体两侧形成源区 241和漏区 242， 再在所述源区和所述漏区上以晶面外延工艺 （faceted epitaxial growth ) 形成外延层 250, 以使所述外延层 250的侧壁与其底 壁的夹角小于 90° 。 本实施例中，所述外延层 250的高度小于所述栅堆叠基体的高度； 所述栅堆叠基体的各组成部分与前述栅堆叠 210相同， 只是高度上有 所不同， 经历后续平坦化以暴露所述外延层 250 的操作以及可选的替 代栅工艺后， 所述栅堆叠基体变为所述栅堆叠 210。
晶面外延工艺意指在衬底上外延生长半导体材料时， 此半导体材 料在不同方向上的生长速率不同， 以衬底材料为 （ 100 )硅为例， 在其 上外延生长半导体材料时， 此半导体材料在 （ 100 ) 上生长速率较快， 而在（ 1 11 )上生长速率较慢， 进而会使如图 3所示的结构中的外延层 自然具有倒锥状结构。
作为示例， 所述衬底为硅时， 所述外延层 250材料为 SiGe、 Ge、
SiC 掺杂或未掺杂的单晶硅或多晶硅中的一种或其组合。 外延层 250 可以为单层或多层 （此时， 相邻的两层材料不同） 。 的第二步骤。 在该步骤中， 形成了层间介质 260。 更具体而言， 形成的 层间介盾 260覆盖外延层 250和所述栅堆叠基体。
图 3C 示出了根据本发明的示例性实施例制造半导体器件的方法 的第三步骤。通过该步骤，形成了平坦化的层间介质 260。更具体而言， 平坦化层间介质 260后， 暴露所述外延层 250。 作为示例， 可以利用化 学机械抛光（CMP ) 工艺来平坦化层间介质 260。 的第四步骤。 在该步骤中， 形成了接触孔。 更具体而言， 至少去除部 分高度的所述外延层 250，以形成接触孔 251。 图 3D示出了外延层 250 被部分地去除的情形。 在其他实施例中， 外延层 250也可以被完全去 除。 本领域技术人员可以根据工艺需要灵活选择。 在一个示例中， 至 少去除部分高度的外延层是通过选择性刻蚀进行的， 如所述外延层包 括第一层 （如 Si ) 和第二层 （如 SiGe )且所述第二层形成于所述第一 层上时， 至少去除部分高度的所述外延层的步骤为去除所述第二层。 的可选的第五步骤， 通过该步骤形成了接触层 270。 作为示例， 可以通 过如下步骤来形成接触层 270: 首先， 形成金属材料以覆盖接触孔 251 的底壁和侧壁， 该金属材料例如可以是含 Ni、 Co或 Ti的金属材料； 然后， 进行退火工艺以形成接触层 270 (如金属硅化物， 例如 NiSi、 CoSi或 TiSi ) ; 最后， 去除未反应的金属材料。 的第六步骤。 在该步骤中， 利用导电材料填充接触孔 251 从而形成接 触塞 230的第一部 280。 其中， 该第一部 280的顶部面积小于其底部面 积。 以导电材料填充所述接触孔的步骤包括： 首先， 形成阻挡层， 所 述阻挡层覆盖所述接触孔的侧壁和底壁， 所述阻挡层材料为 Ta、 TaN、 Ti、 TiN或 Ru中的一种或其组合； 然后， 形成金属层， 所述金属层形 成于所述阻挡层上， 所述金属层材料为 W、 Al、 Cu、 TiAl中的一种或 其组合。 的可选的第七步骤。 在该步骤中， 平坦化所述第一部 280。 作为示例， 可以利用化学机械抛光（CMP ) 工艺来平坦化所述第一部 280。
通过先在形成于 （ 100 )衬底上的源区和 /或漏区上以晶面外延工 艺形成外延层， 以使所述外延层的侧壁与其底壁的夹角小于 90° , 再 在至少去除部分高度的所述外延层后形成接触孔， 再以导电材料填充 所述接触孔， 进而可形成第一部， 且使所述第一部的侧壁与其底壁的 夹角小于 90。 ， 即， 使所述第一部的顶部小于其底部。 换言之， 包含 该第一部的半导体器件与其他同尺寸的半导体器件相比， 该第一部的 顶部面积较小而底部面积较大。 因此， 既可使该第一部与源区和 /或漏 区的接触面积增大， 利于减小接触电阻； 也可使该第一部的顶部与栅 堆叠的顶部之间的距离增大， 利于降低该第一部与栅堆叠之间短路的 可能性。
尽管已经参照附图详细地描述了本发明的示例性实施例， 但是这 样的描述应当被认为是说明性或示例性的， 而不是限制性的； 本发明 并不限于所公开的实施例。 上面以及权利要求中描述的不同实施例也 可以加以组合。 本领域技术人员在实施要求保护的本发明时， 根据对 于附图、 说明书以及权利要求的研究， 能够理解并实施所公开的实施 例的其他变型， 这些变型也落入本发明的保护范围内。
在权利要求中， 词语 "包括" 并不排除其他部件或步骤的存在并 且 "一" 或 "一个" 并不排除复数。 在相互不同的从属权利要求中陈 述了若干技术手段的事实并不意味着这些技术手段的组合不能有利地 力口以利用。

Claims

权 利 要 求
1. 一种半导体器件， 包括栅堆叠、 源区、 漏区、 接触塞和层间介 质， 所述栅堆叠形成于衬底上， 所述源区和所述漏区位于所述栅堆叠 两侧且嵌于所述衬底中， 所述接触塞嵌于所述层间介质中， 其特征在 于， 所述接触塞包括第一部， 所述接触塞以所述第一部接于所述源区 和 /或所述漏区上， 所述第一部的上表面与所述栅堆叠的上表面齐平， 且所述第一部的侧壁与其底壁的夹角小于 90° 。
2. 根据权利要求 1所述的半导体器件， 其特征在于， 所述第一部 的侧壁与其底壁的夹角范围为 50° ~ 60° 。
3. 根据权利要求 1所述的半导体器件， 其特征在于， 所述第一部 包括： 质， 所述阻挡层材料为 Ta、 TaN、 Ti、 TiN或 Ru中的一种或其组合； 金属层， 所述金属层夹于所述阻挡层之中， 所述金属层材料为 W、
Al、 Cu、 TiAl中的一种或其组合。
4. 一种半导体器件的制造方法， 包括：
在（ 100 )衬底上形成栅堆叠基体， 并在所述栅堆叠基体两侧形成 源区和漏区；
在所述源区和 /或所述漏区上以晶面外延工艺形成外延层， 以使所 述外延层的侧壁与其底壁的夹角小于 90° ；
形成平坦化的层间介质， 以暴露所述外延层；
至少去除部分高度的所述外延层， 以形成接触孔；
以导电材料填充所述接触孔。
5. 根据权利要求 4所述的方法， 其特征在于， 所述外延层的高度 小于所述栅堆叠基体的高度。
6. 根据权利要求 4所述的方法， 其特征在于， 所述衬底为硅时， 所述外延层材料为 SiGe、 Ge、 SiC、掺杂或未掺杂的单晶硅或多晶硅中 的一种或其组合。
7. 根据权利要求 6所述的方法， 其特征在于， 所述外延层包括至 少两层， 相邻的两层材料不同。
8. 根据权利要求 7所述的方法， 其特征在于， 所述外延层包括第 一层和第二层且所述第二层形成于所述第一层上时， 至少去除部分高 度的所述外延层的步骤为去除所述第二层。
9. 根据权利要求 4所述的方法， 其特征在于， 在形成接触孔和填 充所述接触孔的步骤之间， 还包括： 在所述接触孔暴露的所述外延层 或所述衬底上形成接触层。
10. 根据权利要求 4 所述的方法， 其特征在于， 以导电材料填充 所述接触孔的步骤包括：
形成阻挡层， 所述阻挡层覆盖所述接触孔的侧壁和底壁， 所述阻 挡层材料为 Ta、 TaN、 Ti、 TiN或 Ru中的一种或其组合；
形成金属层， 所述金属层形成于所述阻挡层上， 所述金属层材料 为 W、 Al、 Cu、 TiAl中的一种或其组合。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106206584A (zh) * 2015-04-29 2016-12-07 华邦电子股份有限公司 存储元件及其制造方法
CN113113488A (zh) * 2020-01-10 2021-07-13 三星电子株式会社 半导体器件及其制造方法
US12635219B2 (en) 2020-01-10 2026-05-19 Samsung Electronics Co., Ltd. Semiconductor devices and methods of fabricating the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001308323A (ja) * 2000-04-26 2001-11-02 Hitachi Ltd 半導体装置の製造方法
JP2005236201A (ja) * 2004-02-23 2005-09-02 Renesas Technology Corp 半導体装置及びその製造方法
CN101047145A (zh) * 2006-03-30 2007-10-03 京东方科技集团股份有限公司 一种制备有源驱动tft矩阵中金属连线的方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6054768A (en) * 1997-10-02 2000-04-25 Micron Technology, Inc. Metal fill by treatment of mobility layers
TW497120B (en) * 2000-03-06 2002-08-01 Toshiba Corp Transistor, semiconductor device and manufacturing method of semiconductor device
US20050085072A1 (en) * 2003-10-20 2005-04-21 Kim Hyun T. Formation of self-aligned contact plugs
JP2007158176A (ja) * 2005-12-07 2007-06-21 Hitachi Ltd 半導体記憶装置およびその製造方法
JP2008004894A (ja) * 2006-06-26 2008-01-10 Elpida Memory Inc 半導体装置及びその製造方法
US7652335B2 (en) * 2007-10-17 2010-01-26 Toshiba America Electronics Components, Inc. Reversely tapered contact structure compatible with dual stress liner process
CN102024744B (zh) * 2009-09-16 2013-02-06 中国科学院微电子研究所 半导体器件及其制造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001308323A (ja) * 2000-04-26 2001-11-02 Hitachi Ltd 半導体装置の製造方法
JP2005236201A (ja) * 2004-02-23 2005-09-02 Renesas Technology Corp 半導体装置及びその製造方法
CN101047145A (zh) * 2006-03-30 2007-10-03 京东方科技集团股份有限公司 一种制备有源驱动tft矩阵中金属连线的方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106206584A (zh) * 2015-04-29 2016-12-07 华邦电子股份有限公司 存储元件及其制造方法
CN113113488A (zh) * 2020-01-10 2021-07-13 三星电子株式会社 半导体器件及其制造方法
US12635219B2 (en) 2020-01-10 2026-05-19 Samsung Electronics Co., Ltd. Semiconductor devices and methods of fabricating the same

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