WO2012136055A1 - 一种抑制闪存编程干扰的工艺方法 - Google Patents

一种抑制闪存编程干扰的工艺方法 Download PDF

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Publication number
WO2012136055A1
WO2012136055A1 PCT/CN2011/081484 CN2011081484W WO2012136055A1 WO 2012136055 A1 WO2012136055 A1 WO 2012136055A1 CN 2011081484 W CN2011081484 W CN 2011081484W WO 2012136055 A1 WO2012136055 A1 WO 2012136055A1
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Prior art keywords
ion implantation
flash memory
drain
implantation
junction
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PCT/CN2011/081484
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English (en)
French (fr)
Inventor
蔡一茂
黄如
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北京大学
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Priority to US13/510,618 priority Critical patent/US20140017870A1/en
Priority to DE112011104672T priority patent/DE112011104672T5/de
Publication of WO2012136055A1 publication Critical patent/WO2012136055A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region

Definitions

  • the present invention relates to the field of nonvolatile memory technology in the manufacturing technology of ultra large scale integrated circuits, and in particular to a process method capable of suppressing program disturb of flash memory. Background technique
  • Non-volatile memory represented by flash memory
  • flash memory is widely used in various products, such as mobile phones, notebooks, PDAs, and SSDs, because of its data retention capability during power-off and the ability to erase data multiple times.
  • Communication equipment Among them, NOR flash memory is widely used in code memory chips of mobile terminals such as mobile phones because of its fast random reading speed.
  • the normal NOR type flash memory is usually an n-channel memory cell, which is programmed by channel hot electron injection. This programming method requires a higher bit line voltage (usually 4 ⁇ 5V). At the same time, in order to obtain sufficient energy for the channel electrons to enter the memory layer, a strong electric field is required between the channel and the drain terminal.
  • the conventional method is to use a high concentration of N-type doping at the drain end to form a mutated PN junction with a substrate and a channel region having a higher P-type doping, thereby obtaining a stronger electric field (Fig. 1).
  • the channel P-type doping concentration is also greatly improved, so that the electric field in the PN junction of the channel/substrate and the drain terminal is higher and higher, and the bit line voltage is programmed. Can not drop, causing programming interference problems are very serious.
  • the schematic diagram of program disturb is shown in Figure 2. Due to programming, the word line of the selected memory cell is connected to a high potential, and the bit line is also connected to a high potential. Since the same word line or bit line is connected to a plurality of memory cells, the program disturb associated with the PN junction electric field refers to those memory cells that are co-located with the selected memory cell (connected to a high potential) and have different word lines.
  • the lightly doped drain region (LDD) process can effectively reduce the doping concentration of the drain terminal, thereby making the PN junction impurity concentration gradient between the channel and the drain terminal slow, thereby reducing the electric field and suppressing the program interference.
  • this method also causes the electric field of the channel/drain PN junction of the memory cell selected to be programmed to also be drastically reduced, thus adversely affecting programming speed and efficiency.
  • how to implement a flash memory device that can effectively avoid programming interference with a simple process is one of the problems that the flash memory technology needs to solve. Summary of the invention
  • the invention provides a flash memory process method, which can suppress programming interference of the flash memory, and the process method is compatible with the conventional method, does not increase the number of lithography plates, and has little influence on the process cost.
  • the structure and other process steps of the flash memory are consistent with the conventional flash memory technology, and the PN junction impurity gradient at the substrate/drain end is reduced by adding a donor impurity ion implantation of one tilt angle, thereby reducing the PN junction between the substrate and the drain terminal.
  • the electric field inside reduces the programming interference.
  • the impurity gradient of the PN junction at the channel/drain is maintained, thereby maintaining the PN junction electric field at the channel/drain end required for programming, ensuring programming efficiency and speed.
  • a process for suppressing flash programming interference comprising: introducing a one-step ion implantation in a standard process of n-channel flash memory, and performing a dip angle of a medium dose donor impurity ion after source-drain implantation and sidewall formation of a standard process injection.
  • the inclination, dose and energy of the ion implantation are selected within a certain range, so that the implanted donor impurities are mainly concentrated at the PN junction of the substrate and the drain end under the channel, and after being thermally annealed, the impurity can effectively compensate the substrate and
  • the P-type impurity near the PN junction of the drain terminal reduces the electric field of the PN junction between the substrate and the drain terminal, reducing program disturb.
  • the impurity species of the donor impurity ion implantation may be phosphorus, arsenic or other pentavalent elements or compounds thereof.
  • the implantation dose is preferably from Iel6/cm 2 to 5el7/cm 2 .
  • the angle of inclination of the injection is 15 Q ⁇ 45 Q , and the implantation energy is 30 keV ⁇ 50 keV.
  • the difference between the process proposed by the present invention and the lightly doped drain (LDD) process is that: the lightly doped drain region is formed to form a super shallow junction between the surface channel and the drain end (Fig. 3), and the surface is reduced. The electric field between the channel and the drain. Therefore, the method is to inject donor impurities before the sidewalls of the memory cell are formed, and the tilt angle is 0 degrees. The implant energy is smaller as the device size is reduced (usually less than 20 keV).
  • While the present invention is to maintain abrupt PN junction between the channel channel and the drain terminal, a tapered PN junction is formed between the substrate under the trench and the drain terminal, so ion implantation is performed after the sidewall spacer is formed, and A tilt injection and a certain amount of injected energy are required.
  • the difference between the present invention and the Pocket implantation process commonly used in CMOS standard processes is that the purpose of the Pocket process is to enhance the concentration gradient between the channel/substrate and the drain terminal, so that the impurity implanted is the same as the impurity type of the substrate.
  • Figure 4 For example, for the n-channel flash memory, it should be an acceptor type impurity, and the donor type impurity implanted by the present invention.
  • the present invention proposes a process method for suppressing flash programming interference, which has the following advantages: First, the process is simple, and only one step can be realized in a standard process flow, without increasing the number of lithography plates. Second, it only reduces the PN junction electric field between the substrate and the drain terminal, and does not affect the electric field between the surface channel and the drain terminal, so it does not affect the programming speed.
  • the above-described method of suppressing flash programming interference is a method of economically and efficiently improving the reliability of flash memory.
  • Figure 1 is a schematic diagram of the structure of an n-channel NOR type flash memory cell, wherein
  • 1 control gate 2 charge storage layer, 3 source terminals, 4 drain terminals, 5 substrates, 6 channels.
  • Figure 2 is a schematic diagram of programming interference when programming NOR flash arrays, where
  • FIG. 3 Schematic diagram of the lightly doped drain region (LDD) process
  • FIG. 4 is a schematic diagram of a doping process of a memory device Pocket, wherein
  • 101 Postle doping ion implantation, implanting impurities into acceptor type impurities, 102—Pocket ion implantation and P+ regions around the source and drain regions.
  • FIG. 5 is a schematic diagram of a process method for suppressing flash programming interference according to the present invention, wherein
  • the impurity implanted is a donor type impurity
  • the impurity implanted is a donor type impurity
  • 203 The ion implantation process provided by the present invention distributes a donor-type impurity formed at the substrate and the source-drain PN junction.
  • the inventors have found through research that if the PN junction impurity concentration gradient between the NOR-type flash memory substrate and the drain terminal is slowed down, the program disturbing electric field can be effectively reduced, thereby suppressing program disturb and greatly improving. Reliability of NOR type flash memory.
  • the present invention proposes a new process method for suppressing flash programming interference, which can be applied to a standard process flow by adding an ion implantation method, which can effectively reduce the programming interference electric field and improve the reliability of the flash memory.
  • the method for suppressing flash programming interference provided by the present invention is shown in FIG. 5, comprising: 201—a spacer of a memory cell, 202—the ion implantation provided by the present invention, the implant impurity is a donor type impurity, and 203—the ion implantation provided by the present invention
  • the process distributes donor-type impurities at the substrate and source-drain PN junctions.
  • the donor impurity ion implantation of the present invention is performed (as shown in FIG. 5);
  • the dose of the impurity ion implantation ranges from Iel6/cm 2 to 5el7/cm 2 ;
  • the inclination of the impurity ion implantation is 15 45 13 ; (5) the energy of the impurity ion implantation is 30 keV ⁇ 50 keV;
  • the effect of the impurity ion implantation is that the implanted donor type impurity is mainly distributed near the PN junction of the substrate and the drain end under the surface channel;

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Description

一种抑制闪存编程干扰的工艺方法 技术领域
本发明属于超大规模集成电路制造技术中的非易失存储器技术领域， 具体涉及一种可以 抑制闪存存储器编程干扰的工艺方法。 背景技术
以闪存为代表的非易失存储器因为其断电情况下的数据保持能力以及可多次擦写数据等 优点被广泛应用于各种产品中,比如手机， 笔记本， 掌上电脑和固态硬盘等存储及通讯设备。 其中 NOR闪存因为其随机读取速度快而被广泛应用在手机等移动终端的代码存储芯片中。然 而普通的 NOR型闪存通常为 n沟存储单元，采用沟道热电子注入方式编程，这种编程方式需 要较高的位线电压 （通常在 4~5V)。 同时为了使沟道电子获得足够的能量进入存储层， 需要 沟道和漏端之间形成较强的电场。 传统的方法是漏端采用高浓度的 N型掺杂， 与具有较高 P 型掺杂的衬底及沟道区形成突变 PN结， 因此获得较强的电场 （图 1 )。 随着每个技术代闪存 沟道长度的减小，沟道 P型掺杂浓度也大大提高，， 因此沟道 /衬底和漏端的 PN结内的电场越 来越高， 而且编程位线电压无法下降， 导致编程干扰问题十分严重。 编程干扰的示意图如图 2 所示， 由于编程的时候， 被选择存储单元的字线接高电位， 位线也接高电位。 由于同一字 线或者位线要接如多个存储单元， 因此和 PN结电场相关的编程干扰是指和被选择存储单元 共位线 （接高电位）， 而字线不一样的那些存储单元。
由于编程干扰对闪存的可靠性带来重要的影响， 因此如何通过结构， 工艺和电路的方法 来抑制编程干扰成为闪存生产和研发的重要技术。 比如采用轻掺杂漏区 （LDD) 工艺可以有 效降低漏端的掺杂浓度， 从而使得沟道和漏端之间的 PN结杂质浓度梯度变缓， 从而减小电 场， 达到抑制编程干扰的作用。 然而这种方法同样会使得被选择编程的存储单元的沟道 /漏端 PN结的电场也急剧减小， 因此对编程速度和效率都带来不利的影响。 总而言之， 如何采用简单的工艺实现可以有效避免编程干扰的闪存器件是闪存存储器技 术亟待解决的难题之一。 发明内容
本发明提供一种闪存的工艺方法， 可以抑制闪存的编程干扰， 并且该工艺方法和传统方 法兼容， 不增加光刻版数， 对工艺成本影响不大。 其中， 闪存的结构和其他工艺步骤和传统 的闪存技术一致，通过增加一步倾角的施主杂质离子注入来减小衬底 /漏端的 PN结杂质梯度， 从而减小衬底和漏端之间 PN结内的电场， 减小编程干扰。 与此同时保持沟道 /漏端的 PN结 的杂质梯度， 从而维持编程所需的沟道 /漏端的 PN结电场， 保证编程效率和速度。
上述目的是通过如下技术方案实现的：
一种抑制闪存编程干扰的工艺方法， 包括： 在 n沟闪存的标准工艺中引入一步离子注入， 既在标准工艺的源漏注入以及侧墙形成以后， 再进行一次倾角的中等剂量的施主杂质离子注 入。 该离子注入的倾角、 剂量和能量在一定范围内选择， 使得注入的施主杂质主要集中在沟 道下面的衬底和漏端的 PN结处， 经过热退火扩散以后， 该杂质能够有效补偿衬底和漏端 PN 结附近的 P型杂质， 从而使得衬底和漏端之间的 PN结电场降低， 减小编程干扰。
上述施主杂质离子注入的杂质种类可以是磷、 砷或者是其他五价元素或者其化合物。 注 入剂量在 Iel6/cm2~5el7/cm2为宜。 注入的倾角为 15Q~45Q为宜,注入能量为 30keV~50keV。
本发明提出的工艺方法和轻掺杂漏区 （LDD) 工艺的区别在于： 轻掺杂漏区是为了形成 表面沟道和漏端之间缓变的超浅结 （图 3 )， 减小表面沟道和漏端之间的电场。 因此其工艺方 法是在存储单元的侧墙形成之前注入施主杂质， 倾角为 0度， 注入能量随着器件尺寸的缩小 越小越好 （通常要小于 20keV)。 而本发明是为了保持表面沟道和漏端之间的突变 PN结， 而 在沟道下面的衬底和漏端之间形成缓变的 PN结， 因此离子注入是在侧墙形成以后， 并且需 要倾角注入和一定的注入能量。
本发明和 CMOS标准工艺里常用的 Pocket注入工艺的区别在于： Pocket工艺的目的是为 了增强沟道 /衬底和漏端之间的浓度梯度， 因此注入的杂质是和衬底的杂质类型是一样的 （图 4)。 比如对于 n沟闪存注入的应该是受主型杂质， 而本发明注入的施主型杂质。 与现有技术相比， 本发明提出抑制闪存编程干扰的工艺方法有如下优势： 第一， 其工艺 简单， 只需在标准工艺流程中加入一步即可实现， 无需增加光刻版数。 第二， 它仅仅降低衬 底和漏端之间 PN结电场， 不会对表面沟道和漏端之间的电场造成影响， 因此不会影响编程 速度。
因此， 上述抑制闪存编程干扰的工艺方法是经济且高效的提高闪存可靠性的方法。 附图说明
通过附图所示， 本发明的上述及其它目的、 特征和优势将更加清晰。 在全部附图中相同 的附图标记指示相同的部分。 并未刻意按实际尺寸等比例缩放绘制附图， 重点在于示出本发 明的主旨。
图 1 为 n沟 NOR型闪存存储单元结构示意图， 其中
1一控制栅， 2 电荷存储层， 3 源端， 4 漏端， 5 衬底， 6 沟道。
图 2 为 NOR型闪存阵列编程时编程干扰示意图， 其中
01_被选择位线， 02_未被选择位线， 03_被选择字线， 04_未被选择字线， 05_被选 择编程的存储单元， 06—受到漏端 PN结电场相关的编程干扰的存储单元。
图 3轻掺杂漏区 （LDD) 工艺示意图， 其中
001—轻掺杂漏区离子注入， 注入杂质为施主型杂质， 002 轻掺杂漏区离子注入形成的 和沟道相接的低浓度 N区。
图 4为存储器件 Pocket掺杂工艺示意图， 其中
101— Pocket掺杂离子注入， 注入杂质为受主型杂质， 102— Pocket离子注入形成的和源 漏区周边的 P+区。
图 5 本发明提出的抑制闪存编程干扰的工艺方法示意图， 其中
201—存储单元的侧墙， 202—本发明提供的离子注入， 注入杂质为施主型杂质， 203— 本发明提供的离子注入工艺在衬底和源漏 PN结处形成的施主型杂质分布。 具体实施方式
为使本发明的上述目的、 特征和优点能够更加明显易懂， 下面结合附图对本发明的具体 实施方式做详细的说明。
在下面的描述中阐述了很多具体细节以便于充分理解本发明， 但是本发明还可以采用其 他不同于在此描述的其它方式来实施， 本领域技术人员可以在不违背本发明内涵的情况下做 类似推广， 因此本发明不受下面公开的具体实施例的限制。
其次， 本发明结合示意图进行详细描述， 在详述本发明实施例时， 为便于说明， 表示器 件结构的剖面图会不依一般比例作局部放大， 而且所述示意图只是示例， 其在此不应限制本 发明保护的范围。 此外， 在实际制作中应包含长度、 宽度及深度的三维空间尺寸。
正如本发明背景技术的介绍，发明人经过研究发现，若将 NOR型闪存衬底和漏端之间的 PN结杂质浓度梯度变缓， 可以有效减小编程干扰电场， 从而抑制编程干扰， 大大提高 NOR 型闪存的可靠性。
基于此， 本发明提出一种新的抑制闪存编程干扰的工艺方法， 可以运用在标准工艺流程 中加入离子注入的方法， 能够有效降低编程干扰电场， 提高闪存的可靠性。
本发明提供的抑制闪存编程干扰的工艺方法图 5 所示， 包括： 201—存储单元的侧墙， 202—本发明提供的离子注入， 注入杂质为施主型杂质， 203—本发明提供的离子注入工艺在 衬底和源漏 PN结处形成的施主型杂质分布。
下面结合附图 5详细说明本发明提供的抑制闪存编程干扰工艺方法的优选实施例。
( 1 ) 在本发明工艺步骤之前的工艺均采用 NOR型闪存标准工艺流程；
(2)在标准工艺流程的侧墙形成以后， 进行本发明的施主杂质离子注入（如图 5所示）；
(3 ) 该杂质离子注入的剂量范围在 Iel6/cm2~5el7/cm2;
(4) 该杂质离子注入的倾角为 15 4513; ( 5 ) 该杂质离子注入的能量为 30keV~50keV;
(6)该杂质离子注入形成的效果为被注入的施主型杂质主要分布在表面沟道下面的衬底 和漏端的 PN结附近；
(7) 本发明工艺步骤之后的工艺均采用 NOR型闪存标准工艺流程。
以上所述， 仅是本发明的较佳实施例而已， 并非对本发明作任何形式上的限制。
虽然本发明已以较佳实施例披露如上， 然而并非用以限定本发明。 任何熟悉本领域的技 术人员， 在不脱离本发明技术方案范围情况下， 都可利用上述揭示的方法和技术内容对本发 明技术方案作出许多可能的变动和修饰， 或修改为等同变化的等效实施例。 因此， 凡是未脱 离本发明技术方案的内容， 依据本发明的技术实质对以上实施例所做的任何简单修改、 等同 变化及修饰， 均仍属于本发明技术方案保护的范围内。

Claims

权 利 要 求
1. 一种抑制闪存编程干扰的工艺方法， 其特征在于， 闪存的标准工艺中引入一步离子注入， 既在标准工艺的源漏注入以及侧墙形成以后， 再进行离子杂质倾角注入， 使得注入的离 子杂质集中在沟道下面的衬底和源漏端的 PN结处。
2. 如权利要求 1 所述的方法， 其特征在于： 注入离子杂质为对于硅为施主型杂质， 如砷、 磷及其化合物。
3. 如权利要求 2所述的离子注入工艺， 其特征在于： 离子注入的能量范围在 30keV~50keV。
4. 如权利要求 2所述的离子注入工艺， 其特征在于： 离子注入的倾角范围在 150~45Q。
5. 如权利要求 2 所述的离子注入工艺， 其特征在于： 离子注入的注入剂量范围在 lel6/cm2~5el7/cm
PCT/CN2011/081484 2011-04-06 2011-10-28 一种抑制闪存编程干扰的工艺方法 WO2012136055A1 (zh)

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