WO2012129956A1 - 防止延迟锁相环错误锁定的方法及系统 - Google Patents

防止延迟锁相环错误锁定的方法及系统 Download PDF

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Publication number
WO2012129956A1
WO2012129956A1 PCT/CN2011/085113 CN2011085113W WO2012129956A1 WO 2012129956 A1 WO2012129956 A1 WO 2012129956A1 CN 2011085113 W CN2011085113 W CN 2011085113W WO 2012129956 A1 WO2012129956 A1 WO 2012129956A1
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Prior art keywords
phase detector
phase
delay
frequency dividing
dividing circuit
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PCT/CN2011/085113
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English (en)
French (fr)
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亚历山大
刘天志
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山东华芯半导体有限公司
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Publication of WO2012129956A1 publication Critical patent/WO2012129956A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/14—Preventing false-lock or pseudo-lock of the PLL

Definitions

  • the invention belongs to the field of delay phase locked loops, and more particularly to a method and system for preventing delay locked phase of a phase locked loop.
  • the delay phase locked loop is a delayed output system that generates an input clock through a delay line.
  • Step 1 The output clock of the delay phase-locked loop generates a feedback clock after passing through the clock distribution network, and the feedback clock is re-entered into the delay phase-locked loop.
  • Step 2 The phase detector of the delay phase locked loop samples and compares the input clock and the feedback clock, and outputs the comparison result to the control logic circuit.
  • Step 3 The control logic circuit adjusts the delay of the variable delay line according to the comparison result, and realizes a zero transmission delay between the feedback clock and the input clock, so that the deviation between the clock pins distributed throughout the system is minimized.
  • the zero transmission delay in step 3 is that the previous clock signal is the output clock of the delay phase-locked loop in step 1. After a number of delays, it can still be the same as the following clock signal.
  • the input clock of the system tends to have a large jitter, that is, the input clock phase is jittered near an equilibrium value, and the feedback clock of the delay-locked loop is delayed. It is a delayed output of the input clock.
  • the feedback clock inherits the jitter of the input clock, which further exacerbates the instability of the system. Therefore, the delay phase-locked loop needs to be locked.
  • the control logic circuit forces the variable delay line to continuously increase.
  • the phase detector samples the feedback clock through the rising edge of the input clock, and then determines whether to lock according to the change of the sampled output signal:
  • the control logic circuit directly adjusts the length of the variable delay line according to the sampling output signal of the phase detector: when the sampling output signal is 1, the length of the variable delay line is increased, and when the sampling output signal is 0, the variable delay line is reduced.
  • the length is such that the phase difference between the input clock and the feedback clock is zero.
  • the present invention provides a method and system for preventing delay lock of a phase-locked loop, which can effectively prevent a delay phase-locked loop mis-lock phenomenon that occurs when an input clock is shaken.
  • the technical solution of the present invention is:
  • the present invention is a method for preventing delay lock of a delay phase locked loop, which is special in that the method includes the following steps:
  • the feedback clock is differentially divided by the feedback clock frequency dividing circuit, and two differential feedback clocks are obtained, which are respectively input to the I phase detector and the II phase detector of the control logic circuit;
  • I phase detector and II phase detector sample and compare the divided input clock and two differential feedback clocks, when the output of I phase detector and II phase detector occurs from 1 to 0 or from 0 to 1 When the flipping is performed, a lock signal is issued;
  • step 2.2 if the delayed differential feedback clock has a sampling result of 1, the output result of the I phase detector is used to control the delay chain increase and decrease. If the delayed differential feedback clock has a sampling result of 0, the II is used. Phaser The output results control the delay chain increase and decrease.
  • the invention also provides a system for preventing delay lock of a phase-locked loop:
  • the special feature is that: the system comprises an input clock frequency dividing circuit, a feedback clock frequency dividing circuit and a control logic circuit, an input clock frequency dividing circuit and a feedback clock minute.
  • the frequency circuit is further divided into a control logic circuit.
  • the above control logic circuit comprises an I phase detector, a phase detector, a delay unit, a flip flop, a lock judging circuit and a multiplexer, the input clock frequency dividing circuit is connected to the I phase detector, and the feedback clock frequency dividing circuit is connected.
  • the II phase detector, the I phase detector and the II phase detector respectively are connected to the lock determination circuit, the input clock frequency dividing circuit is connected to the trigger, and the feedback clock frequency dividing circuit is connected to the trigger through the delay unit,
  • the comparator, the II phase detector and the trigger are respectively connected to the multiplexer.
  • the above delay unit adopts a NAND gate delay unit.
  • the above input clock frequency dividing circuit and feedback clock frequency dividing circuit adopt a flip-flop.
  • the invention divides the input clock and the feedback clock to eliminate the falling edge information, so the invention can effectively prevent the delay phase locked loop error phenomenon occurring when the input clock is shaken, and the invention is compatible with the existing related technologies. Good sex, simple locking process, simple control logic, and accelerated locking process. DRAWINGS
  • Figure 1 is a schematic diagram of a delay phase locked loop
  • FIG. 2 is a locking process diagram of a conventional delay phase locked loop
  • Figure 3 is a diagram of a mislock process of a conventional delay phase locked loop when the feedback clock has jitter
  • Figure 4 is a schematic view of the principle of the present invention.
  • Figure 5 is a process diagram of the locking process of the present invention.
  • Figure 6 is a second process diagram of the locking process of the present invention.
  • FIG. 7 is a schematic diagram showing selection of an increase and decrease signal of the locking process of the present invention.
  • FIG. 8 is a schematic diagram of selection of a second increase and decrease signal of the locking process of the present invention.
  • FIG. 9 is a block diagram of the control logic circuit of the present invention.
  • the invention divides the input clock of the input phase detector and the feedback clock to lock the frequency division signal.
  • the specific process is as follows: See Figures 4 ⁇ 6, (1) The delay continues to increase:
  • the I phase detector and the II phase detector sample and compare the divided input clock, the divided feedback clock, and the divided feedback clock. When the output of the I phase detector and the II phase detector occurs from 1 to 0. Or when a rollover from 0 to 1, a lock signal is issued.
  • the divided feedback clock and the divided feedback clock are two clocks with opposite phases.
  • the control logic can be fine-tuned based on the sample output.
  • the output result of the I phase detector is used to control the delay chain increase and decrease. If the sampling result of the delayed frequency-divided feedback clock is 0, the output result of the II phase detector is controlled.
  • variable delay line i.e., the "variable delay line” described in the background art
  • the delay locked loop error locking system of the present invention comprises an input clock frequency dividing circuit, a feedback clock frequency dividing circuit and a control logic circuit, wherein the input clock frequency dividing circuit and the feedback clock frequency dividing circuit are respectively connected to the control logic circuit.
  • the input clock frequency dividing circuit and the feedback clock frequency dividing circuit have the same circuit structure, and various existing frequency dividing circuit structures, such as a flip-flop, can be used.
  • the control logic circuit of the present invention comprises an I phase detector, a phase detector, a delay unit, a flip-flop, a lock judging circuit and a multiplexer, and the input clock frequency dividing circuit is connected to the I phase detector, and the feedback
  • the clock frequency dividing circuit is connected to the II phase detector, the I phase detector and the II phase detector are respectively connected to the lock determining circuit, the input clock frequency dividing circuit is connected to the trigger, and the feedback clock frequency dividing circuit is connected to the trigger through the delay unit.
  • phase detector, the II phase detector, the flip-flop, the lock judging circuit and the multiplexer can adopt the structure in the prior art control logic circuit, only in the A delay unit is added between the feedback clock frequency dividing circuit and the flip-flop, and the delay unit can adopt various existing delay circuits, such as a NAND gate delay unit.
  • the working principle of the system of the present invention is: After the input clock is divided by the input clock frequency dividing circuit, the obtained divided frequency input clocks are respectively input to the I phase detector and the II phase detector of the control logic circuit; the feedback clock is divided by the feedback clock. After the circuit is differentially divided, two differential feedback clocks are obtained.
  • One differential feedback clock is the frequency-divided feedback clock, the input phase-of-control circuit of the control logic circuit, the other is the frequency-divided feedback clock, and the input control logic circuit is II.
  • Phase detector; I phase detector and II phase detector sample and compare the divided input clock, the divided feedback clock and the divided feedback clock, when the output of the I phase detector and the II phase detector occurs from 1 to 0. Or when the flip is from 0 to 1, the lock judging circuit issues a lock signal.
  • the divided-frequency feedback clock is delayed by a delay of 73 ⁇ 4 lines as the clock input of the flip-flop, and the divided-frequency input clock is used as the data input of the flip-flop, so that the delayed frequency-divided feedback clock is divided into the input clock.
  • Latch select according to the result of the flip-flop. If the latch result is 1, the I-oil multi-way selector selects the output of the I phase detector to control the increase or decrease of the delay chain. If the latch result is 0, then The multiplexer selects the output of the II phase detector to control the increase and decrease of the delay chain, and performs fine adjustment operation to ensure correct locking.

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Description

防止延迟锁相环错误锁定的方法及系统
¾ ^领域
本发明属延迟锁相环领域，尤其涉及一种防止延迟锁相环错误锁定的方法及其 系统。
背景
延迟锁相环是一种通过延时线产生输入时钟的延时输出系统。
参见图 1， 延迟锁相环的具体的基本工作原理如下：
歩骤 1 : 延迟锁相环的输出时钟经过时钟分布网络后产生反馈时钟， 反馈时钟 重新输入延迟锁相环，
歩骤 2: 延迟锁相环的鉴相器对输入时钟和反馈时钟进行抽样、 比较， 并将比 较结果输出给控制逻辑电路，
歩骤 3: 控制逻辑电路根据比较结果调整可变延时线的延时， 实现反馈时钟与 输入时钟为零传输延迟， 使分布于整个系统的时钟引脚间的偏差最小。
其中歩骤 3中的零传输延迟：是指前面的时钟信号即歩骤 1中延迟锁相环的输出 时钟， 经过若干延时后， 依然能够与后面的时钟信号相同歩。
由于现代高频时钟系统时钟在传递过程中很难避免干扰， 因此， 系统的输入时 钟往往会有很大的抖动， 即输入时钟相位是在一个平衡值附近抖动， 而延迟锁相环 的反馈时钟是输入时钟的一个延时输出， 反馈时钟会继承输入时钟的抖动， 由此更 加剧了系统的不稳定， 因此需要对延迟锁相环的进行锁定。
参见图 2， 传统延迟锁相环的主要锁定流程如下：
1 )延时持续增加阶段：
延迟锁相环经过重置后， 控制逻辑电路强制可变延时线持续增加， 鉴相器通过 输入时钟的上升沿对反馈时钟进行采样， 再根据采样输出信号的变化来判断是否锁 定：
由于可变延时线的长度在持续增加，所以反馈时钟与输入时钟的相位差持续增 力口。 当采样输出信号发生从 1到 0的变化时， 判定遇到反馈时钟上升沿， 即认为进入 锁定状态， 然后进入微调阶段； 2)微调阶段
控制逻辑电路直接根据鉴相器的采样输出信号调节可变延时线的长度：当采样 输出信号为 1时增加可变延时线的长度， 当采样输出信号为 0时减少可变延时线的长 度， 从而保持输入时钟与反馈时钟的相位差为 0。
然而， 参见图 3， 当采用上述延迟锁相环的锁定流程时， 当反馈时钟的下降沿 被采样时，若采样输出信号为 1，在输入时钟或者反馈时钟有抖动时，采样输出信号 变为 0，则控制逻辑电路会错误的发出锁定信号，会导致延迟锁相环错误锁定在下降 沿（如图 3中的圆圈处)。
发明内容
为了解决背景技术中存在的技术问题，本发明提供了一种防止延迟锁相环错误 锁定的方法及其系统， 其可有效防止在输入时钟发生抖动时出现的延迟锁相环错锁 现象。
本发明的技术解决方案是： 本发明为一种防止延迟锁相环错误锁定的方法， 其 特殊之处在于： 该方法包括以下歩骤：
1 )延时持续增加阶段：
1.1 )输入时钟经输入时钟分频电路分频后， 所得到的分频输入时钟分别输入 控制逻辑电路的 I鉴相器和 II鉴相器；
1.2)反馈时钟经反馈时钟分频电路进行差分分频后， 得到两路差分反馈时钟， 分别输入控制逻辑电路的 I鉴相器和 II鉴相器；
1.3) I鉴相器和 II鉴相器对分频输入时钟和两路差分反馈时钟进行采样、 比 较后，当 I鉴相器和 II鉴相器的输出发生从 1到 0或从 0到 1的翻转时，发出锁定信号;
2)微调阶段。
上述歩骤 2) 中的具体歩骤如下：
2.1 )对歩骤 1.2) 中的分频后得到的一路差分反馈时钟进行延迟，
2.2)对该延迟的差分反馈时钟进行采样， 根据对延迟的差分反馈时钟的采样 结果， 决定采用不同的采样输出进行微调。
上述歩骤 2.2) 中若延迟的差分反馈时钟的的采样结果为 1， 采用 I鉴相器的输 出结果控制延时链增减，若延迟的差分反馈时钟的的采样结果为 0，采用 II鉴相器的 输出结果控制延时链增减。
本发明还提供一种防止延迟锁相环错误锁定的系统： 其特殊之处在于： 该系统 包括输入时钟分频电路、 反馈时钟分频电路和控制逻辑电路， 输入时钟分频电路和 反馈时钟分频电路分另嗾入控制逻辑电路。
上述控制逻辑电路包括 I鉴相器、 II鉴相器、延时单元、触发器、 锁定判断电 路和多路选择器， 输入时钟分频电路接入 I鉴相器， 反馈时钟分频电路接入 II鉴相 器， I鉴相器和 II鉴相器分别接入锁定判断电路， 输入时钟分频电路接入触发器， 所述反馈时钟分频电路通过延时单元接入触发器， I鉴相器、 II鉴相器和触发器分 别接入多路选择器。
上述延时单元采用与非门延时单元。
上述输入时钟分频电路和反馈时钟分频电路均采用触发器。
本发明的优点如下：
本发明将输入时钟和反馈时钟进行分频处理， 从而消除下降沿信息， 因此本发 明可以有效防止在输入时钟发生抖动时出现的延迟锁相环错锁现象， 同时本发明与 现有相关技术兼容性好， 锁定过程简单， 控制逻辑简单， 并且可以加速锁定过程。 附图说明
图 1是延迟锁相环的原理图；
图 2是传统延迟锁相环的锁定过程图；
图 3是反馈时钟有抖动时传统延迟锁相环的错锁过程图；
图 4是本发明的原理示意图；
图 5是本发明锁定过程一过程图；
图 6是本发明锁定过程二过程图；
图 7是本发明锁定过程一增减信号选择示意图；
图 8是本发明锁定过程二增减信号选择示意图；
图 9是本发明的控制逻辑电路的结构图。
具体实 I»式
本发明是将输入鉴相器的输入时钟和反馈时钟进行分频， 对分频信号进行锁 定。 其具体过程如下： 参见图 4~6， ( 1 )延时持续增加阶段：
( 1.1 ) 输入时钟经输入时钟分频电路分频后， 所得到的分频输入时钟分别输 入控制逻辑电路的 I鉴相器和 II鉴相器；
( 1.2) 反馈时钟经反馈时钟分频电路进行差分分频后， 得到两路差分反馈时 钟， 一路差分反馈时钟为分频反馈时钟反， 输入控制逻辑电路的 I鉴相器， 另一路 为分频反馈时钟， 输入控制逻辑电路的 II鉴相器；
( 1.3 ) I鉴相器和 II鉴相器对分频输入时钟、 分频反馈时钟反和分频反馈时 钟进行采样、 比较， 当 I鉴相器和 II鉴相器的输出发生从 1到 0或从 0到 1的翻转时， 发出锁定信号。
分频反馈时钟反和分频反馈时钟是相位相反的两路时钟。
参见 7、 8， (2)微调阶段：
由于 I鉴相器和 II鉴相器的输出有从 1到 0或从 0到 1的翻转的两种不同锁定状 态， 因此需要判断锁定在何种状态？ ， 控制逻辑电路才能根据采样输出进行微调。
2.1 )对歩骤 1.2) 中的分频后得到的分频反馈时钟进行延迟，
2.2)对该延时分频反馈时钟进行采样， 根据对延迟的分频反馈时钟的采样结 果， 决定采用不同的采样输出， 保证正确锁定。
若延迟的分频反馈时钟的采样结果为 1， 采用 I鉴相器的输出结果控制延时链 增减，若延迟的分频反馈时钟的采样结果为 0，采用 II鉴相器的输出结果控制延时链
(即背景技术所述 "可变延时线"）增减。
参见图 4， 本发明的延迟锁相环错误锁定的系统包括输入时钟分频电路、 反馈 时钟分频电路和控制逻辑电路， 述输入时钟分频电路和反馈时钟分频电路分别接入 控制逻辑电路， 输入时钟分频电路和反馈时钟分频电路的电路结构相同， 可采用现 有的各种分频电路结构， 如触发器的等。
参见图 9， 本发明的控制逻辑电路包括 I鉴相器、 II鉴相器、 延时单元、 触发 器、 锁定判断电路和多路选择器， 输入时钟分频电路接入 I鉴相器， 反馈时钟分频 电路接入 II鉴相器， I鉴相器和 II鉴相器分别接入锁定判断电路， 输入时钟分频电 路接入触发器， 反馈时钟分频电路通过延时单元接入触发器， I鉴相器、 II鉴相器 和触发器分别接入多路选择器， 本发明为提高于现有相关技术的兼容性， I鉴相器、 II鉴相器、触发器、锁定 判断电路和多路选择器均可采用现有技术的控制逻辑电路中的结构， 只是在反馈时 钟分频电路和触发器之间增加了延时单元，而延时单元可采用现有的各种延时电路， 如与非门延时单元等。
本发明的系统工作原理是： 输入时钟经输入时钟分频电路分频后，所得到的分 频输入时钟分别输入控制逻辑电路的 I鉴相器和 II鉴相器； 反馈时钟经反馈时钟分 频电路进行差分分频后， 得到两路差分反馈时钟， 一路差分反馈时钟为分频反馈时 钟反， 输入控制逻辑电路的 I鉴相器， 另一路为分频反馈时钟， 输入控制逻辑电路 的 II鉴相器； I鉴相器和 II鉴相器对分频输入时钟、 分频反馈时钟反和分频反馈时 钟进行采样、 比较， 当 I鉴相器和 II鉴相器的输出发生从 1到 0或从 0到 1的翻转时， 锁定判断电路发出锁定信号。
微调时， 将分频反馈时钟通过延时单7¾行延时， 作为触发器的时钟输入， 利 用分频输入时钟作为触发器的数据输入， 使此延时的分频反馈时钟对分频输入时钟 锁存，根据触发器的结果进行选择，如果锁存结果为 1，贝 I油多路选择器选择用 I鉴 相器的输出控制延时链的增减，如果锁存结果为 0，则由多路选择器选择用 II鉴相器 的输出控制延时链的增减， 进行微调操作， 保证正确锁定。

Claims

权利要求书
1、一种防止延迟锁相环错误锁定的方法， 其特征在于： 该方法包括以下歩骤: 1 )延时持续增加阶段：
1.1 )输入时钟经输入时钟分频电路分频后， 所得到的分频输入时钟分别输入 控制逻辑电路的 I鉴相器和 II鉴相器；
1.2)反馈时钟经反馈时钟分频电路进行差分分频后， 得到两路差分反馈时钟， 分别输入控制逻辑电路的 I鉴相器和 II鉴相器；
1.3 ) I鉴相器和 II鉴相器对分频输入时钟和两路差分反馈时钟进行采样、 比 较后，当 I鉴相器和 II鉴相器的输出发生从 1到 0或从 0到 1的翻转时，发出锁定信号;
2)微调阶段。
2、根据权利要求 1所述的防止延迟锁相环错误锁定的方法， 其特征在于： 所述 歩骤 2) 中的具体歩骤如下：
2.1 )对歩骤 1.2) 中的分频后得到的一路差分反馈时钟进行延迟，
2.2)对该延时差分反馈时钟进行采样， 根据对延迟的差分反馈时钟的采样结 果， 决定采用不同的采样输出进行微调。
3、根据权利要求 2所述的防止延迟锁相环错误锁定的方法， 其特征在于： 所述 歩骤 2.2) 中若延迟的差分反馈时钟的的采样结果为 1， 采用 I鉴相器的输出结果控 制延时链增减，若延迟的差分反馈时钟的的采样结果为 0，采用 II鉴相器的输出结果 控制延时链增减。
4、 一种防止延迟锁相环错误锁定的系统： 其特征在于： 该系统包括输入时钟 分频电路、 反馈时钟分频电路和控制逻辑电路， 所述输入时钟分频电路和反馈时钟 分频电路分别接入控制逻辑电路。
5、根据权利要求 4所述的防止延迟锁相环错误锁定的系统： 其特征在于： 所述 控制逻辑电路包括 I鉴相器、 II鉴相器、 延时单元、 触发器、 锁定判断电路和多路 选择器， 所述输入时钟分频电路接入 I鉴相器， 所述反馈时钟分频电路接入 II鉴相 器， 所述 I鉴相器和 II鉴相器分另嗾入锁定判断电路， 所述输入时钟分频电路接入 触发器， 所述反馈时钟分频电路通过延时单元接入触发器， 所述 I鉴相器、 II鉴相 器和触发器分别接入多路选择器。
6、根据权利要求 5所述的防止延迟锁相环错误锁定的系统： 其特征在于： 所述 延时单元采用与非门延时单元。
7、 根据权利要求 3或 4或 5或 6所述的防止延迟锁相环错误锁定的系统： 其特征 在于： 所述输入时钟分频电路和反馈时钟分频电路均采用触发器。
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