WO2012117533A1 - Procédé de métallisation de trous d'interconnexion et substrat fabriqué au moyen d'un tel procédé - Google Patents

Procédé de métallisation de trous d'interconnexion et substrat fabriqué au moyen d'un tel procédé Download PDF

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Publication number
WO2012117533A1
WO2012117533A1 PCT/JP2011/054725 JP2011054725W WO2012117533A1 WO 2012117533 A1 WO2012117533 A1 WO 2012117533A1 JP 2011054725 W JP2011054725 W JP 2011054725W WO 2012117533 A1 WO2012117533 A1 WO 2012117533A1
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WO
WIPO (PCT)
Prior art keywords
hole
plating
substrate
substrate intermediate
plated
Prior art date
Application number
PCT/JP2011/054725
Other languages
English (en)
Japanese (ja)
Inventor
典明 種子
陽一 齋藤
秀吉 瀧井
Original Assignee
株式会社メイコー
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社メイコー filed Critical 株式会社メイコー
Priority to KR1020137022739A priority Critical patent/KR101475474B1/ko
Priority to PCT/JP2011/054725 priority patent/WO2012117533A1/fr
Priority to CN2011800688393A priority patent/CN103403228A/zh
Publication of WO2012117533A1 publication Critical patent/WO2012117533A1/fr

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    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • C25D5/022—Electroplating of selected surface areas using masking means
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
    • H05K3/424—Plated through-holes or plated via connections characterised by electroplating method by direct electroplating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/427—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates

Definitions

  • the present invention relates to a plating method applied in a through hole and a substrate manufactured using the same.
  • a through hole is provided to penetrate the substrate, and the inner surface is plated with copper or the like (hereinafter described as copper).
  • the continuity is achieved by holes.
  • This through hole is formed by making a hole in the double-sided copper-clad plate or multilayer shield plate with a drill or the like.
  • the plating treatment is performed on the copper foil layer exposed on the substrate surface including the inner surface of the through hole after removing smear after drilling. As the plating treatment, there are electrolytic plating and electroless plating.
  • a substrate in electrolytic plating, a substrate is immersed in a plating solution, power is supplied through a copper foil layer, and copper is electrodeposited on the both surfaces of the substrate and the inner surface of the through hole for surface treatment.
  • the substrate is immersed in a plating solution. That is, in both electrolytic plating and electroless plating, copper plating is performed on both surfaces of the substrate, and at the same time, copper plating is also applied in the through holes.
  • a copper layer of several ⁇ m to several tens of ⁇ m is generally formed on the inner surface of the through hole.
  • the present invention provides a through-hole plating method capable of plating only the inner surface of a through-hole in a simple, quick and inexpensive manner and a substrate manufactured using the same.
  • a substrate intermediate having a through hole penetrating an insulating layer and two conductive masks having an opening penetrating at a position corresponding to the through hole are used, and the position of the opening is passed through the through hole.
  • Forming and immersing the object to be plated in a plating solution depositing a metal on the entire surface of the object to be plated including the inner surface of the through hole, and performing plating treatment from the substrate intermediate to the conductive mask.
  • a through-hole plating method is provided, which is characterized by removing the metal.
  • a conductor pattern is formed on at least one side of the insulating layer before covering the substrate intermediate with the conductive mask.
  • the conductive mask is brought into close contact with both the front and back surfaces of the substrate intermediate.
  • this invention is a board
  • both surfaces of the substrate intermediate are covered with the conductive mask, it is possible to prevent the metal from adhering to both surfaces of the substrate intermediate in the plating process. Therefore, the handleability in the subsequent process is improved, and the workability is improved when a pattern is formed on the substrate intermediate, for example.
  • the conductive mask is provided with an opening at a position corresponding to the through hole, the inner surface of the through hole is exposed in the plating solution. For this reason, it is possible to efficiently perform the plating process only in the through hole, and it is possible to control the plating thickness only in the through hole.
  • a conductor pattern can be formed on at least one side of the insulating layer before plating metal is applied to the through hole. For this reason, it is possible to efficiently perform the plating process only on the inside of the through hole without plating metal adhering to the conductor pattern even on the substrate intermediate on which the conductor pattern is formed in advance.
  • the conductive mask is in close contact with both the front and back surfaces of the substrate intermediate, it is possible to reliably prevent the metal from adhering to both the front and back surfaces of the substrate intermediate during the plating process.
  • the plated metal covers the front and back surfaces of the substrate intermediate with an insulating layer with a conductive mask, and adheres only to the inside of the through hole by plating with the inner surface of the through hole exposed. For example, when a pattern is formed on the substrate intermediate, the workability is improved.
  • the plating methods include electrolytic plating and electroless plating.
  • electrolytic plating a case where electrolytic plating is used will be described.
  • the present invention can also be realized using electroless plating.
  • the object to be plated 2 is immersed in the electrolytic cell 1.
  • the electrolytic cell 1 is filled with the plating solution 3.
  • the plating solution 3 contains metal ions such as copper ions.
  • the object to be plated 2 is composed of a substrate intermediate 4 and a conductive mask 5.
  • the substrate intermediate 4 has a plate-like insulating layer 6, and one or a plurality of (three in the drawing) through holes 7 are formed in the insulating layer 6.
  • Conductive patterns 8 are formed on both surfaces of the insulating layer 6.
  • the conductive mask 5 is provided with a plurality of openings 9 penetrating, and at least the openings 9 are provided in corresponding positions with respect to the through holes 7 formed in the insulating layer 6.
  • the substrate intermediate body 4 is covered with the conductive mask 5 sandwiching both front and back surfaces, and is in close contact with at least a part of the conductive mask 5.
  • the conductive pattern 5 is in close contact with the surface of the conductive pattern 8, but when the conductive pattern 8 is not formed, the conductive mask 5 is the insulating layer 6 (more specifically, a copper foil applied to the surface of the insulating layer 6). Adheres closely to the surface.
  • the conductive mask 5 is in close contact with the land.
  • the conductive mask 5 is at least in close contact with the position protruding to the outermost side of the substrate intermediate 4.
  • the conductive mask 5 may be a metal, or may be a resin in which a metal is stretched on one side or both sides.
  • the conductive mask 5 may be plate-shaped or film-shaped such as copper foil. In the case of a resin, there is no particular limitation as long as the resin is not attacked by the plating solution 3.
  • the object to be plated 2 formed in this way is immersed in the plating solution 3 of the electrolytic cell 1 as described above, and is energized from the power source 10 using the conductive mask 5 as an electrode.
  • further electrodes 11 are provided on both side walls of the electrolytic cell 1.
  • the plating metal 12 in the plating solution adheres to the entire surface of the object to be plated 2 as a metal film. That is, the plating metal 12 adheres to the exposed surface of the conductive mask 5 and the inner surface of the through hole 7.
  • the substrate 2 to be plated is taken out of the plating solution 3 and the conductive mask 5 is removed to obtain the substrate 13 in which only the inner surface of the through hole 7 is plated as shown in FIG. Can do.
  • both surfaces of the substrate intermediate 4 are covered with the conductive mask 5, it is possible to prevent the metal from adhering to both the front and back surfaces of the substrate intermediate 4 during the plating process. Therefore, the handleability in the post process is improved, and for example, when the pattern is formed on the substrate intermediate 4 in the post process, the workability is improved.
  • the opening part 9 is provided in the position corresponding to the through hole 7 in the conductive mask 5, the inner surface of the through hole 7 is exposed in the plating solution. For this reason, the plating process can be efficiently performed in the through hole 7, and the plating thickness in the through hole 7 can be controlled. This is very convenient especially when it is desired to form a plating thickness of 100 ⁇ m.
  • the conductive mask 5 serves as an electrode to prevent plating metal from adhering to the front and back surfaces of the substrate intermediate 4 and at the same time serves as an electrode to perform a power feeding operation. For this reason, it is possible to perform the plating process in the through hole simply and inexpensively with only the conductive mask 5. Further, as shown in the figure, when the conductor pattern 8 is provided in advance, it is preferable because the plating pattern 12 can be efficiently applied to the conductor pattern 8 without attaching the plating metal 12 to the conductor pattern 8. . On the other hand, when the conductive pattern 8 is not formed, the conductive mask 5 adheres over the entire surface of the insulating layer 7, so that the plating metal 12 adheres to both the front and back surfaces of the substrate intermediate 4 during the plating process. Can be surely prevented.
  • Electrolysis tank 1
  • To-be-plated body 3
  • Plating solution 4
  • Conductive mask 6
  • Insulating layer 7
  • Through-hole 8
  • Conductive pattern Opening 10
  • Power supply 11
  • Electrode 12 Plating metal 13

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Electroplating Methods And Accessories (AREA)

Abstract

La présente invention concerne l'utilisation d'un substrat intermédiaire (4) comportant des trous d'interconnexion (7) traversant une couche isolante (6) et deux masques électro-conducteurs (5) comprenant des ouvertures à des positions correspondant aux trous d'interconnexion (7), l'ensemble des surfaces avant et arrière du substrat intermédiaire (4) étant recouvert par les masques électro-conducteurs (5) de sorte que les positions des ouvertures soient alignées avec les trous d'interconnexion (7), et les masques électro-conducteurs (5) soient amenés à adhérer fortement à au moins une partie des surfaces avant et arrière du substrat intermédiaire (4) pour qu'un article à être métallisé (2) soit formé. L'article à être métallisé (2) est immergé dans un bain de métallisation (3), un métal est déposé sur l'ensemble de la surface avant de l'article métallisé (2) comprenant les surfaces internes des trous d'interconnexion (7) de sorte qu'un traitement de métallisation soit effectué, et les masques électro-conducteurs (5) soient enlevés depuis le substrat intermédiaire.
PCT/JP2011/054725 2011-03-02 2011-03-02 Procédé de métallisation de trous d'interconnexion et substrat fabriqué au moyen d'un tel procédé WO2012117533A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020137022739A KR101475474B1 (ko) 2011-03-02 2011-03-02 관통공 도금 방법 및 이를 이용하여 제조된 기판
PCT/JP2011/054725 WO2012117533A1 (fr) 2011-03-02 2011-03-02 Procédé de métallisation de trous d'interconnexion et substrat fabriqué au moyen d'un tel procédé
CN2011800688393A CN103403228A (zh) 2011-03-02 2011-03-02 贯通孔镀敷方法以及利用该贯通孔镀敷方法制造的基板

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2011/054725 WO2012117533A1 (fr) 2011-03-02 2011-03-02 Procédé de métallisation de trous d'interconnexion et substrat fabriqué au moyen d'un tel procédé

Publications (1)

Publication Number Publication Date
WO2012117533A1 true WO2012117533A1 (fr) 2012-09-07

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2011/054725 WO2012117533A1 (fr) 2011-03-02 2011-03-02 Procédé de métallisation de trous d'interconnexion et substrat fabriqué au moyen d'un tel procédé

Country Status (3)

Country Link
KR (1) KR101475474B1 (fr)
CN (1) CN103403228A (fr)
WO (1) WO2012117533A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104313657A (zh) * 2014-11-10 2015-01-28 临安振有电子有限公司 Hdi印制线路板通孔的电沉积装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5989783A (ja) * 1982-11-13 1984-05-24 Yamada Mekki Kogyosho:Kk 電気メツキ装置
JPH10173337A (ja) * 1996-12-06 1998-06-26 Fujitsu Ltd プリント基板の製造方法
JP2003309356A (ja) * 2002-04-15 2003-10-31 Daiwa Kogyo:Kk メッキスルーホールの形成方法、及び多層配線基板の製造方法
JP2007059796A (ja) * 2005-08-26 2007-03-08 Matsushita Electric Works Ltd 貫通孔配線の製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5932915B2 (ja) * 1981-07-25 1984-08-11 「弐」夫 甲斐 スル−ホ−ルを有する配線基板製造方法
JPH09214134A (ja) * 1996-01-31 1997-08-15 Matsushita Electric Works Ltd プリント配線板の製造方法
TWI389205B (zh) * 2005-03-04 2013-03-11 Sanmina Sci Corp 使用抗鍍層分隔介層結構

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5989783A (ja) * 1982-11-13 1984-05-24 Yamada Mekki Kogyosho:Kk 電気メツキ装置
JPH10173337A (ja) * 1996-12-06 1998-06-26 Fujitsu Ltd プリント基板の製造方法
JP2003309356A (ja) * 2002-04-15 2003-10-31 Daiwa Kogyo:Kk メッキスルーホールの形成方法、及び多層配線基板の製造方法
JP2007059796A (ja) * 2005-08-26 2007-03-08 Matsushita Electric Works Ltd 貫通孔配線の製造方法

Also Published As

Publication number Publication date
CN103403228A (zh) 2013-11-20
KR20130139336A (ko) 2013-12-20
KR101475474B1 (ko) 2014-12-23

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