WO2012103789A1 - 一种数据处理方法、数据处理系统以及相关设备 - Google Patents

一种数据处理方法、数据处理系统以及相关设备 Download PDF

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Publication number
WO2012103789A1
WO2012103789A1 PCT/CN2012/070569 CN2012070569W WO2012103789A1 WO 2012103789 A1 WO2012103789 A1 WO 2012103789A1 CN 2012070569 W CN2012070569 W CN 2012070569W WO 2012103789 A1 WO2012103789 A1 WO 2012103789A1
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Prior art keywords
bit
output
bits
analog
turned
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PCT/CN2012/070569
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English (en)
French (fr)
Inventor
王勇
石晓明
李刚
邵珠法
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华为技术有限公司
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Priority to EP12741633.7A priority Critical patent/EP2672627B1/en
Priority to JP2013550748A priority patent/JP6050761B2/ja
Publication of WO2012103789A1 publication Critical patent/WO2012103789A1/zh
Priority to US13/955,235 priority patent/US9058171B2/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3253—Power saving in bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/05—Digital input using the sampling of an analogue quantity at regular intervals of time, input from a/d converter or output to d/a converter
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates to the field of data processing, and in particular, to a data processing method, a data processing system, and related devices.
  • ADC analog-to-digital converter
  • the ADC samples the analog signal to obtain the analog sampled value, and then converts the analog sampled value into a set of digital signals through analog-to-digital conversion. During each sampling period, the ADC can sample an analog sampled value and output a set of digital signals to Subsequent data processing equipment processes.
  • the sampling frequency of the ADC is 100Hz, that is, 100 analog samples are sampled per second
  • the resolution of analog-to-digital conversion is 8 bits, that is, each analog sample value is quantized with 8 bits, and the ADC converts an analog sample value.
  • the total number of bits output by the ADC per second is 800 bits, that is, the interface rate of the ADC output digital signal is 0.8 Kbps, and the subsequent data processing device connected to the ADC also needs to receive the data signal at the interface rate. And processing each bit of the digital signal.
  • the various data processing devices connected to the ADC must also operate at a high rate, thereby increasing the overall system's power. Consumption.
  • Embodiments of the present invention provide a data processing method, a data processing system, and related devices, which can reduce system power consumption.
  • the data processing method provided by the embodiment of the present invention includes: simulating an analog signal to obtain a simulation a sampled value; performing analog-to-digital conversion on the analog sampled value to obtain a digital signal; splitting each bit in the digital signal to obtain at least two bit groups; if the preset turn-off condition is met, turning off at least one The output of the bits in the bit group.
  • the analog-to-digital converter includes: a sampling unit, configured to sample an analog signal to obtain an analog sample value; and a conversion unit, configured to perform analog-to-digital conversion on the analog sample value to obtain a digital signal; And a method for splitting each bit in the digital signal to obtain at least two bit groups; and a shutdown control unit, configured to turn off an output of the bits in the at least one bit group when a preset off condition is met.
  • a data processing system includes: a data processing device, and an analog to digital converter; the data processing device is configured to receive a digital signal output by the analog to digital converter, and perform data according to the received digital signal. deal with.
  • the base station provided by the embodiment of the present invention includes: an analog to digital converter.
  • the base station controller provided by the embodiment of the present invention includes: an analog to digital converter.
  • the embodiments of the present invention have the following advantages:
  • each bit in the data signal may be split to obtain at least two bit groups, and when the off condition is satisfied, the output of the bits in the at least one bit group is turned off, so When the shutdown condition is met, the number of bits output by the ADC is reduced, which can reduce the interface rate of the digital signal output by the ADC, thereby reducing the operating speed of various data processing devices connected to the ADC, thereby effectively reducing the overall power consumption of the system. .
  • FIG. 1 is a schematic diagram of an embodiment of a data processing method according to the present invention.
  • FIG. 2 is a schematic diagram of another embodiment of a data processing method according to the present invention.
  • FIG. 3 is a schematic diagram of a data processing flow of the present invention.
  • FIG. 4 is a schematic diagram of an operation sequence of an interface according to the present invention.
  • Figure 5 is a schematic diagram of an embodiment of an analog to digital converter of the present invention.
  • FIG. 6 is a schematic diagram of another embodiment of an analog to digital converter of the present invention.
  • FIG. 7 is a schematic diagram of an embodiment of a data processing system of the present invention.
  • Embodiments of the present invention provide a data processing method, a data processing system, and related devices, which can Reduce system power consumption.
  • an embodiment of the data processing method of the present invention includes:
  • the ADC can sample the input analog signal according to the preset sampling rate to obtain an analog sample value.
  • the process and mode of the specific sampling are not limited herein.
  • the analog sample value can be analog-to-digital converted to obtain a digital signal.
  • the analog-to-digital conversion can be implemented in various ways, which is not limited herein.
  • Each analog sampled value is subjected to analog-to-digital conversion to obtain a digital signal consisting of several consecutive bits.
  • the number of bits contained in each digital signal is usually referred to as the resolution of analog-to-digital conversion, and each digital signal is included. The greater the number of bits, the finer the expression of the analog signal can be.
  • the ADC can split each bit in the digital signal to obtain at least two groups of bits, or more, and the specific number is not limited herein.
  • the output of the bits in the at least one bit group is turned off.
  • the ADC After the ADC splits each bit to obtain a number of bit groups, if it detects that the preset shutdown condition is satisfied, it means that the number of output bits needs to be reduced to reduce the system power consumption, and the ADC can turn off the bits in at least one bit group. Output.
  • the ADC can detect whether the preset shutdown condition is satisfied in real time, and the shutdown condition is used to indicate whether it is necessary to reduce the number of output bits. If the shutdown condition is met, it indicates that the output needs to be reduced. The number of bits, if the off condition is not met, means that there is no need to reduce the number of bits output.
  • the ADC can detect whether the preset shutdown condition is met in various ways, for example, by a local preset shutdown rule and a current sampling period, or according to whether a trigger signal is received, and the specific detection is performed.
  • the method is not limited here.
  • each bit in the data signal can be split to obtain at least two groups of bits, and when the off condition is satisfied, the output of the bits in at least one of the groups of bits is turned off, so When the shutdown condition is satisfied, the number of bits output by the ADC is reduced, which can reduce the interface rate of the digital signal output by the ADC, thereby reducing the various data processing devices connected to the ADC.
  • the operating rate can effectively reduce the overall power consumption of the system.
  • FIG. 2 another embodiment of the data processing method of the present invention includes:
  • the ADC can sample the input analog signal according to the preset sampling rate to obtain an analog sample value.
  • the process and mode of the specific sampling are not limited herein.
  • the analog sample value can be analog-to-digital converted to obtain a digital signal.
  • the analog-to-digital conversion can be implemented in various ways, which is not limited herein.
  • Each analog sampled value is subjected to analog-to-digital conversion to obtain a digital signal consisting of several consecutive bits.
  • the number of bits contained in each digital signal is usually referred to as the resolution of analog-to-digital conversion, and each digital signal is included. The greater the number of bits, the finer the expression of the analog signal can be.
  • the ADC may split each bit in the digital signal into the first bit group according to the importance weight and The second bit group.
  • the ADC can be connected to various data processing devices, such as spectrum analysis devices, power analysis devices, etc., which receive digital signals output by the ADC and perform corresponding data processing, for example, spectrum analysis and power analysis. Wait.
  • data processing devices such as spectrum analysis devices, power analysis devices, etc.
  • the importance weights described in this embodiment refer to the degree of influence of each bit in the digital signal on the data processing of the data processing device. The greater the degree of influence, the higher the importance weight of the bit, and the smaller the degree of influence. , the lower the importance weight of the bit.
  • the ADC may split each bit of the digital signal according to the importance weight to obtain at least two groups of bits, and the obtained weights of each group of bits may be all bits in the group of bits.
  • the demarcation information of the high and low bits may be set in advance in the ADC.
  • the demarcation information may be set by the user according to the empirical data, or may be set by the ADC according to the requirements of the data processing device, which is not limited herein.
  • the demarcation information is "high X bits are high. Bit bit, low Y bit is low bit bit", then the ADC can compose the high X bit of the bit of the digital signal into the first bit group, and the low clamp bits in the digital signal form the second bit group, X and ⁇ The sum is equal to ⁇ .
  • the amplitude of the analog signal represented by the upper bits of the digital signal is greater than the amplitude of the analog signal represented by the lower bits, so the degree of influence of the upper bits on the data processing of the data processing device is greater than the extent to which the lower bits affect the data processing of the data processing device. That is to say, the importance weight of the high order bit is higher than the importance weight of the low order bit.
  • the first bit group is composed of high order bits
  • the second bit group is composed of low order bits, so the importance weight of the first bit group is higher than the importance weight of the second bit group.
  • each bit in the digital signal can be divided into a high-order bit, a median bit, and a low-order bit, and then three bit groups are formed, which is not limited herein.
  • the ADC After splitting each bit in the digital signal, the ADC obtains a first bit group and a second bit group, wherein the first bit group is composed of high order bits, and the second bit group is composed of low order bits.
  • the ADC can then output the bits in the first group of bits (i.e., the upper bits) and the bits in the second group of bits (i.e., the lower bits).
  • the ADC may first completely output the bits in the first bit group (ie, the high order bits) and the bits in the second bit group (ie, the low order bits), which is understandable. Yes, in practical applications, the ADC does not necessarily need to completely output the bits in the first bit group (ie, the high order bits) and the bits in the second bit group (ie, the low order bits). Therefore, in this embodiment, Step 204 is an optional step.
  • the ADC is in the first bit group (ie, the high order bit) and the bit in the second bit group
  • the ADC can activate the shutdown control.
  • the trigger signal received by the ADC may be sent by the data processing device, or may be sent by the user through the terminal, which is not limited herein.
  • the trigger signal in this embodiment may be a signal dedicated to triggering the ADC to activate the shutdown control, or may be other types of signals, as long as the ADC recognizes the signal as a trigger signal, for example, data processing of a large power consumption.
  • the device When the device is powered on, it can send a power-on signal to the ADC, and the ADC can recognize the power-on signal as a trigger signal.
  • the trigger signal in this embodiment is sent to the ADC by an external device or network element.
  • the ADC does not necessarily need to receive the trigger signal to activate the shutdown control, but may also decide independently.
  • the shutdown control is activated.
  • a timer can be set in the ADC. When the timer is timed out, the ADC activates the shutdown control and resets the timer.
  • the shutdown control can be activated periodically. Therefore, in this embodiment, Step 205 is an optional step.
  • the bits in the first group of bits may be continuously output, and the bits in the second group of bits (ie, the lower bits) are intermittently output according to a preset shutdown rule.
  • the shutdown rule is used to indicate the sampling period that needs to be turned off, and/or the sampling period without turning off the output.
  • the shutdown rule can be set according to the requirements of the data processing device, or can be set according to the user's experience value, or Set according to power consumption requirements, which is not limited here.
  • the ADC will get an analog sample value every sampling period, so the ADC will also output a digital signal every sampling period.
  • the shutdown rule indicates how to perform the shutdown control. Specifically, it can be the sampling period that needs to be turned off, and / The sampling period of the output may not be turned off, for example, "the odd-numbered period needs to be turned off the output", or "the even-numbered period does not need to turn off the output”.
  • the ADC can acquire the shutdown flag according to the shutdown rule and the current sampling period.
  • the shutdown identifier is used to indicate whether the current cycle needs to be turned off. If the shutdown flag indicates that the output needs to be turned off, the preset shutdown condition is satisfied.
  • the ADC can turn off the output of the bits in the at least one bit group of the current period. In this embodiment, the ADC can turn off the output of the bits in the second bit group of the current period, since it is important not to output the part of the bit. The performance of data processing equipment has a serious impact.
  • the ADC can acquire the shutdown flag according to the shutdown rule and the current sampling period in each sampling period. If a sampling period after the output of the bit in the second bit group is turned off, the ADC determines that the shutdown flag indicates that the output does not need to be turned off. , the preset recovery condition is satisfied, and the ADC can recover the second bit group. The output of the bit.
  • the shutdown control described above is for the bits in the second bit group.
  • two bit groups are taken as an example. If there are multiple bit groups, the lowest importance weight can be used.
  • the bits in the bit group are controlled to be turned off, and the bits in the two bit groups with lower importance weights can also be turned off, and can be used in other bit groups except the one with the highest importance weight.
  • the bits are all turned off, and the object of the specific shutdown control is not limited herein.
  • the output of the bits (ie, the high order bits) in the first bit group is not limited, and is still output sequentially according to the sampling period, and the high order bits have higher importance weights, so the bits are output.
  • the basic performance of the data processing device can be guaranteed.
  • all data processing devices work intermittently according to a certain period, assuming that the sampling rate of the ADC is 1000 Hz, each sampling period is 1 millisecond, and all data processing devices Both work for 1 millisecond, pause for 10 milliseconds, and the input of the analog signal is continuous. Then, within 10 milliseconds of pause of all data processing devices, the high-order bits of the ADC output have no effect, so the ADC can process according to the data.
  • These features of the device set the shutdown rules so that when all data processing devices are paused, the digital signal output is completely turned off, and within 1 millisecond of the data processing device's operation, the ADC can recover the digital signal output. In this way, 10 times extraction of the digital signal can be achieved.
  • the ADC determines the bit output in which bit group is turned off according to the importance weight. For example, the number of bits in each bit group can be determined to determine the output of the bit in the bit group containing the least bit. The output of the bits in the bit group containing the least number of "1" bits can also be determined based on the value of the bits in each bit group. The output of the bits in which bit group is specifically turned off is not limited herein.
  • each bit in the data signal may be split according to the importance weight to obtain at least two bit groups, and when the shutdown condition is met, the importance weight is turned off is low.
  • the bit output of the bit group so when the turn-off condition is satisfied, the number of bits output by the ADC is reduced, which can reduce the interface rate of the digital signal output by the ADC, thereby reducing the operating speed of various data processing devices connected to the ADC. Therefore, the overall power consumption of the system can be effectively reduced.
  • the ratio of the ADC turning off the importance weight is low.
  • the data processing process of the present invention is:
  • the analog signal is input to analog-to-digital conversion, and the analog-to-digital conversion samples the analog signal according to the sampling clock and converts it into a digital signal;
  • the resolution of the analog-to-digital conversion is 8 bits, that is, the digital signal corresponding to each analog sample value includes 8 bits, the sampling rate is 1000 Hz, and the sampling period is 1 millisecond.
  • the relationship between the analog sampled value and the digital signal in the first 10 sampling periods is as follows:
  • each bit in the digital signal obtained by analog-to-digital conversion can be split into high-order bits and low-order bits according to high-low-order boundary information
  • the high and low bit boundary information in this embodiment is "the upper 6 bits are the upper bits and the lower 2 bits are the lower bits", and the bits after the splitting of each sampling period are as shown in Table 2 below:
  • the digital filter performs digital filtering on the upper bits and the lower bits
  • the digital filter in this embodiment may be a configurable digital filter, which may be a Finite Impulse Response (FIR) structure, the filter bandwidth of which is configurable, and the filter coefficients are configurable. It can be configured in the form of all-pass, low-pass or band-pass and out-of-band suppression in different systems, or can be configured to resist the extraction and aliasing mode, which is not limited herein.
  • FIR Finite Impulse Response
  • the upper bits and the lower bits can be stored in the output buffer. Specifically, the upper bits are stored in the buffer H, and the lower bits are stored in the buffer L.
  • the output buffer can store 8 bits corresponding to one sampling period. When the 8 bits are output or turned off, the 8 bits corresponding to the next sampling period are stored.
  • the high order bit stored in the buffer H is "011110"
  • the buffer The lower bit stored in L is "10"
  • the high order bit stored in buffer H is "100000", and the low order bit stored in buffer L is "01";
  • the high order bit stored in buffer H is "110101", and the low order bit stored in buffer L is "00";
  • the high order bit stored in buffer H is "101011", and the low order bit stored in buffer L is "11";
  • the high order bit stored in buffer H is "010001", and the low order bit stored in buffer L is "01";
  • the high order bit stored in buffer H is "001001", and the low order bit stored in buffer L is "01";
  • the high order bit stored in buffer H is "010110", and the low order bit stored in buffer L is "00";
  • the high order bit stored in buffer H is "101100", and the low order bit stored in buffer L is "00";
  • the high order bit stored in buffer H is "111000", and the low order bit stored in buffer L is "01";
  • the high order bit stored in buffer H is "100101"
  • the low order bit stored in buffer L is "01”.
  • the enable module activates the shutdown control according to the trigger signal.
  • the enable module When the enable module receives an external trigger signal, it can obtain the current sampling period information according to the sampling clock, and activate the shutdown control according to the current sampling period and the shutdown rule.
  • the shutdown rule can be represented by the Ton counter and the Toff timer in the enabling module, where Ton indicates the number of sampling clocks that need not be turned off, and Toff indicates the number of sampling clocks that need to be turned off. number.
  • Ton 3 and Toff is 3, which means that after the shutdown control is activated, there is no need to turn off during the three sampling periods, and then turn off in the next three sampling periods.
  • Figure 4 shows the interface output from the first sampling period to the 12th sampling period.
  • the enable module does not receive the trigger signal, does not activate the shutdown control, and completely outputs the high order bit and the low order bit, the output bit is 01111010;
  • the enable module does not receive the trigger signal, does not activate the shutdown control, and completely outputs the high order bit and the low order bit.
  • the output bit is 10000001.
  • the enable module detects The falling edge of the trigger signal, that is, the trigger signal is received, and the turn-off control is activated;
  • the enabling module acquires the shutdown rule as: "Ton is 3, Toff is 3", and the current sampling period is the first period after the activation of the shutdown control. , indicating that there is no need to perform shutdown, and the high-order bits and the low-order bits are completely output, and the output bit is 11010100;
  • the current sampling period is the second period after the activation of the shutdown control.
  • Ton it means that the high-order bits and the low-order bits are not required to be turned off, and the output bits are output. Is 10101111;
  • the current sampling period is the 3rd cycle after the activation of the shutdown control. If Ton is applied, it means that the output bit is not required to be turned off, and the high-order bit and the low-order bit are completely output. Is 01000101;
  • the current sampling period is the fourth cycle after the shutdown control is activated. If Toff is applied, it indicates that the shutdown is required, then the output of the lower bit is turned off, and the high bit is output. , the output bit is 001001;
  • the current sampling period is the 5th cycle after the shutdown control is activated. If Toff is applied, it indicates that the shutdown is required, then the output of the lower bit is turned off, and the high bit is output. , the output bit is 010110;
  • the current sampling period is the 6th cycle after the shutdown control is activated. If Toff is applied, it indicates that the shutdown is required, then the output of the lower bit is turned off, and the high bit is output. , the output bit is 101100.
  • the enable module detects the falling edge of the trigger signal, that is, when the trigger signal is received, the shutdown control is activated; the shutdown control reference of the subsequent sampling period.
  • the following tube describes the corresponding process of the data processing device: It can also be used for other types of devices.
  • the power analysis device is taken as an example.
  • the power analysis device Since the ADC outputs digital signals according to the sampling period, the power analysis device should receive 8 bits per sampling period, assuming that the delay of data transmission is not considered, the processing flow of the power analysis device is as follows:
  • the power analysis device receives the bit 01111010, and the power analysis device can convert the corresponding voltage to 122 millivolts according to the bit conversion, and perform power analysis according to the voltage;
  • the power analysis device receives the bit 10000001, and the power analysis device can convert the corresponding voltage to 129 millivolts according to the bit conversion, and perform power analysis according to the voltage;
  • the power analysis device receives the bit 11010100, and the power analysis device can convert the corresponding voltage to 212 millivolts according to the bit conversion, and perform power analysis according to the voltage;
  • the power analysis device receives the bit 10101111, and the power analysis device can convert the corresponding voltage to 175 millivolts according to the bit conversion, and perform power analysis according to the voltage;
  • the power analysis device receives the bit 01000101, and the power analysis device can convert the corresponding voltage to 69 millivolts according to the bit conversion, and perform power analysis according to the voltage;
  • the power analysis device receives the bit of 001001. Since the power analysis device only receives 6 bits, the power analysis device fills the digital register with the bit in order from high to low. If the bit is missing, the power analysis device ignores the contents of the two registers and directly fills the 2 bits that are not received by 0.
  • the restored bit of the power analysis device is 00100100, and the corresponding voltage is 36 according to these bit conversions. Millivolts, and perform power analysis based on the voltage;
  • the bit received by the power analysis device is 010110. Since the power analysis device only receives 6 bits, the power analysis device fills the bit register in high order from high to low, and the lowest register The bit will be missing, then the power analysis device ignores the two registers. The content of the 2 bits that are not received is directly filled with 0, then the bit after the power analysis device is restored is 01011000, and the corresponding voltage is converted to 88 millivolts according to these bits, and power analysis is performed according to the voltage;
  • the power analysis device receives the bit 101100. Since the power analysis device only receives 6 bits, the power analysis device fills the digital register with the bits in order from high to low. If the bit is missing, the power analysis device ignores the contents of the two registers and directly fills the 2 bits that are not received by 0.
  • the restored bit of the power analysis device is 10110000, and the corresponding voltage is converted according to these bits to 176. Millivolts, and power analysis is performed based on this voltage.
  • the data processing manner of the subsequent sampling period is performed by referring to the foregoing manner, and details are not described herein again.
  • the impact on the power analysis device is small even if it is not output.
  • the power analysis device only in the sixth sampling period, the power analysis device The voltage of the reduction is slightly different from the original value, but for power analysis, which does not require detailed analysis results, such differences are negligible.
  • Spectral analysis requires fine-grained analysis, but it will not continue to be analyzed for a long time, usually at intervals.
  • Ton counter and the Toff counter in the enabling module can be configured to meet the requirements of spectrum analysis and power analysis. For example, it is assumed that the spectrum analysis is performed every 10 sampling periods, each time. To analyze the digital signal that needs to receive 5 sampling periods, you can set Ton to 5 and Toff to 10. In addition, since the power analysis will continue, the ADC only controls the low-order bits according to Ton and Toff. The high order bits are continuously output.
  • the resolution of the analog-to-digital conversion is 8 bits, that is, the digital signal corresponding to each analog sample value includes 8 bits, and the sampling rate is 1000 Hz.
  • the ADC outputs 8000 bits per second.
  • the data that is, the interface rate of the ADC output digital signal is 8Kbps. If the shutdown control is performed according to the interface timing shown in FIG. 4 in this embodiment, the upper bits (6 bits) are kept continuously output, and the lower bits (2 bits) are output in 3 sampling periods, in the subsequent 3 When the sampling period is turned off, in the 1000 sampling periods, the lower bits can be approximated as being output in 500 sampling periods and turned off in another 500 sampling periods.
  • the number of bits output by the ADC per second is:
  • Ton and Toff are changed, the degree of decrease in the interface rate of the ADC output digital signal will also occur.
  • Change for example, when Ton is set to 5 and Toff is set to 10, it means that the high order bits (6 bits) remain continuously output, and the low order bits (2 bits) are output in 5 sample periods, in the following 10 sample periods. Internally, in the 1000 sampling periods, the low bits can be approximated as output in 333 sampling periods and turned off in another 667 sampling periods.
  • each bit in the data signal may be split according to the importance weight to obtain at least two bit groups, and when the shutdown condition is met, the importance weight is turned off is low.
  • the bit output of the bit group so when the turn-off condition is satisfied, the number of bits output by the ADC is reduced, which can reduce the interface rate of the digital signal output by the ADC, thereby reducing the operating speed of various data processing devices connected to the ADC. Thereby, the overall power consumption of the system can be effectively reduced.
  • an embodiment of the analog to digital converter of the present invention includes:
  • a sampling unit 501 configured to sample the analog signal to obtain an analog sample value
  • the converting unit 502 is configured to perform analog-to-digital conversion on the analog sample values to obtain a digital signal
  • a grouping unit 503 configured to split each bit in the digital signal to obtain at least two bit groups
  • the shutdown control unit 504 is configured to turn off the output of the bits in the at least one bit group when the preset off condition is satisfied. It should be noted that, in this embodiment, the shutdown control unit 504 can detect in real time whether the preset shutdown condition is met, and the shutdown condition is used to indicate whether it is necessary to reduce the number of output bits. If the shutdown condition is met, Explain that it is necessary to reduce the number of bits of the output. If the shutdown condition is not satisfied, it means that there is no need to reduce the number of bits of the output.
  • the shutdown control unit 504 can detect whether the preset shutdown condition is met in various manners, for example, by a locally preset shutdown rule and a current sampling period, or according to whether a trigger signal is received or not.
  • the specific detection method is not limited here.
  • FIG. 6 another embodiment of the analog-to-digital converter of the present invention includes:
  • a sampling unit 601 configured to sample the analog signal to obtain an analog sample value
  • a converting unit 602 configured to perform analog-to-digital conversion on the analog sampled value to obtain a digital signal
  • the digital filtering unit 604 is configured to perform anti-aliasing digital filtering on the bits in each bit group split by the grouping unit 603, and output the filtered bits to the shutdown control unit 605;
  • the shutdown control unit 605 is configured to turn off the output of the bits in the bit group having a lower importance weight when the preset off condition is satisfied.
  • the shutdown control unit 605 in this embodiment is further configured to restore the output of the bits in the bit group having a lower importance weight when the preset recovery condition is satisfied.
  • the status check unit 606 is configured to acquire a shutdown identifier according to a preset shutdown rule and a current sampling period, where the shutdown rule is used to indicate a sampling period in which the output needs to be turned off, and/or a sampling period in which the output is not required to be turned off;
  • the shutdown control unit 605 is triggered to turn off the output of the bit in the bit group having a lower importance weight
  • the shutdown control unit 605 is triggered to restore the output of the bit in the bit group having a lower importance weight.
  • the shutdown rule may be preset to the analog-to-digital converter, and the state verification unit 606 may obtain the shutdown rule locally.
  • the state verification unit 606 may also Connected to the sampling clock signal, the current sampling period is determined based on the sampling clock signal.
  • the trigger unit 607 is configured to trigger the status check unit 606 to perform a corresponding operation according to the received trigger signal.
  • the grouping unit 603 splits each bit in the digital signal according to the importance weight to obtain at least two bit groups, and the shutdown control unit 605 turns off the importance right when the preset shutdown condition is satisfied.
  • the output of the bit in the lower bit group that is, the embodiment is based on the importance weight to determine which bit group the output of the bit is turned off. In practical applications, it is also possible to determine which one to turn off according to other factors.
  • the output of the bits in the bit group for example, may be determined according to the number of bits in each bit group to turn off the output of the bit in the bit group containing the least bit, and may also be based on the value of the bit in each bit group to determine that the off contains the least number of bits.
  • the output of the bits in the bit group of "1" bits, which specifically turns off the output of the bits in which bit group is not limited herein.
  • the sampling unit 601 can sample the input analog signal according to a preset sampling rate to obtain an analog sampling value, and the specific sampling process and manner are not limited herein.
  • the conversion unit 602 can perform analog-to-digital conversion on the analog sample value to obtain a digital signal.
  • the analog-to-digital conversion can be implemented in various manners, which is not limited herein.
  • Each analog sampled value is subjected to analog-to-digital conversion to obtain a digital signal consisting of several consecutive bits.
  • the number of bits contained in each digital signal is usually referred to as the resolution of analog-to-digital conversion, and each digital signal is included. The greater the number of bits, the finer the expression of the analog signal can be.
  • the grouping unit 603 may split the bits in the digital signal according to the importance weight to obtain at least two groups of bits, or may be more, and the specific number is not limited herein.
  • the ADC is connected to various data processing devices, such as, for example, a spectrum analysis device, a power analysis device, etc., which receive digital signals output by the ADC and perform corresponding data processing, for example, spectrum analysis and power analysis. Wait.
  • data processing devices such as, for example, a spectrum analysis device, a power analysis device, etc.
  • the importance weights described in this embodiment refer to the degree of influence of each bit in the digital signal on the data processing of the data processing device. The greater the degree of influence, the higher the importance weight of the bit. The smaller the degree of ringing, the lower the importance weight of the bit.
  • the grouping unit 603 splits each bit in the order of the importance weights of the bits, so that the importance weights of the obtained bit groups are also high or low.
  • the digital filtering unit 604 may perform anti-aliasing digital filtering on the bits in each bit group obtained by the grouping unit 603, and then, if the switching control unit 605 is turned off, Detecting the shutdown condition that satisfies the preset indicates that it is necessary to reduce the number of bits of the output to reduce the system power consumption. For example, the shutdown control unit 605 can turn off the output of the bit in the bit group with lower importance weight, due to importance. The bits in the bit group with lower weight have less influence on the data processing of the data processing device, and not outputting the bit does not seriously affect the performance of the data processing device;
  • the shutdown control unit 605 After the shutdown control unit 605 turns off the output of the bit in the bit group having a lower importance weight, if the preset recovery condition is satisfied, the shutdown control unit 605 can restore the bit in the bit group having a lower importance weight. Output.
  • whether the preset shutdown condition and the preset recovery condition are satisfied may be determined by the state verification unit 606.
  • the state verification unit 606 may obtain according to the preset shutdown rule and the current sampling period. Shutdown flag, the shutdown rule is used to indicate the sampling period that needs to be turned off, and/or the sampling period without turning off the output.
  • the trigger shutdown control unit 605 turns off the output of the bit in the bit group with a lower importance weight; if the turn-off flag indicates that the output does not need to be turned off, it determines that the preset recovery condition is satisfied, and triggers the shutdown control unit 605 to restore the important The output of the bits in the bit group with lower weight.
  • the status check unit 606 in this embodiment may perform a corresponding operation under the trigger of the trigger unit 607.
  • the trigger status check unit 606 performs a corresponding operation.
  • the grouping unit 603 may split each bit in the data signal to obtain at least two groups of bits.
  • the shutdown control unit 605 may turn off at least The output of the bits in a bit group, so when the shutdown condition is satisfied, the number of bits output by the ADC is reduced, which can reduce the interface rate of the digital signal output by the ADC, thereby reducing the operating speed of various data processing devices connected to the ADC. Thereby effectively reducing the overall power consumption of the system;
  • the shutdown control unit 605 turns off the output of the bit in the bit group having the lower importance weight, and maintains the output of the bit in the bit group having the higher importance weight. Because the bit with higher importance weight has more influence on the data processing of the data processing device, continuously outputting the bit in the bit group with higher importance weight can keep the data processing device while reducing the overall power consumption of the system. The basic performance.
  • an embodiment of the data processing system of the present invention includes:
  • the analog-to-digital converter 701 in this embodiment may be similar to the analog-to-digital converter described in the foregoing FIG. 5 or FIG. 6, and details are not described herein again.
  • the data processing device 702 in this embodiment is configured to receive a digital signal output from the analog to digital converter 701 and perform data processing based on the received digital signal.
  • the data processing system in this embodiment can be implemented in a base station or a base station controller, or other network element, where the analog-to-digital converter can be implemented by a single board having an acquisition and conversion function, and each data processing device is also implemented. Can be implemented by different boards.
  • the analog-to-digital converter can be located in a base station or a base station controller, and the analog-to-digital converter can be implemented by a single board having an acquisition and conversion function, and each data processing device can be separately configured. It is located in different network elements, and the specific implementation manner is not limited herein.
  • a base station and a base station controller are further provided:
  • the base station of this embodiment includes at least an analog-to-digital converter, and the analog-to-digital converter can be similar to the analog-to-digital converter described in FIG. 5 or FIG. 6, and details are not described herein again.
  • the base station controller of this embodiment includes at least an analog-to-digital converter, and the analog-to-digital converter can be similar to the analog-to-digital converter described in FIG. 5 or FIG. 6, and details are not described herein again.
  • the base station and the base station controller in this embodiment may include other modules for communication in addition to the analog-to-digital converter, which is not limited herein.

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Abstract

一种数据处理方法、数据处理系统以及相关设备，用于降低系统功耗。本发明实施例方法包括：对模拟信号进行采样得到模拟采样值；将所述模拟采样值进行模数转换得到数字信号；对所述数字信号中的各比特进行拆分得到至少两个比特组；若满足预置的关断条件，则关断至少一个比特组中比特的输出。还提供一种数据处理系统以及相关设备。

Description

一种数据处理方法、 数据处理系统以及相关设备
本申请要求于 2011 年 1 月 31 日提交中国专利局、 申请号为 201110033987.3、 发明名称为 "一种数据处理方法、 数据处理系统以及相关设 备" 的中国专利申请的优先权， 其全部内容通过引用结合在本申请中。
技术领域
本发明涉及数据处理领域， 尤其涉及一种数据处理方法、数据处理系统以 及相关设备。
背景技术
随着网络技术的发展， 数据传输速率越来越高， 为了适应这种趋势， 模数 转换器（ADC, Analog to Digital Converter ) 的采样速率也不断提高。
目前各种数据处理设备的数字化程度都比较高， 所以大量的设备需要与 ADC 连接， 以获得数字信号进行后续的处理， 例如频谱分析设备， 功率分析 设备等。
ADC对模拟信号进行采样得到模拟采样值， 再通过模数转换， 将模拟采 样值转换为一组数字信号， 每个采样周期内， ADC 可以采样得到一个模拟采 样值， 且输出一组数字信号给后续的数据处理设备进行处理。
例如 ADC的采样频率为 100Hz, 即每秒采样得到 100个模拟采样值， 模 数转换的分辨率为 8个比特， 即每个模拟采样值用 8个比特进行量化， ADC 将一个模拟采样值转换为 8个比特的数字信号， 则每秒 ADC输出的比特总数 为 800比特， 即 ADC输出数字信号的接口速率为 0.8Kbps, 则与 ADC连接的 后续数据处理设备也需要以该接口速率接收数据信号，并对数字信号的每一个 比特进行处理。
当 ADC的采样速率提高时， ADC输出数字信号的接口速率也随之提高， 为了匹配这种高速率，与 ADC连接的各种数据处理设备也必须以高速率运行， 从而加重了整个系统的功耗。
发明内容
本发明实施例提供了一种数据处理方法、数据处理系统以及相关设备， 能 够降低系统功耗。
本发明实施例提供的数据处理方法， 包括： 对模拟信号进行采样得到模拟 采样值； 将所述模拟采样值进行模数转换得到数字信号； 对所述数字信号中的 各比特进行拆分得到至少两个比特组； 若满足预置的关断条件， 则关断至少一 个比特组中比特的输出。
本发明实施例提供的模数转换器， 包括： 采样单元， 用于对模拟信号进行 采样得到模拟采样值； 转换单元， 用于将所述模拟采样值进行模数转换得到数 字信号； 分组单元， 用于对所述数字信号中的各比特进行拆分得到至少两个比 特组； 关断控制单元， 用于当满足预置的关断条件时， 关断至少一个比特组中 比特的输出。
本发明实施例提供的数据处理系统， 包括： 数据处理设备， 以及模数转换 器； 所述数据处理设备用于接收所述模数转换器输出的数字信号， 并根据接收 到的数字信号进行数据处理。
本发明实施例提供的基站， 包括： 模数转换器。
本发明实施例提供的基站控制器， 包括： 模数转换器。
从以上技术方案可以看出， 本发明实施例具有以下优点：
本发明实施例中， ADC得到数字信号之后， 可以对数据信号中的各比特 进行拆分得到至少两个比特组， 并在满足关断条件时， 关断至少一个比特组中 比特的输出， 所以当满足关断条件时， ADC输出的比特数目减少， 可以降低 ADC输出数字信号的接口速率，也就可以降低与 ADC连接的各种数据处理设 备的运行速率， 从而能够有效的降低系统整体功耗。
附图说明
图 1为本发明数据处理方法一个实施例示意图；
图 2为本发明数据处理方法另一实施例示意图；
图 3为本发明数据处理流程示意图；
图 4为本发明接口工作时序示意图；
图 5为本发明模数转换器一个实施例示意图；
图 6为本发明模数转换器另一实施例示意图；
图 7为本发明数据处理系统一个实施例示意图。
具体实施方式
本发明实施例提供了一种数据处理方法、数据处理系统以及相关设备， 能 够降低系统功耗。
请参阅图 1 , 本发明数据处理方法一个实施例包括：
101、 对模拟信号进行采样得到模拟采样值；
本实施例中， ADC 可以按照预置的采样率对输入的模拟信号进行采样得 到模拟采样值， 具体采样的过程和方式此处不做限定。
102、 将模拟采样值进行模数转换得到数字信号；
ADC得到模拟采样值后，可以对模拟采样值进行模数转换得到数字信号， 模数转换可以采用多种方式实现， 此处不做限定。
每个模拟采样值经过模数转换后即得到一个由若干连续比特组成的数字 信号，每个数字信号所包含的比特的数目通常被称作是模数转换的分辨率，每 个数字信号所包含的比特的数目越多， 则能够越精细的对模拟信号进行表达。
103、 对数字信号中的各比特进行拆分得到至少两个比特组；
当得到数字信号之后， ADC 可以对数字信号中的各比特进行拆分得到至 少两个比特组， 也可以为更多个， 具体数目此处不做限定。
104、 若满足预置的关断条件， 则关断至少一个比特组中比特的输出。
ADC对各比特进行拆分得到若干个比特组之后， 若检测到满足预置的关 断条件， 则说明需要减少输出的比特数目以降低系统功耗， ADC 可以关断至 少一个比特组中比特的输出。
需要说明的是， 本实施例中， ADC 可以实时检测是否满足预置的关断条 件， 该关断条件用以指示是否需要减少输出的比特数目， 若满足该关断条件， 则说明需要减少输出的比特数目， 若不满足该关断条件， 则说明无需减少输出 的比特数目。
在实际应用中， ADC 可以通过多种方式检测是否满足预置的关断条件， 例如通过本地预置的关断规则以及当前采样周期进行检测，或者根据是否接收 到触发信号进行检测， 具体检测的方式此处不作限定。
本实施例中， ADC得到数字信号之后， 可以对数据信号中的各比特进行 拆分得到至少两个比特组， 并在满足关断条件时， 关断至少一个比特组中比特 的输出， 所以当满足关断条件时， ADC输出的比特数目减少， 可以降低 ADC 输出数字信号的接口速率， 也就可以降低与 ADC连接的各种数据处理设备的 运行速率， 从而能够有效的降低系统整体功耗。
为便于理解， 下面以一具体实例对本发明数据处理方法进行详细描述，请 参阅图 2, 本发明数据处理方法另一实施例包括：
201、 对模拟信号进行采样得到模拟采样值；
本实施例中， ADC 可以按照预置的采样率对输入的模拟信号进行采样得 到模拟采样值， 具体采样的过程和方式此处不做限定。
202、 将模拟采样值进行模数转换得到数字信号；
ADC得到模拟采样值后，可以对模拟采样值进行模数转换得到数字信号， 模数转换可以采用多种方式实现， 此处不做限定。
每个模拟采样值经过模数转换后即得到一个由若干连续比特组成的数字 信号，每个数字信号所包含的比特的数目通常被称作是模数转换的分辨率，每 个数字信号所包含的比特的数目越多， 则能够越精细的对模拟信号进行表达。
203、 将数字信号中的各比特拆分为第一比特组以及第二比特组； 当得到数字信号之后， ADC 可以按照重要性权值将数字信号中的各比特 拆分为第一比特组以及第二比特组。
需要说明的是， ADC可以与各种数据处理设备相连， 例如频谱分析设备， 功率分析设备等， 这些数据处理设备接收 ADC输出的数字信号， 并进行相应 的数据处理， 例如进行频谱分析和功率分析等。
本实施例中所描述的重要性权值是指数字信号中的各比特对数据处理设 备进行数据处理的影响程度， 影响程度越大， 则该比特的重要性权值越高， 影 响程度越小， 则该比特的重要性权值越低。
对于每一个数字信号， ADC 可以将该数字信号的各比特按照重要性权值 进行拆分从而得到至少两个比特组，得到的各比特组的重要性权值可以为该比 特组内所有比特的重要性权值之和，或者也可以为该比特组内所有比特的重要 性权值的平均值。
本实施例中， ADC中预先可以设置有高低位比特的分界信息， 该分界信 息可以由用户根据经验数据设置， 也可以由 ADC根据数据处理设备的需求设 置， 具体此处不做限定。
假设每个模拟采样值对应 N比特的数字信号， 分界信息为 "高 X位为高 位比特， 低 Y位为低位比特"， 则 ADC可以将数字信号的 Ν比特中的高 X位 比特组成第一比特组， 将数字信号中的低 Υ位比特组成第二比特组， X与 Υ 之和等于 Ν。
数字信号的高位比特所表示的模拟信号的幅度大于低位比特所表示的模 拟信号的幅度，所以高位比特对数据处理设备进行数据处理的影响程度大于低 位比特对数据处理设备进行数据处理的影响程度，也就是说高位比特的重要性 权值高于低位比特的重要性权值。
本实施例中， 第一比特组由高位比特组成， 第二比特组由低位比特组成， 所以第一比特组的重要性权值高于第二比特组的重要性权值。
需要说明的是，本实施例中仅以将数字信号中的各比特拆分为第一比特组 以及第二比特组为例进行说明， 在实际应用中， 还可以拆分为更多的比特组， 例如可以将数字信号中的各比特拆分为高位比特、 中位比特以及低位比特， 然 后组成三个比特组， 具体此处不做限定。
204、 输出第一比特组中的比特以及第二比特组中的比特；
ADC 对数字信号中的各比特进行拆分后， 得到第一比特组以及第二比特 组， 其中， 第一比特组由高位比特组成， 第二比特组由低位比特组成。
之后 ADC可以输出第一比特组中的比特（即高位比特） 以及第二比特组 中的比特（即低位比特）。
为便于描述 ADC的关断控制， 本实施例中， ADC可以先对第一比特组中 的比特（即高位比特）以及第二比特组中的比特（即低位比特）进行完整输出， 可以理解的是， 在实际应用中， ADC 并不一定需要先对第一比特组中的比特 (即高位比特）以及第二比特组中的比特（即低位比特）进行完整输出， 因此， 本实施例中的步骤 204为可选步骤。
205、 接收触发信号；
ADC 在对第一比特组中的比特（即高位比特） 以及第二比特组中的比特
(即低位比特）的输出过程中， 若接收到触发信号， 则说明需要减少输出的比 特数目以降低系统功耗， 则 ADC可以激活关断控制。
本实施例中， ADC接收到的触发信号可以由数据处理设备发出， 也可以 由用户通过终端发出， 具体此处不做限定。 本实施例中的触发信号并可以是专用于触发 ADC激活关断控制的信号， 也可以是其他类型的信号， 只要 ADC将该信号识别为触发信号即可， 例如， 某大功耗的数据处理设备上电时可以向 ADC发送上电信号， 则 ADC可以将 该上电信号识别为触发信号。
需要说明的是， 本实施例中的触发信号是外部的设备或网元发送给 ADC 的， 在实际应用中， ADC并不一定需要接收到该触发信号才能激活关断控制， 而也可以自主决定激活关断控制， 例如 ADC内可以设置有定时器， 每当定时 器超时的时候， ADC 即激活关断控制并重置定时器， 则可周期性的激活关断 控制， 因此， 本实施例中的步骤 205为可选步骤。
206、 持续输出第一比特组中的比特， 并按照预置的关断规则间歇性的输 出第二比特组中的比特。
当 ADC激活关断控制之后， 可以持续输出第一比特组中的比特（即高位 比特）， 并按照预置的关断规则间歇性的输出第二比特组中的比特（即低位比 特）， 该关断规则用以表示需要关断输出的采样周期， 和 /或无需关断输出的采 样周期， 该关断规则可以根据数据处理设备的需求进行设置，也可以根据用户 的经验值进行设置， 或者根据功耗需求进行设置， 具体此处不做限定。
ADC每个采样周期会得到一个模拟采样值，所以 ADC每个采样周期也会 输出一个数字信号， 关断规则中指示了如何进行关断控制， 具体可以是需要关 断输出的采样周期， 和 /或无需关断输出的采样周期， 例如可以为 "奇数周期 需要关断输出"， 或者是 "偶数周期无需关断输出"。
ADC根据该关断规则以及当前采样周期即可获取关断标识， 该关断标识 用于指示当前周期是否需要关断输出， 若关断标识表示需要关断输出， 则满足 预置的关断条件，则 ADC可以关断当前周期的至少一个比特组中比特的输出， 本实施例中， ADC 可以关断当前周期的第二比特组中比特的输出， 由于重要 不输出这部分比特并不会对数据处理设备的性能造成严重影响。
ADC在每个采样周期都可以根据该关断规则以及当前采样周期获取关断 标识， 若关断第二比特组中比特的输出之后的某个采样周期， ADC确定关断 标识表示无需关断输出， 则满足预置的恢复条件， ADC 可以恢复第二比特组 中比特的输出。
上述描述的关断控制均是针对第二比特组中的比特，本实施例中是以两个 比特组为例进行说明的， 若有多个比特组， 则可以对重要性权值最低的一个比 特组中比特进行关断控制，也可以对重要性权值较低的两个比特组中比特进行 关断控制，还可以对除重要性权值最高的一个比特组之外的其他比特组中比特 均进行关断控制， 具体关断控制的对象此处不做限定。
在本实施例的步骤 206中， 第一比特组中的比特（即高位比特）的输出并 未受到限制， 仍然按照采样周期依次输出， 高位比特具有较高的重要性权值， 所以输出这些比特可以保证数据处理设备的基本性能。
在实际应用中， 若出现某些特殊的场景， 例如所有的数据处理设备均按照 某一周期间歇性工作， 假设 ADC 的采样率为 1000Hz, 则每个采样周期为 1 毫秒， 所有的数据处理设备均是工作 1毫秒， 暂停 10毫秒， 而模拟信号的输 入是连续不断的， 那么在所有的数据处理设备均暂停的 10毫秒内， ADC输出 的高位比特也是没有作用的， 所以 ADC可以根据数据处理设备的这些特性设 置关断规则， 使得所有的数据处理设备均暂停时， 完全关断数字信号的输出， 而在数据处理设备均工作的 1毫秒内， ADC可以恢复数字信号的输出， 通过 这样的方式， 则可以实现对数字信号的 10倍抽取。
本实施例中， ADC根据重要性权值的高低以确定关断哪个比特组中比特 输出，例如可以根据每个比特组中比特的数目以确定关断包含最少比特的比特 组中比特的输出， 还可以根据各比特组中比特的数值以确定关断包含最少个 "1" 比特的比特组中比特的输出， 具体关断哪个比特组中比特的输出此处不 作限定。
本实施例中， ADC得到数字信号之后， 可以按照重要性权值对数据信号 中的各比特进行拆分得到至少两个比特组， 并在满足关断条件时， 关断重要性 权值较低的比特组中比特的输出， 所以当满足关断条件时， ADC输出的比特 数目减少， 可以降低 ADC输出数字信号的接口速率， 也就可以降低与 ADC 连接的各种数据处理设备的运行速率， 从而能够有效的降低系统整体功耗； 此外， 本实施例中， 当满足关断条件时， ADC 关断重要性权值较低的比 特组中比特的输出， 而保持重要性权值较高的比特组中比特的输出， 由于重要 性权值越高的比特对数据处理设备进行数据处理的影响程度越大，所以持续输 出重要性权值较高的比特组中比特可以在降低系统整体功耗的同时保持数据 处理设备的基本性能。
上面通过几个实施例对本发明数据处理方法进行了描述，为了对数据处理 的过程进行更详细的描述， 下面以实际应用中的一些例子进行说明， 下述的内 容中所举的例子均为本发明数据处理过程的一种情况，根据前述实施例中的描 述， 同样可以采用其他类似的例子， 为描述筒便， 以下不再赘述。
首先请参阅图 3, 本发明数据处理的过程为：
( 1 )、模拟信号被输入模数转换， 该模数转换根据采样时钟对模拟信号进 行采样， 并转换为数字信号；
本实施例中，模数转换的分辨率为 8位， 即每个模拟采样值对应的数字信 号包含 8个比特， 采样率为 1000Hz, 采样周期为 1毫秒。
输入模数转换的模拟采样值的范围为 1毫伏至 256毫伏，由于模数转换的 分辨率为 8位， 所以转换后的数字信号的精确度为 256/28=1毫伏。
本实施例中， 前 10个采样周期内模拟采样值与数字信号的关系如下表 1 所示：
表 1
采 样
模拟采样值 数字信号
周期
1 122 01111010
2 129 10000001
3 212 11010100
4 175 10101111
5 69 01000101
6 37 00100101
7 88 01011000
8 176 10110000
9 225 11100001 10 149 10010101
( 2 )、模数转换得到的数字信号中的各比特可以按照高低位分界信息拆分 成高位比特以及低位比特；
本实施例中的高低位分界信息为"高 6位为高位比特，低 2位为低位比特" , 则各采样周期拆分后的比特如下表 2所示：
表 2
Figure imgf000011_0001
( 3 )、 数字滤波器对高位比特以及低位比特进行数字滤波；
本实施例中的数字滤波器可以是可配置的数字滤波器，可以为有限长单位 沖激响应（FIR, Finite Impulse Response )结构， 该滤波器的滤波带宽可配置， 滤波器系数可配置。在不同系统中可以配置成全通，低通或带通的形式且带外 抑制能力， 或者还可以配置成抗抽取混迭的模式， 具体此处不做限定。
( 4 )、 将高位比特以及低位比特存入输出緩沖区；
经过数字滤波后，可以将高位比特以及低位比特存入输出緩沖区，具体的， 将高位比特存入緩沖区 H, 将低位比特存入緩沖区 L。
本实施例中，输出緩沖区中可以存储一个采样周期对应的 8个比特， 当这 8个比特被输出或是关断时， 再存入下一采样周期对应的 8个比特。
则第 1个采样周期内， 緩沖区 H中存储的高位比特为 "011110" , 緩沖区 L中存储的低位比特为 "10";
第 2个采样周期内， 緩沖区 H中存储的高位比特为 "100000", 緩沖区 L 中存储的低位比特为 "01";
第 3个采样周期内， 緩沖区 H中存储的高位比特为 "110101", 緩沖区 L 中存储的低位比特为 "00";
第 4个采样周期内， 緩沖区 H中存储的高位比特为 "101011", 緩沖区 L 中存储的低位比特为 "11";
第 5个采样周期内， 緩沖区 H中存储的高位比特为 "010001", 緩沖区 L 中存储的低位比特为 "01";
第 6个采样周期内， 緩沖区 H中存储的高位比特为 "001001", 緩沖区 L 中存储的低位比特为 "01";
第 7个采样周期内， 緩沖区 H中存储的高位比特为 "010110", 緩沖区 L 中存储的低位比特为 "00";
第 8个采样周期内， 緩沖区 H中存储的高位比特为 "101100", 緩沖区 L 中存储的低位比特为 "00";
第 9个采样周期内， 緩沖区 H中存储的高位比特为 "111000", 緩沖区 L 中存储的低位比特为 "01";
第 10个采样周期内， 緩沖区 H中存储的高位比特为 "100101", 緩沖区 L 中存储的低位比特为 "01"。
(5)、 使能模块根据触发信号激活关断控制。
使能模块接收到外部的触发信号时，可以根据采样时钟获取当前采样周期 的信息， 并根据当前采样周期以及关断规则激活关断控制。
本实施例中， 关断规则可以通过使能模块中的 Ton计数器和 Toff计时器 进行表示， 其中， Ton表示无需进行关断的采样时钟的个数， Toff表示需要进 行关断的采样时钟的个数。
本实施例中， Ton为 3, Toff 为 3, 则表示激活关断控制后， 三个采样周 期内无需进行关断， 随后的三个采样周期内关断。
为便于理解， 请参阅图 4, 具体的接口时序如图 4所示， 图 4中展示了第 1个采样周期至第 12个采样周期的接口输出情况， 下面进行说明： 第 l个采样周期， 使能模块未收到触发信号， 不激活关断控制， 完整输出 高位比特以及低位比特， 则输出的比特为 01111010;
第 2个采样周期， 使能模块未收到触发信号， 不激活关断控制， 完整输出 高位比特以及低位比特， 则输出的比特为 10000001 , 在第 2个采样周期结束 时， 使能模块检测到触发信号的下降沿， 即表示接收到了触发信号， 则激活关 断控制；
第 3个采样周期，由于激活了关断控制，则使能模块获取关断规则为： "Ton 为 3 , Toff为 3" , 当前采样周期是激活关断控制后的第 1个周期， 适用 Ton, 则表示无需进行关断， 完整输出高位比特以及低位比特， 则输出的比特为 11010100;
第 4个采样周期， 由于激活了关断控制， 当前采样周期是激活关断控制后 的第 2个周期， 适用 Ton, 则表示无需进行关断， 完整输出高位比特以及低位 比特， 则输出的比特为 10101111 ;
第 5个采样周期， 由于激活了关断控制， 当前采样周期是激活关断控制后 的第 3个周期， 适用 Ton, 则表示无需进行关断， 完整输出高位比特以及低位 比特， 则输出的比特为 01000101 ;
第 6个采样周期， 由于激活了关断控制， 当前采样周期是激活关断控制后 的第 4个周期， 适用 Toff, 则表示需要进行关断， 则关断低位比特的输出， 进 输出高位比特， 则输出的比特为 001001 ;
第 7个采样周期， 由于激活了关断控制， 当前采样周期是激活关断控制后 的第 5个周期， 适用 Toff, 则表示需要进行关断， 则关断低位比特的输出， 进 输出高位比特， 则输出的比特为 010110;
第 8个采样周期， 由于激活了关断控制， 当前采样周期是激活关断控制后 的第 6个周期， 适用 Toff, 则表示需要进行关断， 则关断低位比特的输出， 进 输出高位比特， 则输出的比特为 101100, 在第 8个采样周期结束时， 使能模 块检测到触发信号的下降沿， 即表示接收到了触发信号， 则激活关断控制； 后续的采样周期的关断控制参照前述的方式进行， 此处不再赘述。
为使得整个数据流程更加清楚，下面筒要描述一下数据处理设备的相应流 程： 备， 还可以为其他类型的设备， 此处仅以功率分析设备为例进行说明。
由于 ADC按照采样周期输出数字信号， 则功率分析设备每个采样周期应 当接收到 8个比特，假设不考虑数据传输的时延， 功率分析设备的处理流程如 下：
第 1 个采样周期， 功率分析设备接收到的比特为 01111010, 则功率分析 设备可以根据这些比特转换得到对应的电压为 122毫伏，并根据该电压进行功 率分析；
第 2个采样周期， 功率分析设备接收到的比特为 10000001 , 则功率分析 设备可以根据这些比特转换得到对应的电压为 129毫伏，并根据该电压进行功 率分析；
第 3个采样周期， 功率分析设备接收到的比特为 11010100, 则功率分析 设备可以根据这些比特转换得到对应的电压为 212毫伏，并根据该电压进行功 率分析；
第 4个采样周期， 功率分析设备接收到的比特为 10101111 , 则功率分析 设备可以根据这些比特转换得到对应的电压为 175毫伏，并根据该电压进行功 率分析；
第 5个采样周期， 功率分析设备接收到的比特为 01000101 , 则功率分析 设备可以根据这些比特转换得到对应的电压为 69毫伏， 并根据该电压进行功 率分析；
第 6个采样周期， 功率分析设备接收到的比特为 001001 , 由于功率分析 设备只接收到 6个比特，所以功率分析设备将比特依次由高到低填入数字寄存 器时， 最低位的两个寄存器会缺少比特， 则功率分析设备忽略这两个寄存器中 的内容， 直接将未接收到的 2 个比特填 0, 则功率分析设备还原后的比特为 00100100, 根据这些比特转换得到对应的电压为 36毫伏， 并根据该电压进行 功率分析；
第 7个采样周期， 功率分析设备接收到的比特为 010110, 由于功率分析 设备只接收到 6个比特，所以功率分析设备将比特依次由高到低填入数字寄存 器时， 最低位的两个寄存器会缺少比特， 则功率分析设备忽略这两个寄存器中 的内容， 直接将未接收到的 2 个比特填 0, 则功率分析设备还原后的比特为 01011000, 根据这些比特转换得到对应的电压为 88毫伏， 并根据该电压进行 功率分析；
第 8个采样周期， 功率分析设备接收到的比特为 101100, 由于功率分析 设备只接收到 6个比特，所以功率分析设备将比特依次由高到低填入数字寄存 器时， 最低位的两个寄存器会缺少比特， 则功率分析设备忽略这两个寄存器中 的内容， 直接将未接收到的 2 个比特填 0, 则功率分析设备还原后的比特为 10110000,根据这些比特转换得到对应的电压为 176毫伏， 并根据该电压进行 功率分析。
后续的采样周期的数据处理方式参照前述的方式进行， 此处不再赘述。 由上可以看出， 由于低位比特的重要性权值较低， 所以即使不输出， 对于 功率分析设备的影响也很小， 在上述的例子中， 仅在第 6个采样周期中， 功率 分析设备还原的电压与原值有略微差别，但对于功率分析这一类不需要精细分 析结果的处理方式而言， 这样的差别是可以忽略不计的。
如果是频谱分析这一类非常需要精细分析结果的处理方式，则可以保持所 有比特的输出。
不过， 频谱分析和功率分析还各自具有一些特点：
频谱分析要求精细，但不会长时间持续进行分析，一般是间隔一段时间分 析一次；
功率分析不要求精细，但一般会持续分析，以保持实时更新功率分析结果。 基于上述的特点， 则可以对使能模块中的 Ton计数器和 Toff计数器进行 配置， 从而同时满足频谱分析和功率分析的需求， 例如， 假设频谱分析是每隔 10个采样周期进行一次分析， 每次分析需要接收 5个采样周期的数字信号， 则可以将 Ton设置为 5, Toff设置为 10, 此外， 由于功率分析会持续进行， 所 以 ADC仅根据 Ton和 Toff对低位比特进行关断控制， 而保持高位比特持续输 出。
本实施例中，模数转换的分辨率为 8位， 即每个模拟采样值对应的数字信 号包含 8个比特， 采样率为 1000Hz, 若不进行关断控制， 则 ADC每秒将输出 8000比特的数据， 即 ADC输出数字信号的接口速率为 8Kbps。 若按照本实施例中图 4所示的接口时序进行关断控制， 则高位比特（ 6个 比特 )保持持续输出， 低位比特（ 2个比特 )在 3个采样周期内输出， 在随后 的 3个采样周期内关断， 则在 1000个采样周期中， 低位比特可以近似看作在 500个采样周期内输出， 在另外 500个采样周期内关断。
由此， 采用 了关断控制之后， ADC 每秒输出的比特数目 为：
1000*6+500*2=7000, 即 ADC输出数字信号的接口速率为 7Kbps。
上述是以图 4所示的接口时序进行关断控制为例进行说明的，在实际应用 中， 若 Ton和 Toff的数值发生变化， 则 ADC输出数字信号的接口速率降低的 程度也会随之发生变化， 例如， 当 Ton设置为 5 , Toff设置为 10时， 表示高 位比特（ 6个比特 )保持持续输出， 低位比特（ 2个比特 )在 5个采样周期内 输出， 在随后的 10个采样周期内关断， 则在 1000个采样周期中， 低位比特可 以近似看作在 333个采样周期内输出， 在另外 667个采样周期内关断。
由此， 采用 了关断控制之后， ADC 每秒输出的比特数目 为： 1000*6+333*2=7000, 即 ADC输出数字信号的接口速率为 6.666Kbps。
从上述的对比可以看出， 本实施例采用了关断控制之后， 能够有效的降低
ADC输出数字信号的接口速率。
本实施例中， ADC得到数字信号之后， 可以按照重要性权值对数据信号 中的各比特进行拆分得到至少两个比特组， 并在满足关断条件时， 关断重要性 权值较低的比特组中比特的输出， 所以当满足关断条件时， ADC输出的比特 数目减少， 可以降低 ADC输出数字信号的接口速率， 也就可以降低与 ADC 连接的各种数据处理设备的运行速率， 从而能够有效的降低系统整体功耗。
下面对本发明模数转换器进行描述， 请参阅图 5 , 本发明模数转换器一个 实施例包括：
采样单元 501 , 用于对模拟信号进行采样得到模拟采样值；
转换单元 502, 用于将模拟采样值进行模数转换得到数字信号；
分组单元 503 , 用于对数字信号中的各比特进行拆分得到至少两个比特 组；
关断控制单元 504, 用于当满足预置的关断条件时， 关断至少一个比特组 中比特的输出。 需要说明的是， 本实施例中， 关断控制单元 504可以实时检测是否满足预 置的关断条件， 该关断条件用以指示是否需要减少输出的比特数目， 若满足该 关断条件， 则说明需要减少输出的比特数目， 若不满足该关断条件， 则说明无 需减少输出的比特数目。
在实际应用中，关断控制单元 504可以通过多种方式检测是否满足预置的 关断条件， 例如通过本地预置的关断规则以及当前采样周期进行检测， 或者根 据是否接收到触发信号进行检测， 具体检测的方式此处不作限定。
下面对本发明模数转换器进行详细描述， 请参阅图 6, 本发明模数转换器 另一实施例包括：
采样单元 601 , 用于对模拟信号进行采样得到模拟采样值；
转换单元 602, 用于将模拟采样值进行模数转换得到数字信号； 分组单元 603 , 用于按照重要性权值对数字信号中的各比特进行拆分得到 至少两个比特组；
数字滤波单元 604, 用于对分组单元 603拆分得到的各比特组中的比特进 行抗混迭数字滤波， 将滤波后的比特输出至关断控制单元 605;
关断控制单元 605 , 用于当满足预置的关断条件时， 关断重要性权值较低 的比特组中比特的输出。
本实施例中的关断控制单元 605还用于当满足预置的恢复条件时，恢复重 要性权值较低的比特组中比特的输出。
本实施例中的模数转换器还可以进一步包括：
状态校验单元 606, 用于根据预置的关断规则以及当前采样周期获取关断 标识， 关断规则用以表示需要关断输出的采样周期， 和 /或无需关断输出的采 样周期；
若关断标识表示需要关断输出， 则确定满足预置的关断条件， 并触发关断 控制单元 605关断重要性权值较低的比特组中比特的输出；
若关断标识表示无需关断输出， 则确定满足预置的恢复条件， 并触发关断 控制单元 605恢复重要性权值较低的比特组中比特的输出。
需要说明的是， 本实施例中， 关断规则可以预置在模数转换器本地， 状态 校验单元 606可以从本地获取到该关断规则，此外，状态校验单元 606还可以 与采样时钟信号相连， 根据采样时钟信号确定当前采样周期。
本实施例中的模数转换器还可以进一步包括：
触发单元 607, 用于根据接收到的触发信号触发状态校验单元 606执行相 应操作。
本实施例中，分组单元 603按照重要性权值对数字信号中的各比特进行拆 分得到至少两个比特组， 关断控制单元 605在满足预置的关断条件时， 关断重 要性权值较低的比特组中比特的输出，即本实施例是根据重要性权值的高低以 确定关断哪个比特组中比特的输出，在实际应用中，还可以根据其他的因素确 定关断哪个比特组中比特的输出，例如可以根据每个比特组中比特的数目以确 定关断包含最少比特的比特组中比特的输出，还可以根据各比特组中比特的数 值以确定关断包含最少个 "1" 比特的比特组中比特的输出， 具体关断哪个比 特组中比特的输出此处不作限定。
为便于理解，下面以一具体应用场景对本实施例模数转换器中各单元之间 的联系进行说明：
本实施例中，采样单元 601可以按照预置的采样率对输入的模拟信号进行 采样得到模拟采样值， 具体采样的过程和方式此处不做限定。
采样单元 601得到模拟采样值后，转换单元 602可以对模拟采样值进行模 数转换得到数字信号， 模数转换可以采用多种方式实现， 此处不做限定。
每个模拟采样值经过模数转换后即得到一个由若干连续比特组成的数字 信号，每个数字信号所包含的比特的数目通常被称作是模数转换的分辨率，每 个数字信号所包含的比特的数目越多， 则能够越精细的对模拟信号进行表达。
转换单元 602当得到数字信号之后，分组单元 603可以按照重要性权值对 数字信号中的各比特进行拆分得到至少两个比特组，也可以为更多个， 具体数 目此处不做限定。
需要说明的是， ADC与各种数据处理设备相连， 例如例如频谱分析设备， 功率分析设备等， 这些数据处理设备接收 ADC输出的数字信号， 并进行相应 的数据处理， 例如进行频谱分析和功率分析等。
本实施例中所描述的重要性权值是指数字信号中的各比特对数据处理设 备进行数据处理的影响程度， 影响程度越大， 则该比特的重要性权值越高， 影 响程度越小， 则该比特的重要性权值越低。
分组单元 603 对各比特进行拆分时可以按照比特的重要性权值的顺序依 次拆分 , 所以得到的各比特组的重要性权值也有高低之分。
分组单元 603 对各比特进行拆分得到若干个比特组之后， 数字滤波单元 604可以对分组单元 603拆分得到的各比特组中的比特进行抗混迭数字滤波， 之后， 关断控制单元 605若检测到满足预置的关断条件， 则说明需要减少输出 的比特数目以降低系统功耗，比如关断控制单元 605可以关断重要性权值较低 的比特组中比特的输出，由于重要性权值较低的比特组中的比特对数据处理设 备进行数据处理的影响程度较小，不输出这部分比特并不会对数据处理设备的 性能造成严重影响；
关断控制单元 605关断重要性权值较低的比特组中比特的输出之后，若满 足预置的恢复条件，则关断控制单元 605可以恢复重要性权值较低的比特组中 比特的输出。
本实施例中，预置的关断条件和预置的恢复条件是否满足可以由状态校验 单元 606进行判断， 具体的，状态校验单元 606可以根据预置的关断规则以及 当前采样周期获取关断标识， 关断规则用以表示需要关断输出的采样周期， 和 /或无需关断输出的采样周期， 若关断标识表示需要关断输出， 则确定满足预 置的关断条件，并触发关断控制单元 605关断重要性权值较低的比特组中比特 的输出； 若关断标识表示无需关断输出， 则确定满足预置的恢复条件， 并触发 关断控制单元 605恢复重要性权值较低的比特组中比特的输出。
需要说明的是，本实施例中的状态校验单元 606可以在触发单元 607的触 发下执行相应操作， 该触发单元 607当接收到触发信号时，触发状态校验单元 606执行相应操作。
本实施例中，转换单元 602得到数字信号之后， 分组单元 603可以对数据 信号中的各比特进行拆分得到至少两个比特组，在满足关断条件时， 关断控制 单元 605 可以关断至少一个比特组中比特的输出， 所以当满足关断条件时， ADC输出的比特数目减少， 可以降低 ADC输出数字信号的接口速率， 也就可 以降低与 ADC连接的各种数据处理设备的运行速率， 从而能够有效的降低系 统整体功耗； 此外， 本实施例中， 当满足关断条件时， 关断控制单元 605关断重要性权 值较低的比特组中比特的输出， 而保持重要性权值较高的比特组中比特的输 出， 由于重要性权值越高的比特对数据处理设备进行数据处理的影响程度越 大，所以持续输出重要性权值较高的比特组中比特可以在降低系统整体功耗的 同时保持数据处理设备的基本性能。
请参阅图 7, 本发明数据处理系统一个实施例包括：
模数转换器 701以及若干数据处理设备 702;
本实施例中的模数转换器 701可以与前述图 5或图 6中所描述的模数转换 器类似， 此处不再赘述。
本实施例中的数据处理设备 702用于接收模数转换器 701输出的数字信 号， 并根据接收到的数字信号进行数据处理。
本实施例中的数据处理系统在实际应用中可以在基站或基站控制器，或其 他网元上实现， 其中， 模数转换器可以由一块具有采集转换功能的单板实现， 各数据处理设备也可以由不同的单板实现。
可以理解的是， 本实施例中的数据处理系统中，模数转换器可以位于基站 或基站控制器， 该模数转换器可以由一块具有采集转换功能的单板实现，各数 据处理设备可以分别位于不同的网元， 具体实现方式此处不作限定。
本实施例中还提供一种基站以及基站控制器：
本实施例的基站中至少包含模数转换器， 该模数转换器可以与前述图 5 或图 6中所描述的模数转换器类似， 此处不再赘述。
本实施例的基站控制器中至少包含模数转换器，该模数转换器可以与前述 图 5或图 6中所描述的模数转换器类似， 此处不再赘述。
本实施例中的基站和基站控制器除了包括模数转换器之外，还可以包含其 他的用于通信的模块， 具体此处不作限定。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分步骤 是可以通过程序来指令相关的硬件完成，该程序可以存储于一种计算机可读存 储介质中， 上述提到的存储介质可以是只读存储器， 磁盘或光盘等。
以上对本发明所提供的一种数据处理方法、数据处理系统以及相关设备进 行了详细介绍， 对于本领域的一般技术人员， 依据本发明实施例的思想， 在具 体实施方式及应用范围上均会有改变之处， 因此， 本说明书内容不应理解为对 本发明的限制。

Claims

权 利 要 求
1、 一种数据处理方法， 其特征在于， 包括：
对模拟信号进行采样得到模拟采样值；
将所述模拟采样值进行模数转换得到数字信号；
对所述数字信号中的各比特进行拆分得到至少两个比特组；
若满足预置的关断条件， 则关断至少一个比特组中比特的输出。
2、 根据权利要求 1所述的方法， 所述方法还包括：
根据预置的关断规则以及当前采样周期获取关断标识，所述关断规则用以 表示需要关断输出的采样周期， 和 /或无需关断输出的采样周期；
若所述关断标识表示需要关断输出， 则确定满足所述预置的关断条件。
3、 根据权利要求 1所述的方法， 其特征在于， 所述关断至少一个比特组 中比特的输出之后包括：
若满足预置的恢复条件， 则恢复被关断的比特组中比特的输出。
4、 根据权利要求 2所述的方法， 其特征在于， 所述关断至少一个比特组 中比特的输出之后包括：
若满足预置的恢复条件， 则恢复被关断的比特组中比特的输出。
5、 根据权利要求 3或 4所述的方法， 所述方法还包括：
根据预置的关断规则以及当前采样周期获取关断标识，所述关断规则用以 表示需要关断输出的采样周期， 和 /或无需关断输出的采样周期；
若所述关断标识表示无需关断输出， 则确定满足所述预置的恢复条件。
6、 根据权利要求 2或 4或 5所述的方法， 其特征在于， 所述根据预置的 关断规则以及当前采样周期获取关断标识之前包括：
根据接收的触发信号触发所述根据预置的关断规则以及当前采样周期获 取关断标识的步骤。
7、 根据权利要求 1至 6中任一项所述的方法， 其特征在于， 所述对所述 数字信号中的各比特进行拆分得到至少两个比特组包括：
按照重要性权值对所述数字信号中的各比特进行拆分得到至少两个比特 组；
所述关断至少一个比特组中比特的输出包括： 关断重要性权值较低的比特组中比特的输出。
8、 根据权利要求 7所述的方法， 其特征在于， 每个模拟采样值对应 N比 特的数字信号；
所述按照重要性权值对所述数字信号中的各比特进行拆分得到至少两个 比特组包括：
将所述数字信号中的高 X位比特组成第一比特组， 将所述数字信号中的 低 Y位比特组成第二比特组， 所述 X与所述 Y之和等于所述 N;
所述第一比特组的重要性权值高于所述第二比特组的重要性权值。
9、 根据权利要求 8所述的方法， 其特征在于，
若满足预置的关断条件， 则关断所述第二比特组中比特的输出， 或关断所 述第一比特组以及第二比特组中比特的输出。
10、 根据权利要求 1至 9中任一项所述的方法， 其特征在于， 所述对所述 数字信号中的各比特进行拆分得到至少两个比特组之后包括：
对各比特组中的比特进行抗混迭数字滤波。
11、 一种模数转换器， 其特征在于， 包括：
采样单元， 用于对模拟信号进行采样得到模拟采样值；
转换单元， 用于将所述模拟采样值进行模数转换得到数字信号； 分组单元， 用于对所述数字信号中的各比特进行拆分得到至少两个比特 组；
关断控制单元， 用于当满足预置的关断条件时， 关断至少一个比特组中比 特的输出。
12、 根据权利要求 11所述的模数转换器， 其特征在于， 所述关断控制单 元还用于当满足预置的恢复条件时， 恢复被关断的比特组中比特的输出。
13、 根据权利要求 11或 12所述的模数转换器， 其特征在于， 所述分组单 元具体用于按照重要性权值对所述数字信号中的各比特进行拆分得到至少两 个比特组；
所述关断控制单元具体用于关断重要性权值较低的比特组中比特的输出。
14、 根据权利要求 11至 13中任一项所述的模数转换器， 其特征在于， 所 述模数转换器还包括： 状态校验单元， 用于根据预置的关断规则以及当前采样周期获取关断标 识， 所述关断规则用以表示需要关断输出的采样周期， 和 /或无需关断输出的 采样周期；
若所述关断标识表示需要关断输出， 则确定满足所述预置的关断条件， 并 触发所述关断控制单元关断至少一个比特组中比特的输出；
若所述关断标识表示无需关断输出， 则确定满足所述预置的恢复条件， 并 触发所述关断控制单元恢复被关断的比特组中比特的输出。
15、 根据权利要求 14所述的模数转换器， 其特征在于， 所述模数转换器 还包括：
触发单元，用于根据接收到的触发信号触发所述状态校验单元执行相应操 作。
16、 根据权利要求 11至 15中任一项所述的模数转换器， 其特征在于， 所 述模数转换器还包括：
数字滤波单元，用于对所述分组单元拆分得到的各比特组中的比特进行抗 混迭数字滤波， 并将滤波后的比特输出至所述关断控制单元。
17、 一种数据处理系统， 其特征在于， 包括：
数据处理设备， 以及如权利要求 11至 16中任一项所述的模数转换器； 所述数据处理设备用于接收所述模数转换器输出的数字信号，并根据接收 到的数字信号进行数据处理。
18、 一种基站， 其特征在于， 包括：
如权利要求 11至 16中任一项所述的模数转换器。
19、 一种基站控制器， 其特征在于， 包括：
如权利要求 11至 16中任一项所述的模数转换器。
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