WO2012056809A1 - 半導体装置、放熱部材、および、半導体装置の製造方法 - Google Patents
半導体装置、放熱部材、および、半導体装置の製造方法 Download PDFInfo
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- WO2012056809A1 WO2012056809A1 PCT/JP2011/069562 JP2011069562W WO2012056809A1 WO 2012056809 A1 WO2012056809 A1 WO 2012056809A1 JP 2011069562 W JP2011069562 W JP 2011069562W WO 2012056809 A1 WO2012056809 A1 WO 2012056809A1
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Definitions
- the present invention relates to a semiconductor device having a heat radiation fin, a heat radiation member, and a method for manufacturing the semiconductor device.
- a semiconductor device As a semiconductor device provided with fins for heat dissipation, a substrate, an insulating substrate mounted on the surface of the substrate, a semiconductor chip mounted on the insulating substrate, and a plurality of fins formed on the back surface of the substrate There is a semiconductor device having the same.
- heat generated from the semiconductor chip is conducted to the plurality of fins through the insulating substrate and the substrate, and is released to the outside from the plurality of fins.
- a semiconductor device provided with such a fin for heat dissipation for example, a conductive layer for mounting electronic components formed on the upper surface of a ceramic insulating substrate, a fin base formed on the lower surface of the insulating substrate,
- a semiconductor device having an insulating fin provided with a heat radiating fin see, for example, Patent Document 1).
- thermal contraction or thermal expansion occurs between a portion near the center of the substrate where the plurality of fins are formed and a peripheral portion of the substrate where the fins are not formed. Since the degree is different, the substrate may be warped.
- an object of the present invention is to provide a semiconductor device, a heat radiating member, and a method for manufacturing the semiconductor device in which the warpage of the substrate is suppressed while improving the heat dissipation.
- the semiconductor device includes a substrate having a front surface and a back surface including a fin forming region and a peripheral region surrounding the fin forming region, an insulating substrate mounted on the front surface, and a semiconductor chip mounted on the insulating substrate. And a plurality of fins formed on the fin formation region, and a reinforcing member formed on the substrate via a bonding member so as to overlap the peripheral region.
- the semiconductor device According to the semiconductor device, the heat radiating member, and the semiconductor device manufacturing method of the present invention, it is possible to suppress the warpage of the substrate while improving the heat dissipation.
- 1 is a top view illustrating an example of a semiconductor device according to a first embodiment. It is a bottom view showing an example of a semiconductor device concerning a 1st embodiment.
- 1 is a cross-sectional view showing an example of a semiconductor device according to a first embodiment. It is a figure which shows an example of the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is a figure which shows the semiconductor device of the modification of 1st Embodiment. It is a figure which shows the manufacturing method of the heat radiating member of the modification of 1st Embodiment. It is a figure which shows an example of the semiconductor device which concerns on 2nd Embodiment.
- FIG. 1 is a top view showing an example of the semiconductor device according to the first embodiment.
- FIG. 2 is a bottom view showing an example of the semiconductor device according to the first embodiment.
- FIG. 3 is a cross-sectional view illustrating an example of the semiconductor device according to the first embodiment.
- FIG. 3 corresponds to a cross-sectional view taken along a dotted line AA in FIG.
- the semiconductor device 100 includes a substrate 110 having a front surface 111 and a back surface 112.
- a copper alloy or an aluminum alloy is used as the material of the substrate 110.
- the copper alloy for example, a copper alloy (copper: 99.5% or more) obtained by adding a trace amount of cobalt, phosphorus, tin, nickel, and zinc to copper is used.
- C1020 1000 series to 7000 series
- the aluminum alloy for example, A3000 series, A5000 series, A6000 series, and A7000 series are used.
- an insulating substrate 130 is mounted on the surface 111 of the substrate 110 via a bonding member 120.
- solder is used for the joining member 120.
- the insulating substrate 130 includes a conductive layer 131 bonded to the bonding member 120, an insulating layer 132 formed on the conductive layer 131, and conductive layers 133a and 133b formed on the insulating layer 132 (not shown in FIG. 3). And have.
- the conductor layers 131, 133a, 133b for example, copper, aluminum, or the like is used.
- ceramic such as aluminum nitride, silicon nitride, or aluminum oxide is used.
- semiconductor chips 150a and 150b are mounted via bonding members 140a and 140b, respectively. As shown in FIG. 1, the semiconductor chips 150 a and 150 b are connected to each other or to the conductor layer 133 b by wires 151.
- solder is used for the joining members 140a and 140b.
- an insulated gate bipolar transistor Insulated Gate Bipolar Transistor: IGBT
- a free wheel diode Free Wheeling Diode: FWD
- the back surface 112 of the substrate 110 includes a fin formation region S1 surrounded by a dotted line B1 and a peripheral region S2 surrounding the fin formation region S1.
- the fin forming region S ⁇ b> 1 is located directly below the insulating substrate 130.
- a plurality of fins 170 are formed on the fin forming region S ⁇ b> 1 via the bonding member 160.
- the plurality of fins 170 are arranged in a matrix.
- the heat generated from the semiconductor chips 150a and 150b is conducted to the plurality of fins 170 through the insulating substrate 130 and the substrate 110, and is released to the outside from the plurality of fins 170.
- a brazing material such as a copper alloy or an aluminum alloy is used.
- a copper alloy for example, a phosphor copper type is used.
- aluminum alloy for example, A4000 series is used.
- a copper alloy or an aluminum alloy is used for the fin 170.
- a copper alloy for example, C1020 (1000 series) oxygen-free copper is used.
- the aluminum alloy for example, A4000 series is used.
- a reinforcing member 180 is formed on the peripheral region S2 of the back surface 112 of the substrate 110 with a bonding member 160 interposed therebetween.
- An opening 181 is provided in the reinforcing member 180. That is, the reinforcing member 180 has a frame shape.
- the reinforcing member 180 is formed on the peripheral region S2 so as to expose the fin forming region S1 through the opening 181.
- the material of the reinforcing member 180 is, for example, a copper alloy or an aluminum alloy.
- a copper alloy for example, a copper alloy (copper: 99.5% or more) obtained by adding a trace amount of cobalt, phosphorus, tin, nickel, and zinc to copper is used.
- C1000-C7000 series copper alloys are used.
- the aluminum alloy for example, A3000 series, A5000 series, A6000 series, and A7000 series are used.
- the reinforcing member 180 a material different from that of the substrate 110 is used for the reinforcing member 180. Specifically, a material harder than the substrate 110 is used for the reinforcing member 180. Further, the substrate 110 is made of a material having higher thermal conductivity than the reinforcing member 180.
- a copper alloy is used for the reinforcing member 180 and the substrate 110, for example, a hard copper alloy is selected from the C1000 series to C7000 series and used for the reinforcing member 180.
- a copper alloy having high thermal conductivity is selected and used from among C1000 series to C7000 series.
- FIG. 4 is a diagram illustrating an example of a method for manufacturing the semiconductor device according to the first embodiment.
- a heat radiating member 190 is prepared.
- the heat dissipating member 190 has a plurality of fins 170 and a reinforcing member 180 mounted on the back surface 112 of the substrate 110 via the joining member 160, and heat treatment is performed in this state, and the joining member 160 causes the substrate 110 and the plurality of fins 170 to be heat-treated. And the reinforcing member 180 is joined. That is, the plurality of fins 170 and the reinforcing member 180 are collectively bonded to the substrate 110.
- the surface of the heat dissipation member 190 may be entirely or partially plated with nickel.
- the bonding member 120, the insulating substrate 130, the bonding members 140a and 140b, and the semiconductor chips 150a and 150b are sequentially mounted on the heat dissipation member 190.
- heat treatment is performed on the structure 101 on which the components are mounted. Thereby, the board
- the reinforcing member 180 is formed on the peripheral region S2 of the back surface 112 of the substrate 110 via the bonding member 160. According to this configuration, since the peripheral portion of the substrate 110 is supported by the reinforcing member 180, the warp generated in the substrate 110 can be suppressed.
- the thermal resistance of the substrate 110 can be lowered, the heat generated from the semiconductor chips 150a and 150b can be effectively conducted to the plurality of fins 170, and heat dissipation is improved. Is possible.
- the material of the substrate 110 is reduced, and a relatively easily available roll material can be used, so that the material cost can be reduced. Further, the weight of the semiconductor device 100 can be reduced. In particular, when the semiconductor device 100 is used in a vehicle-mounted product, the effect is great because there is a strong demand for weight reduction.
- the reinforcing member 180 is formed on the back surface 112 of the substrate 110 via the bonding member 160.
- the reinforcing member 180 and the substrate 110 are composed of different parts.
- the substrate 110 is used for the reinforcing member 180. Specifically, a material harder than the substrate 110 is used for the reinforcing member 180. As a result, the peripheral portion of the substrate 110 can be more strongly supported. Further, the substrate 110 is made of a material having higher thermal conductivity than the reinforcing member 180. Thereby, the heat generated from the semiconductor chips 150a and 150b can be more effectively conducted to the plurality of fins 170.
- the fins 170 and the reinforcing member 180 are joined to the substrate 110 by the joining member 160. Since the fins 170 are joined together with the reinforcing members 180, the substrate 110 can be assembled without warping, and manufacturing is facilitated.
- FIG. 5 is a diagram illustrating a semiconductor device according to a modification of the first embodiment.
- 5A is a bottom view of the semiconductor device
- FIG. 5B is a cross-sectional view of the semiconductor device.
- the semiconductor device 100a of the modified example uses a reinforcing member 180a having a shape and arrangement different from that of the reinforcing member 180 instead of the reinforcing member 180 with respect to the semiconductor device 100.
- Other configurations are the same as those of the semiconductor device 100.
- the reinforcing member 180a is provided with a plurality of through holes 182.
- the diameter of the through hole 182 is larger than the diameter of the fin 170.
- the reinforcing member 180a is formed on the peripheral region S2 of the back surface 112 of the substrate 110 and on the fin forming region S1 so that each of the plurality of fins 170 is located in each of the plurality of through holes 182. Is formed through.
- a portion including the substrate 110, the bonding member 160, the plurality of fins 170, and the reinforcing member 180a is referred to as a heat dissipation member 190a.
- the reinforcing member 180a is formed on the peripheral region S2 of the back surface 112 of the substrate 110 via the bonding member 160. According to this configuration, since the peripheral portion of the substrate 110 is supported by the reinforcing member 180a, warping that occurs in the substrate 110 can be suppressed. Thereby, the substrate 110 can be thinned, and the heat dissipation can be improved.
- the manufacturing method of the semiconductor device 100a is the same as the manufacturing method of the semiconductor device 100 shown in FIG. That is, after the semiconductor device 100a sequentially mounts the bonding member 120, the insulating substrate 130, the bonding members 140a and 140b, and the semiconductor chips 150a and 150b on the heat dissipation member 190a, It is generated by heat treatment.
- FIG. 6 is a diagram illustrating a method for manufacturing a heat radiating member according to a modification of the first embodiment.
- a plurality of fins 170 are arranged on the back surface 112 of the substrate 110 with the bonding member 160 interposed therebetween.
- the plurality of fins 170 are not completely joined to the substrate 110.
- the reinforcing member 180 a is disposed so as to face the back surface 112 of the substrate 110.
- the reinforcing member 180a is brought into contact with the joining member 160 such that the plurality of fins 170 are positioned in the plurality of through holes 182, respectively. At this time, each of the plurality of fins 170 is aligned by each of the plurality of through holes 182 of the reinforcing member 180a.
- the reinforcing member 180a provided with the plurality of through holes 182 is arranged such that each of the plurality of fins 170 is located in each of the plurality of through holes 182.
- heat treatment is performed to bond the substrate 110 to the plurality of fins 170 and the reinforcing member 180 a by the bonding member 160.
- FIG. 7 is a diagram illustrating an example of a semiconductor device according to the second embodiment.
- 7A is a top view
- FIG. 7B corresponds to a cross-sectional view taken along dotted line AA in FIG. 7A.
- the semiconductor device 200 according to the second embodiment is obtained by forming a reinforcing member on the surface 111 of the substrate 110 as compared with the semiconductor device 100 according to the first embodiment.
- Other configurations are the same as those of the semiconductor device 100.
- the surface 111 of the substrate 110 is a region surrounded by a dotted line B2, and includes an insulating substrate mounting region S3 on which the insulating substrate 130 is mounted, and an insulating substrate mounting region S3. And a surrounding area S4.
- a reinforcing member 220 is formed on the peripheral region S4 with a joining member 210 interposed therebetween.
- the reinforcing member 220 is provided with an opening 221. That is, the reinforcing member 220 has a frame shape.
- the reinforcing member 220 is formed on the peripheral region S4 so that the insulating substrate mounting region S3 is exposed through the opening 221.
- a brazing material such as a copper alloy or an aluminum alloy is used.
- a copper alloy for example, a phosphor copper type is used.
- aluminum alloy for example, A4000 series is used.
- the material of the reinforcing member 220 is, for example, a copper alloy or an aluminum alloy.
- a copper alloy for example, a copper alloy (copper: 99.5% or more) obtained by adding a trace amount of cobalt, phosphorus, tin, nickel, and zinc to copper is used.
- C1000-C7000 series copper alloys are used.
- the aluminum alloy for example, A3000 series, A5000 series, A6000 series, and A7000 series are used.
- the reinforcing member 220 a material different from that of the substrate 110 is used for the reinforcing member 220. Specifically, a material harder than the substrate 110 is used for the reinforcing member 220. In addition, a material having higher thermal conductivity than the reinforcing member 220 is used for the substrate 110.
- FIG. 8 is a diagram illustrating an example of a method of manufacturing a semiconductor device according to the second embodiment.
- a heat radiating member 230 is prepared.
- the plurality of fins 170 and the reinforcing member 180 are mounted on the back surface 112 of the substrate 110 via the bonding member 160, and further, the bonding member 210 is mounted on the surface 111 of the substrate 110.
- the reinforcing member 220 is mounted via
- the substrate 110 is bonded to the plurality of fins 170 and the reinforcing member 180 by the bonding member 160, and the substrate 110 and the reinforcing member 220 are bonded to each other by the bonding member 210. That is, the plurality of fins 170 and the reinforcing members 180 and 220 are collectively bonded to the substrate 110. Thereby, the heat radiating member 230 is produced
- the surface of the heat radiating member 230 may be entirely or partially nickel-plated.
- the bonding member 120, the insulating substrate 130, the bonding members 140a and 140b, and the semiconductor chips 150a and 150b are sequentially mounted on the heat dissipation member 230.
- heat treatment is performed on the structure 201 on which the components are mounted. Thereby, the board
- the reinforcing member 180 is formed on the peripheral region S2 of the back surface 112 of the substrate 110 via the bonding member 160. According to this configuration, since the peripheral portion of the substrate 110 is supported by the reinforcing member 180, the warp generated in the substrate 110 can be suppressed. Thereby, the substrate 110 can be thinned, and the heat dissipation can be improved.
- the reinforcing member 220 is formed on the peripheral region S 4 of the surface 111 of the substrate 110 via the bonding member 210. According to this configuration, since the peripheral portion of the substrate 110 is supported by the reinforcing member 220, it is possible to more effectively suppress the warp generated in the substrate 110. In the semiconductor device 200, the reinforcing member 180 can be deleted.
- FIG. 9 is a diagram illustrating a semiconductor device according to a modification of the second embodiment.
- 9A shows a top view of the semiconductor device
- FIG. 9B corresponds to a cross-sectional view taken along a dotted line AA in FIG. 9A.
- the semiconductor device 200a of the modified example is obtained by mounting a plurality of insulating substrates 240, 250, and 260 on the substrate 110 instead of the insulating substrate 130 with respect to the semiconductor device 200. Further, the semiconductor device 200a uses a reinforcing member 220a having a shape different from that of the reinforcing member 220 instead of the reinforcing member 220 with respect to the semiconductor device 200. Other configurations are the same as those of the semiconductor device 200.
- insulating substrates 240 to 260 are mounted on the surface 111 of the substrate 110 with a bonding member 210 interposed therebetween.
- Each of the insulating substrates 240 to 260 has the same configuration as that of the insulating substrate 130 of the semiconductor device 200.
- semiconductor chips 270a and 270b are mounted on the insulating substrate 240 via the bonding member 271.
- semiconductor chips 280a and 280b are mounted via a bonding member 272.
- semiconductor chips 290a and 290b are mounted via a bonding member 273.
- solder is used as a material.
- the reinforcing member 220a is provided with an opening 221a and a plurality of protrusions 222, 223, 224, and 225 protruding into the opening 221a.
- the reinforcing member 220a is formed on the peripheral region S4 so that the insulating substrate mounting region S3 is exposed through the opening 221a.
- the insulating substrates 240 to 260 are disposed in the opening 221a with the protrusions 222 to 225 as boundaries.
- the insulating substrates 240 and 250 are respectively disposed in the opening 221a, and the dotted line B4 connecting the protruding portion 223 and the protruding portion 225 is shown.
- Insulating substrates 250 and 260 are disposed in the openings 221a, respectively, as boundaries.
- a portion including the substrate 110, the joining members 160 and 210, the plurality of fins 170, and the reinforcing members 180 and 220a is referred to as a heat dissipation member 230a.
- the reinforcing member 220a is formed on the peripheral region S4 of the surface 111 of the substrate 110 via the bonding member 210. According to this configuration, since the peripheral portion of the substrate 110 is supported by the reinforcing member 220a, it is possible to more effectively suppress the warp generated in the substrate 110.
- the manufacturing method of the semiconductor device 200a is the same as the manufacturing method of the semiconductor device 200 shown in FIG. That is, the semiconductor device 200a sequentially mounts the bonding member 120, the insulating substrates 240 to 260, the bonding members 271 to 273, and the semiconductor chips 270a, 270b, 280a, 280b, 290a, and 290b on the heat dissipation member 230a, It is generated by performing heat treatment on the structure on which each component is mounted.
- the alignment is performed using the protrusions 222 to 225 provided on the reinforcing member 220a as marks. .
- alignment is performed using the protrusions 222 and 224 as marks, and with respect to the insulating substrate 250, the position is determined using the protrusions 222 and 224 or the protrusions 223 and 225 as marks.
- the insulating substrate 260 is aligned with the protrusions 223 and 225 as marks.
- the insulating substrates 240 to 260 are mounted on the substrate 110 with the protruding portions 222 to 225 provided on the reinforcing member 220a as marks. According to this configuration, since it is possible to align the insulating substrates 240 to 260 without using a jig or the like, the manufacturing process can be simplified.
- FIG. 10 is a cross-sectional view showing an example of a semiconductor device according to the third embodiment.
- the semiconductor device 300 according to the third embodiment is a bonding member that joins the substrate 110, the insulating substrate 130, and the reinforcing member 220 to the semiconductor device 200 according to the second embodiment. Instead, the joining member 210a is used. Other configurations are the same as those of the semiconductor device 200.
- the insulating substrate 130 and the reinforcing member 220 are mounted or formed on the surface 111 of the substrate 110 via a bonding member 210a.
- a brazing material such as a copper alloy or an aluminum alloy is used.
- the copper alloy for example, a phosphor copper type is used.
- the aluminum alloy for example, A4000 series is used.
- FIG. 11 is a diagram illustrating an example of a method of manufacturing a semiconductor device according to the third embodiment.
- a laminate in which an insulating substrate 130 is mounted on a heat dissipation member 310 is prepared.
- a plurality of fins 170 and reinforcing members 180 are mounted on the back surface 112 of the substrate 110 via the bonding member 160, and further, the bonding member 210 a is mounted on the surface 111 of the substrate 110.
- the insulating substrate 130 and the reinforcing member 220 are mounted via
- the substrate 110, the plurality of fins 170, and the reinforcing member 180 are bonded by the bonding member 160, and the substrate 110, the insulating substrate 130, and the reinforcing member 220 are bonded by the bonding member 210a. That is, the plurality of fins 170, the reinforcing members 180 and 220, and the insulating substrate 130 are bonded together to the substrate 110. Thereby, a laminated body in which the insulating substrate 130 is mounted on the heat dissipation member 310 is generated.
- the joining members 140a and 140b and the semiconductor chips 150a and 150b are sequentially mounted on the stacked body.
- heat treatment is performed on the structure 301 on which the components are mounted.
- the insulating substrate 130 and the semiconductor chips 150a and 150b are bonded by the bonding members 140a and 140b. In this way, the semiconductor device 300 is generated.
- the reinforcing member 180 is formed on the peripheral region S2 of the back surface 112 of the substrate 110 via the bonding member 160. According to this configuration, since the peripheral portion of the substrate 110 is supported by the reinforcing member 180, the warp generated in the substrate 110 can be suppressed. Thereby, the substrate 110 can be thinned, and the heat dissipation can be improved.
- the reinforcing member 220 is formed on the peripheral region S4 of the surface 111 of the substrate 110 via the bonding member 210a. According to this configuration, since the peripheral portion of the substrate 110 is supported by the reinforcing member 220, it is possible to more effectively suppress the warp generated in the substrate 110.
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Abstract
Description
このような放熱用のフィンを備えた半導体装置としては、例えば、セラミックス製の絶縁基板の上面に形成された電子部品搭載用の導電層と、絶縁基板の下面に形成されたフィンベースと、複数の放熱フィンとを備えている絶縁フィンを有する半導体装置がある(例えば、特許文献1参照)。
この半導体装置は、表面と、フィン形成領域とフィン形成領域を取り囲む周辺領域とを含む裏面とを備えた基板と、表面上に搭載された絶縁基板と、絶縁基板上に搭載された半導体チップと、フィン形成領域上に形成された複数のフィンと、周辺領域と重なるように、基板に接合部材を介して形成された補強部材と、を有する。
本発明の上記および他の目的、特徴および利点は本発明の例として好ましい実施の形態を表す添付の図面と関連した以下の説明により明らかになるであろう。
[第1の実施の形態]
図1は、第1の実施の形態に係る半導体装置の一例を示す上面図である。図2は、第1の実施の形態に係る半導体装置の一例を示す下面図である。図3は、第1の実施の形態に係る半導体装置の一例を示す断面図である。ここで、図3は、図1の点線A-Aにおける断面図に相当する。
絶縁基板130は、接合部材120と接合された導体層131と、導体層131上に形成された絶縁層132と、絶縁層132上に形成された導体層133a,133b(図3では不図示)とを有している。導体層131,133a,133bには、例えば、銅、または、アルミ等が用いられている。絶縁層132には、例えば、窒化アルミニウム、窒化シリコン、または、酸化アルミニウム等のセラミックスが用いられている。
次に、半導体装置100の製造方法について説明する。図4は、第1の実施の形態に係る半導体装置の製造方法の一例を示す図である。
次に、図4(B)に示すように、各部品が搭載された構造体101に、熱処理を施す。これにより、接合部材120により基板110と絶縁基板130とが接合し、接合部材140a,140bにより、絶縁基板130と半導体チップ150a,150bとが接合する。このようにして、半導体装置100が生成される。
次に、半導体装置100の変形例について説明する。図5は、第1の実施の形態の変形例の半導体装置を示す図である。図5(A)は、半導体装置の下面図を示し、図5(B)は、半導体装置の断面図を示す。
半導体装置100aにおいても、基板110の裏面112の周辺領域S2上に、接合部材160を介して補強部材180aが形成されている。この構成によれば、補強部材180aにより基板110の周辺部分が支持されるため、基板110に発生する反りを抑制することができる。また、これにより、基板110を薄くすることができ、放熱性を向上させることが可能となる。
まず、図6(A)に示すように、基板110の裏面112上に接合部材160を介して複数のフィン170を配置する。ここで、複数のフィン170は、基板110に完全には接合されていない。そして、基板110の裏面112と対向するように、補強部材180aを配置する。
[第2の実施の形態]
次に、第2の実施の形態の半導体装置について説明する。図7は、第2の実施の形態に係る半導体装置の一例を示す図である。図7(A)は、上面図であり、図7(B)は、図7(A)の点線A-Aにおける断面図に相当する。
次に、半導体装置200の製造方法について説明する。図8は、第2の実施の形態に係る半導体装置の製造方法の一例を示す図である。
次に、図8(B)に示すように、各部品が搭載された構造体201に、熱処理を施す。これにより、接合部材120により基板110と絶縁基板130とが接合し、接合部材140a,140bにより、絶縁基板130と半導体チップ150a,150bとが接合する。このようにして、半導体装置200が生成される。
次に、半導体装置200の変形例について説明する。図9は、第2の実施の形態の変形例の半導体装置を示す図である。図9(A)は、半導体装置の上面図を示し、図9(B)は、図9(A)の点線A-Aにおける断面図に相当する。
次に、第3の実施の形態の半導体装置について説明する。図10は、第3の実施の形態に係る半導体装置の一例を示す断面図である。
次に、半導体装置300の製造方法について説明する。図11は、第3の実施の形態に係る半導体装置の製造方法の一例を示す図である。
次に、図11(B)に示すように、各部品が搭載された構造体301に、熱処理を施す。これにより、接合部材140a,140bにより、絶縁基板130と半導体チップ150a,150bとが接合する。このようにして、半導体装置300が生成される。
101,201,301 構造体
110 基板
111 表面
112 裏面
120,140a,140b,160,210,210a,271,272,273 接合部材
130,240,250,260 絶縁基板
131,133a,133b 導体層
132 絶縁層
150a,150b,270a,270b,280a,280b,290a,290b 半導体チップ
151 ワイヤ
170 フィン
180,180a,220,220a 補強部材
181,221,221a 開口部
182 貫通孔
190,190a,230,230a,310 放熱部材
222,223,224,225 突出部
S1 フィン形成領域
S2,S4 周辺領域
S3 絶縁基板搭載領域
Claims (19)
- 表面と、フィン形成領域と前記フィン形成領域を取り囲む周辺領域とを含む裏面とを備えた基板と、
前記表面上に搭載された絶縁基板と、
前記絶縁基板上に搭載された半導体チップと、
前記フィン形成領域上に形成された複数のフィンと、
前記周辺領域と重なるように、前記基板に接合部材を介して形成された補強部材と、
を有することを特徴とする半導体装置。 - 前記補強部材には、前記基板とは異なる材料が用いられていることを特徴とする請求の範囲第1項記載の半導体装置。
- 前記補強部材には、前記基板よりも硬い材料が用いられていることを特徴とする請求の範囲第2項記載の半導体装置。
- 前記基板には、前記補強部材よりも熱伝導性が高い材料が用いられていることを特徴とする請求の範囲第2項または第3項記載の半導体装置。
- 前記補強部材は、前記周辺領域上に前記接合部材を介して形成されていることを特徴とする請求の範囲第1項~第4項のいずれか1項に記載の半導体装置。
- 前記補強部材には開口部が設けられ、前記補強部材は、前記開口部により前記フィン形成領域を露出するように、前記周辺領域上に形成されていることを特徴とする請求の範囲第5項記載の半導体装置。
- 前記補強部材には複数の貫通孔が設けられ、前記補強部材は、前記複数のフィンのそれぞれが前記複数の貫通孔のそれぞれの内に位置するように、前記周辺領域上および前記フィン形成領域上に形成されていることを特徴とする請求の範囲第5項または第6項記載の半導体装置。
- 前記基板の前記表面は、絶縁基板搭載領域と前記絶縁基板搭載領域を取り囲む周辺領域とを備え、
前記絶縁基板は、前記絶縁基板搭載領域上に搭載され、
前記表面の周辺領域上に接合部材を介して補強部材が形成されていることを特徴とする請求の範囲第5項~第7項のいずれか1項に記載の半導体装置。 - 前記絶縁基板は、前記表面の周辺領域上の前記接合部材と同じ材料を用いた接合部材を介して、前記絶縁基板搭載領域上に搭載されていることを特徴とする請求の範囲第8項記載の半導体装置。
- 前記基板の前記表面上には前記絶縁基板が複数個搭載され、
前記表面上の前記補強部材には、開口部と前記開口部に突出する突出部とが設けられ、
前記複数の絶縁基板はそれぞれ、前記突出部を境界にして、前記開口部内に配置されていることを特徴とする請求の範囲第8項または第9項記載の半導体装置。 - 前記基板の前記表面は、絶縁基板搭載領域と前記絶縁基板搭載領域を取り囲む周辺領域とを備え、
前記絶縁基板は、前記絶縁基板搭載領域上に搭載され、
前記表面の周辺領域上に前記接合部材を介して前記補強部材が形成されていることを特徴とする請求の範囲第1項~第4項のいずれか1項に記載の半導体装置。 - 絶縁基板搭載領域を含む表面と、フィン形成領域と前記フィン形成領域を取り囲む周辺領域とを含む裏面とを備えた基板と、
前記フィン形成領域上に形成された複数のフィンと、
前記周辺領域と重なるように、前記基板に接合部材を介して形成された補強部材と、
を有することを特徴とする放熱部材。 - 前記補強部材には、前記基板とは異なる材料が用いられていることを特徴とする請求の範囲第12項記載の放熱部材。
- 前記補強部材には、前記基板よりも硬い材料が用いられていることを特徴とする請求の範囲第13項記載の放熱部材。
- 前記基板には、前記補強部材よりも熱伝導性が高い材料が用いられていることを特徴とする請求の範囲第13項または第14項記載の放熱部材。
- 前記補強部材は、前記周辺領域上に前記接合部材を介して形成されていることを特徴とする請求の範囲第12項~第15項のいずれか1項に記載の放熱部材。
- 前記基板の前記表面は、前記絶縁基板搭載領域を取り囲む周辺領域を備え、
前記表面の周辺領域上に接合部材を介して補強部材が形成されていることを特徴とする請求の範囲第12項~第16項のいずれか1項に記載の放熱部材。 - 表面と、フィン形成領域と前記フィン形成領域を取り囲む周辺領域とを含む裏面とを備えた基板の、前記フィン形成領域上に接合部材を介して複数のフィンを配置する工程と、
複数の貫通孔が設けられた補強部材を、前記複数のフィンのそれぞれが前記複数の貫通孔のそれぞれの内に位置するように、前記周辺領域上および前記フィン形成領域上に前記接合部材を介して配置する工程と、
前記補強部材が配置された前記基板に熱処理を施して、前記接合部材により前記基板と前記複数のフィンおよび前記補強部材とを接合させる工程と、
前記表面上に絶縁基板を搭載する工程と、
前記絶縁基板上に半導体チップを搭載する工程と、
を有することを特徴とする半導体装置の製造方法。 - 絶縁基板搭載領域と前記絶縁基板搭載領域を取り囲む周辺領域とを含む表面と、フィン形成領域を含む裏面とを備え、前記フィン形成領域上に複数のフィンが形成され、かつ、前記表面の周辺領域上に開口部と前記開口部に突出する突出部とが設けられた補強部材が前記開口部により前記絶縁基板搭載領域を露出するように接合部材を介して形成された基板の、前記絶縁基板搭載領域上に、複数の絶縁基板をそれぞれ、前記突出部を目印にして搭載する工程と、
前記複数の絶縁基板のそれぞれの上に、半導体チップを搭載する工程と、
を有することを特徴とする半導体装置の製造方法。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140083671A1 (en) * | 2012-09-27 | 2014-03-27 | Dowa Metaltech Co., Ltd. | Heat radiating plate and method for producing same |
JP7463825B2 (ja) | 2020-04-27 | 2024-04-09 | 富士電機株式会社 | 半導体モジュールおよび車両 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2017086324A1 (ja) * | 2015-11-16 | 2017-05-26 | 株式会社豊田中央研究所 | 接合構造体およびその製造方法 |
US11488903B2 (en) | 2020-01-28 | 2022-11-01 | Littelfuse, Inc. | Semiconductor chip package and method of assembly |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004022914A (ja) * | 2002-06-19 | 2004-01-22 | Hitachi Ltd | 絶縁回路基板とその冷却構造及ぴパワー半導体装置とその冷却構造 |
JP2010182831A (ja) * | 2009-02-04 | 2010-08-19 | Toyota Industries Corp | 半導体装置 |
JP2010238963A (ja) * | 2009-03-31 | 2010-10-21 | Mitsubishi Materials Corp | パワーモジュール用基板、パワーモジュール用基板の製造方法及びパワーモジュール |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5937514A (en) * | 1997-02-25 | 1999-08-17 | Li; Chou H. | Method of making a heat-resistant system |
US5964285A (en) * | 1999-02-12 | 1999-10-12 | Yung-Tsai Chu | Heat sink |
JP2009026957A (ja) | 2007-07-19 | 2009-02-05 | Ngk Insulators Ltd | 絶縁フィン及びヒートシンク |
JP5700034B2 (ja) * | 2009-08-10 | 2015-04-15 | 富士電機株式会社 | 半導体モジュール及び冷却器 |
-
2011
- 2011-08-30 US US13/814,852 patent/US9299633B2/en not_active Expired - Fee Related
- 2011-08-30 WO PCT/JP2011/069562 patent/WO2012056809A1/ja active Application Filing
- 2011-08-30 JP JP2012540729A patent/JP5720694B2/ja not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004022914A (ja) * | 2002-06-19 | 2004-01-22 | Hitachi Ltd | 絶縁回路基板とその冷却構造及ぴパワー半導体装置とその冷却構造 |
JP2010182831A (ja) * | 2009-02-04 | 2010-08-19 | Toyota Industries Corp | 半導体装置 |
JP2010238963A (ja) * | 2009-03-31 | 2010-10-21 | Mitsubishi Materials Corp | パワーモジュール用基板、パワーモジュール用基板の製造方法及びパワーモジュール |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140083671A1 (en) * | 2012-09-27 | 2014-03-27 | Dowa Metaltech Co., Ltd. | Heat radiating plate and method for producing same |
CN103700636A (zh) * | 2012-09-27 | 2014-04-02 | 同和金属技术有限公司 | 散热板及其生产方法 |
JP7463825B2 (ja) | 2020-04-27 | 2024-04-09 | 富士電機株式会社 | 半導体モジュールおよび車両 |
Also Published As
Publication number | Publication date |
---|---|
US20130200510A1 (en) | 2013-08-08 |
JP5720694B2 (ja) | 2015-05-20 |
US9299633B2 (en) | 2016-03-29 |
JPWO2012056809A1 (ja) | 2014-03-20 |
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