WO2012053687A1 - 동작 중 재구성이 가능한 제어 시스템 및 그 방법 - Google Patents

동작 중 재구성이 가능한 제어 시스템 및 그 방법 Download PDF

Info

Publication number
WO2012053687A1
WO2012053687A1 PCT/KR2010/007795 KR2010007795W WO2012053687A1 WO 2012053687 A1 WO2012053687 A1 WO 2012053687A1 KR 2010007795 W KR2010007795 W KR 2010007795W WO 2012053687 A1 WO2012053687 A1 WO 2012053687A1
Authority
WO
WIPO (PCT)
Prior art keywords
information
reconfiguration
reconstruction
gate array
module
Prior art date
Application number
PCT/KR2010/007795
Other languages
English (en)
French (fr)
Korean (ko)
Inventor
최성훈
김민수
박영준
하영열
Original Assignee
삼성중공업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020100103627A external-priority patent/KR101259133B1/ko
Application filed by 삼성중공업 주식회사 filed Critical 삼성중공업 주식회사
Priority to DE112010005955T priority Critical patent/DE112010005955T5/de
Priority to JP2013534789A priority patent/JP5646764B2/ja
Priority to US13/880,700 priority patent/US10095201B2/en
Priority to CN201080069761.2A priority patent/CN103262405B/zh
Publication of WO2012053687A1 publication Critical patent/WO2012053687A1/ko

Links

Images

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/18—Numerical control [NC], i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form
    • G05B19/404—Numerical control [NC], i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by control arrangements for compensation, e.g. for backlash, overshoot, tool offset, tool wear, temperature, machine construction errors, load, inertia
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/30—Nc systems
    • G05B2219/34—Director, elements to supervisory
    • G05B2219/34024—Fpga fieldprogrammable gate arrays

Definitions

  • the present invention relates to a control system and a method thereof, and more particularly, to a control system and a method capable of reconfiguring in operation.
  • Devices such as robots use servo motors for operation.
  • the operation of the device can be controlled through the control of the servo motor.
  • operation control is performed using a master controller and a slave controller.
  • the master controller sends a control signal to each slave controller, and the slave controller controls the corresponding servo motor according to the control signal.
  • the master controller can be connected with a plurality of slave controllers, each slave controller controlling a corresponding servo motor.
  • the slave controller generally mounts a functional board package suitable for the operation of the servo motor.
  • the slave controller has a problem in that it can control only the corresponding servo motor. That is, there is a problem that the slave controller needs to be replaced when changing the servo motor to another model.
  • An object of the present invention is to provide a control system and method capable of reconfiguring an operation of changing a control scheme of a device by reconfiguring a structure of a field array (FPGA) while maintaining control of the device.
  • FPGA field array
  • a master controller for generating a bitstream including reconfiguration information according to a user command; And a first slave controller, wherein the first slave controller comprises: a first dynamic reconfiguration module (FPGA) which is reconfigured according to the reconfiguration information to produce a control value; A static reconfiguration module which is a gate array controlling an operation of a target device according to the control value; And a control unit configured to reconfigure at least one of the first dynamic reconfiguration module and the static reconfiguration module according to the reconfiguration information.
  • FPGA first dynamic reconfiguration module
  • the controller may reconfigure the gate array structure of the dynamic reconfiguration module independently of the operation of the static reconfiguration module.
  • the slave controller may further include a second dynamic reconfiguration module, which is a gate array reconfigured according to the reconfiguration information to calculate a control value.
  • the controller may further include the reconfiguration information when the capacity of the reconfiguration information is equal to or greater than a specified value. Accordingly, the second dynamic reconfiguration module may be controlled to be reconfigured, and the operation of the first dynamic reconfiguration module may be maintained until the reconfiguration of the second dynamic reconfiguration module is completed.
  • the controller may stop the operation of the first dynamic reconfiguration module when the reconfiguration of the second dynamic reconfiguration module is completed.
  • the master controller may further include a reconfiguration library storage unit for storing function information indicating a connection relationship between the gates of the first dynamic reconfiguration module or the static reconfiguration module; A reconstruction information combination unit configured to extract the function information according to the command and generate the reconstruction information by combining the extracted function information; And an entry manager to generate a bitstream including the reconfiguration information.
  • the slave communication unit may further include a slave communication unit configured to transmit the bitstream to the first slave controller, wherein the entry manager generates reconfiguration time information at which it is time to transmit the bitstream according to the command.
  • the bitstream may be transmitted to the first slave controller when a predetermined period arrives or when the bitstream is generated according to time information.
  • the method may further include a second slave controller which is a controller having the same configuration as the first slave controller, wherein the master controller includes the bitstream including reconfiguration information corresponding to each of the first slave controller and the second slave controller. Can be generated.
  • a second slave controller which is a controller having the same configuration as the first slave controller, wherein the master controller includes the bitstream including reconfiguration information corresponding to each of the first slave controller and the second slave controller. Can be generated.
  • the master controller, the first slave controller and the second slave controller may be connected to a network of a dual ring structure.
  • the static reconfiguration module may be a gate array reconfigured according to the reconfiguration information.
  • a method for controlling an operation of a target device by a reconfigurable control system comprising: generating a bitstream including reconfiguration information according to a user's command; Reconstructing a first gate array (FPGA) that is reconstructed according to the reconstruction information to produce a control value; Calculating a control value using the reconstructed gate array; And transmitting the control value to a second gate array that controls an operation of the target device.
  • FPGA first gate array
  • reconstructing the first gate array may be independent of the operation of the second gate array.
  • the method may further include reconfiguring a third gate array configured to be reconfigured according to the reconstruction information and calculating a control value when the capacity of the reconstruction information is equal to or greater than a specified value, until the reconstruction of the third gate array is completed. Operation of the first gate array can be maintained.
  • the method may further include stopping the operation of the first gate array when the reconstruction of the third gate array is completed.
  • the generating of the bitstream may include extracting the function information from a storage space of the control system that stores function information indicating a connection relationship between each gate of the first gate array or the second gate array according to the command. Making; Generating the reconstruction information by combining the extracted function information; And generating a bitstream including the reconstruction information.
  • FIG. 2 illustrates the structure of a bitstream generated by a master controller of a control system.
  • FIG. 3 is a block diagram conceptually illustrating a configuration of a master controller.
  • FIG. 4 is a diagram illustrating a process in which a master controller generates reconfiguration information.
  • FIG. 5 is a block diagram schematically illustrating a functional unit configuring a first slave controller.
  • FIG. 6 is a flowchart illustrating a process in which a control system controls the operation of a servo motor.
  • FIG. 1 is a view showing a control system capable of reconfiguring during operation according to an embodiment of the present invention.
  • a control system includes a master controller 101, a first slave controller 102, and a second slave controller 103. Although two slave controllers are illustrated in FIG. 1, the control system according to an embodiment of the present invention may include various numbers of slave controllers according to an environment to which the present invention is applied. In addition, each slave controller may be connected to one or more sensors that sense acceleration, heat generation, etc. for each servo motor and the corresponding servo motor.
  • the master controller 101 receives a command for an operation to control the operation from an input device (for example, a PC) (not shown).
  • the command received from the input device is a signal indicating a command to operate according to any one of the patterns of the servo motor operation.
  • the master controller 101 matches the received command with one or more reconfiguration information instructing reconfiguration of the field programmable gate array (FPGA) included in each slave controller. Can be stored.
  • the master controller 101 may generate a bitstream including a command received from an input device and reconfiguration information matching the command.
  • the master controller 101 may include first reconfiguration information and a second slave controller corresponding to the first slave controller 102.
  • One or more of the second reconstruction information corresponding to 103 may be generated to generate a bitstream.
  • FIG. 2 illustrates a structure of a bitstream generated by a master controller of a control system according to an exemplary embodiment of the present invention.
  • the master controller 101 controls the first slave controller 102 and the second slave controller to control servo motors respectively connected to the first slave controller 102 and the second slave controller 103 according to a command received from the input device.
  • a bitstream including reconfiguration information indicating reconfiguration of the FPGA included in 103 is generated.
  • the master controller 101 allows the reconfiguration information to be located after the slave identification information, which is information for identifying each slave controller, in the bitstream, so that each slave controller can easily extract the corresponding reconfiguration information.
  • the first slave identification information 210 and the first reconfiguration information 220 illustrated in FIG. 2 are slave identification information and reconfiguration information corresponding to the first slave controller 102
  • the second slave identification information ( 230 and the second reconfiguration information 240 are slave identification information and reconfiguration information corresponding to the second slave controller 103.
  • the first slave controller 102 retrieves the first slave identification information 210 included in the bitstream, and reconstructs the data from the first slave identification information 210 to the first slave identification information before the next slave identification information 220. ), And the first reconstruction information 220 may be extracted from the bitstream.
  • the master controller 101 may periodically generate a plurality of bitstreams for a command received from an input device.
  • a command received from an input device is a command for instructing the servo motor to alternately perform a process of operation and stop every predetermined period.
  • the master controller 101 may alternately generate a bitstream including reconfiguration information for performing the operation of the servo motor and a bitstream including reconfiguration information for stopping the servo motor at predetermined cycles.
  • the configuration of the master controller 101 will be described in detail with reference to FIG. 3.
  • the master controller 101 includes a host communication unit 310, a reconfiguration information combination unit 320, a reconfiguration library storage unit 330, an entry manager 340, and a slave communication unit 350.
  • the host communicator 310 receives a user's command from an input device through a network.
  • the host communicator 310 transmits the received command to the reconfiguration information combiner 320.
  • the reconfiguration information combination unit 320 extracts one or more function information stored in the reconfiguration library storage unit according to a command received from the host communication unit 310, and generates reconfiguration information by combining the extracted function information.
  • the function information according to the embodiment of the present invention may include information on the connection relationship between the gates of the FPGA of the slave controller, it may be represented in various ways such as a bit string.
  • the FPGA according to the embodiment of the present invention may perform a specific function when reconfigured according to the function information. The process of generating reconfiguration information will be described in detail later with reference to FIG. 4.
  • the reconstruction information combination unit 320 transmits the generated reconstruction information to the entry manager 340.
  • the entry manager 340 generates reconstruction time information and reconstruction mode information based on the reconstruction information received from the reconstruction information combination unit 320.
  • the reconfiguration time information is information indicating whether the time point at which the bitstream including the reconstruction information is transmitted is immediately transmitted or the time point at which the slave communication unit 350 periodically transmits the bitstream.
  • the reconfiguration mode information is information indicating whether each slave controller receiving the corresponding bitstream reconfigures the FPGA.
  • the entry manager 340 inserts reconfiguration mode information into reconfiguration information, generates a bitstream including each reconfiguration information and slave identification information, and transmits the reconstruction information to the slave communication unit 350 along with reconfiguration time information.
  • the slave communication unit 350 transmits the bitstream to the first slave controller 102 or the second slave controller 103 according to the reconfiguration time information. That is, when the slave communication unit 350 indicates that the reconstruction time information immediately transmits the bitstream, the slave communication unit 350 immediately transmits the bitstream to the slave controller, and when the reconstruction time information indicates transmitting the bitstream according to the transmission period, The stream is transmitted when the transmission period specified in the slave communication unit 350 arrives.
  • the master controller 101 transmits the generated bitstream to the first slave controller 102.
  • the master controller 101 may be connected to the first slave controller 102 and the second slave controller 103 in a double ring structure. That is, the second slave controller 103 may not receive the bitstream transmitted by the master controller 101 to the first slave controller 102.
  • the master controller 101 can transmit the generated bitstream back to the second slave controller 103. Therefore, according to the exemplary embodiment of the present invention, even if some of the networks between the master controller 101, the first slave controller 102, and the second slave controller 103 are disconnected, it can be operated normally.
  • the first slave controller 102 extracts reconfiguration information from the bitstream received from the master controller 101, reconfigures the FPGA according to the reconfiguration information, and controls the servo motor using the reconfigured FPGA.
  • the structure of the first slave controller 102 will be described in detail with reference to FIG. 5.
  • FIG. 4 is a diagram illustrating a process of generating reconfiguration information by a master controller.
  • the reconstruction information combining unit 320 of the master controller 101 receives a command from an input device.
  • the reconstruction information combination unit 320 extracts necessary function information from the reconstruction library storage unit 330 according to the received command.
  • the reconfiguration library storage unit 330 stores one or more function information, and the reconfiguration information combination unit 320 may store in advance a list of function information required for reconfiguration of the FPGA according to each command that may be received from a user. Therefore, upon receiving the command, the reconstruction information combination unit 320 retrieves a list of function information matching the command, extracts the function information included in the searched list from the reconstruction library storage unit 330, and combines the function information. To generate reconstruction information.
  • the reconstruction library storage unit 330 includes function information on an algorithm to be performed by a slave controller, function information indicating a function of receiving data from a sensor performing a sensing function of a servo motor, and controlling actual motor driving. Function information indicating the function can be stored.
  • the reconstruction information combination unit 320 receives the command 1 from the input device 410 and retrieves a list of the stored function information matching the command 1.
  • the reconstruction information combining unit 320 confirms that the function information included in the list of the function information is algorithm 1, sensor input 1, and motor driving 2, and extracts each function information from the reconstruction library storage unit 330.
  • the reconstruction information combination unit 320 generates the reconstruction information 420 corresponding to the command 1 by combining the extracted function information.
  • the reconfiguration information combiner 320 may transmit the reconfiguration information 420 to the entry manager 340.
  • the master controller 101 has been described as generating reconstruction information by extracting and combining function information from the reconstruction information combination unit 320, but the reconstruction information itself corresponding to each command in advance in the reconstruction information combination unit 320 is described.
  • the reconfiguration information combination unit 320 may transmit reconfiguration information corresponding to the command to the entry manager 340. Accordingly, the master controller 101 may extract reconfiguration information and transmit the reconfiguration information to the entry manager 340 without a separate function information combining process.
  • the first slave controller 102 includes a controller 510 and a reconstructor 520.
  • the controller 510 receives the bitstream from the master controller 101 and extracts reconstruction information from the bitstream.
  • the controller 510 checks whether reconfiguration mode information included in the reconfiguration information indicates reconfiguration of the FPGA. If the reconfiguration mode information does not indicate reconfiguration of the FPGA, the controller 510 does not perform a reconfiguration process of the FPGA.
  • the controller 510 reconstructs the gate array structure of the reconstruction unit 520 according to the reconstruction information. For example, an FPGA structure in which reconstruction information receives data according to sensing of a servo motor from a sensor, calculates the received data according to a predetermined algorithm, and controls the servo motor according to the calculated result. In this case, the controller 510 controls the reconstruction unit 520 to reconfigure the FPGA according to the reconfiguration information.
  • the controller 510 may determine the reconfiguration information corresponding to the corresponding slave controller in the bitstream. It can be determined whether or not FPGA reconfiguration should be performed based on the inclusion.
  • the reconstruction unit 520 includes a static reconstruction module 523, a first dynamic reconstruction module 526, and a second dynamic reconstruction module 529 configured as FPGAs.
  • the static reconfiguration module 523 controls the operation of the servo motor.
  • the static reconfiguration module 523 controls the operation of the servo motor.
  • the static reconfiguration module 523 controls the operation of the servo motor. It can be controlled to perform rotational acceleration, reverse rotational acceleration, stop, and the like. Since the static reconfiguration module 523 directly controls the operation of the servo motor, reconfiguration is not performed while the first slave controller 102 controls the servo motor. However, the static reconfiguration module 523 may perform reconfiguration when the servo motor is replaced with another type of device.
  • the master controller 101 when the user commands the control of the other type of devices replaced through the input device, the master controller 101 includes reconfiguration information indicating the reconfiguration of the static reconfiguration unit 523 to correspond to the command
  • the bitstream may be transmitted to the controller 510 of the first slave controller 102.
  • the controller 510 reconfigures the gate array structure of the static reconstruction unit 523 according to the reconstruction information included in the bitstream so as to control the replaced other type of device.
  • the first dynamic reconfiguration module 526 is reconfigured from the FPGA independently of the static reconfiguration module 523 under the control of the controller 510. That is, the first dynamic reconfiguration module 526 is reconfigured regardless of whether the static reconfiguration module 523 is currently controlling or reconfiguring the servo motor.
  • the dynamic reconfiguration module 526 receives the rotational speed of the servo motor from a sensor that detects the rotational speed of the servo motor, and calculates according to an algorithm determined for the rotational speed of the servo motor when the rotational speed is equal to or greater than a specified speed. Can be performed.
  • the dynamic reconfiguration module 323 may transmit the control value that is the result of the operation to the static reconfiguration module 523.
  • the static reconstruction module 323 may adjust the rotation speed at a speed according to the received control value.
  • the data is sequentially received from the first sensor, the second sensor, and the third sensor for the control of the servo motor, and operation is required through a first algorithm.
  • a bitstream for this is generated in the master controller 101.
  • the controller 510 may receive the first bitstream from the master controller 101.
  • the first bitstream includes reconfiguration information indicating an FPGA structure for receiving data from the first sensor and performing a calculation through a first predetermined algorithm.
  • the controller 510 controls the first dynamic reconfiguration module 526 to reconstruct the FPGA structure according to the reconfiguration information.
  • the first static reconfiguration module 523 may continue to control the servo motor.
  • the dynamic reconfiguration module 526 receives data from the first sensor according to the FPGA structure, and calculates a control value, which is a value calculated through the first algorithm.
  • the dynamic reconfiguration module 526 sends control values to the static reconfiguration module 523.
  • the static reconfiguration module 523 continues to control the servo motor according to the control value.
  • the controller 510 may receive the second bitstream from the master controller 101.
  • the second bitstream includes reconfiguration information indicating an FPGA structure for receiving data from a second sensor and performing an operation through a first algorithm.
  • the first dynamic reconfiguration module 526 is reconfigured into an FPGA structure for receiving data from the second sensor through the above-described process and performs an operation.
  • the static reconstruction module 523 continues to control the servo motor according to the control value.
  • the controller 510 may receive the third bitstream from the master controller 101.
  • the third bitstream includes reconfiguration information indicating an FPGA structure for receiving data from the third sensor and performing calculation through the first algorithm.
  • the first dynamic reconfiguration module 526 is reconfigured into an FPGA structure for receiving data from the third sensor through the above-described process and performs an operation.
  • the static reconstruction module 523 continues to control the servo motor according to the control value.
  • a function of sequentially receiving data from the first sensor, the second sensor, and the third sensor may be performed.
  • the conventional operation controller when a process of sequentially receiving data from each sensor is to be performed, all modules for receiving data from each sensor should be provided, and accordingly, the circuit size of the operation controller has to be increased.
  • the first slave controller 510 sequentially receives data from each sensor for controlling the servo motor using one dynamic reconfiguration module 526 while maintaining control of the servo motor using the static reconfiguration module 523. It is possible. Therefore, the above-described control system can be implemented in a relatively small size compared to the conventional operation controller.
  • the functions of the above-described static reconfiguration module 523 and the first dynamic reconfiguration module 526 are not limited to the above-described functions, only embodiments. That is, the functions of the static reconstruction module 523 and the first dynamic reconstruction module 526 may vary according to reconstruction information of the bitstream received by the controller 510.
  • the second dynamic reconfiguration module 529 is a module having the same configuration as the first dynamic reconfiguration module 526 and may be reconfigured as in the reconfiguration process of the first dynamic reconfiguration module 526 described above.
  • the controller 510 may reconfigure the FPGA structure of the first dynamic reconfiguration module 526 or the second dynamic reconfiguration module 529 according to the capacity of the reconfiguration information extracted from the bitstream.
  • the controller 510 controls the FPGA of the second dynamic reconfiguration module 529 that is not currently operated when the capacity of the reconfiguration information is greater than or equal to a specified capacity. Reconstruct according to the reconstruction information.
  • the second dynamic reconfiguration module 529 transmits a reconfiguration completion signal indicating that the reconfiguration is completed, to the controller 510.
  • the controller 510 transmits an operation stop request for requesting to stop the operation to the first dynamic reconfiguration module 526 currently in operation.
  • the first dynamic reconfiguration module 526 stops the operation according to the stop operation request.
  • the second dynamic reconfiguration module 529 having the structure of the FPGA reconstructed according to the reconfiguration information performs an operation and transmits the calculation result to the static reconfiguration module 523.
  • the static reconfiguration module 423 may receive a calculation result from the second dynamic reconfiguration module 526 and control the servo motor.
  • control unit 510 has been described as determining that the capacity of the reconstruction information of the bitstream received from the master controller 101 is equal to or larger than a specified value
  • the control unit 510 of the master controller 101 reconfigures according to an implementation method. It may be determined that the capacity of the information is greater than or equal to the designated value, and the information according to the information may be inserted into the header of the reconstruction information.
  • the controller 510 may perform the reconstruction process of the first dynamic reconfiguration module 526 or the second dynamic reconfiguration module 529 by checking the corresponding information in the header of the reconfiguration information.
  • FIG. 6 is a flowchart illustrating a process of controlling a servo motor by a control system.
  • the master controller 101 receives a command from an input device.
  • the master controller 101 In operation 620, the master controller 101 generates a bitstream for controlling the servo motor according to the command received in operation 610. At this time, the master controller 101 generates a bitstream including reconfiguration information indicating the FPGA structure of the slave controller required to control the servo motor according to the command. The master controller 101 transmits the generated bitstream to the first slave controller.
  • the first slave controller 102 extracts reconfiguration information from the received bitstream.
  • the first slave controller may extract the reconfiguration information and then transmit the bitstream to the second slave controller 103.
  • the second slave controller 103 receiving the bitstream may perform the same process as the operation of the first slave controller 102 after step 630.
  • the first slave controller 102 reconstructs the structure of the reconstruction unit, which is an FPGA module, according to the reconfiguration information. At this time, when the first slave controller 102 reconfigures the first dynamic reconfiguration module 526 which is currently controlling the servo motor among the plurality of dynamic reconfiguration modules according to the reconfiguration information, the first slave controller 102 performs the servo motor. If it is necessary to stop the control of the, to reconfigure the configuration of the second dynamic reconfiguration module 529. When the reconfiguration of the second dynamic reconfiguration module 529 is completed, the first slave controller 102 stops the operation of the first dynamic reconfiguration module 526 and replaces the second dynamic reconfiguration module 529 and the static reconfiguration module 523. Servo motor can be controlled.
  • the first slave controller 102 may independently perform reconfiguration of the static reconfiguration module 523, the first dynamic reconfiguration module 526, and the second dynamic reconfiguration module 529 according to the reconfiguration information. That is, when the first slave controller 102 shows only the structure of the first dynamic reconfiguration module 526 or the second dynamic reconfiguration module 529 in the reconfiguration information, the static reconfiguration module 523 controls the servo motor. During the operation, the first dynamic reconfiguration module 526 or the second dynamic reconfiguration module 529 may be reconfigured.
  • the first slave controller 102 controls the operation of the servo motor using the reconstruction unit reconfigured in operation 640.
  • control system has been described as controlling the servo motor, it is apparent that the reconfiguration information can be configured to be suitable for other devices to control devices other than the servo motor.
  • control system and method thereof have the effect of flexibly controlling various devices by reconfiguring the gate array structure according to a user input.
  • control system and method according to an embodiment of the present invention can reduce the size of the control device by reconfiguring the structure of the gate array and controlling the device using the reconstructed gate array.

Landscapes

  • Engineering & Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Automation & Control Theory (AREA)
  • Programmable Controllers (AREA)
  • Advance Control (AREA)
  • Logic Circuits (AREA)
  • Control Of Multiple Motors (AREA)
PCT/KR2010/007795 2009-11-11 2010-11-05 동작 중 재구성이 가능한 제어 시스템 및 그 방법 WO2012053687A1 (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
DE112010005955T DE112010005955T5 (de) 2010-10-22 2010-11-05 Steuerungssystem das während des Betriebs rekonfigurierbar ist, und Verfahren dafür
JP2013534789A JP5646764B2 (ja) 2010-10-22 2010-11-05 動作中に再構成可能な制御システム及びその方法
US13/880,700 US10095201B2 (en) 2009-11-11 2010-11-05 Reconfigurable control system for controlling a target apparatus, and method for reconfiguration during operation of the control system
CN201080069761.2A CN103262405B (zh) 2010-10-22 2010-11-05 可在操作中重构的控制系统以及用于其的方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2010-0103627 2010-10-22
KR1020100103627A KR101259133B1 (ko) 2009-11-11 2010-10-22 동작 중 재구성이 가능한 제어 시스템 및 그 방법

Publications (1)

Publication Number Publication Date
WO2012053687A1 true WO2012053687A1 (ko) 2012-04-26

Family

ID=45975984

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2010/007795 WO2012053687A1 (ko) 2009-11-11 2010-11-05 동작 중 재구성이 가능한 제어 시스템 및 그 방법

Country Status (4)

Country Link
JP (1) JP5646764B2 (de)
CN (1) CN103262405B (de)
DE (1) DE112010005955T5 (de)
WO (1) WO2012053687A1 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3118747B1 (de) * 2014-04-03 2018-08-22 Huawei Technologies Co., Ltd. Feldprogrammierbare gate-anordnung und kommunikationsverfahren
JP2017069777A (ja) * 2015-09-30 2017-04-06 株式会社日立製作所 通信処理装置、通信方法および通信システム
KR101873380B1 (ko) * 2015-12-22 2018-07-02 주식회사 씨드앤 적외선 학습 기반의 온습도 조절 제어 방법 및 이를 운용하는 장치
CN106227037B (zh) * 2016-07-29 2017-11-07 宁波工程学院 一种基于fpga的类人机器人动作规划参数优化方法
US10338135B2 (en) 2016-09-28 2019-07-02 Amazon Technologies, Inc. Extracting debug information from FPGAs in multi-tenant environments
US11099894B2 (en) 2016-09-28 2021-08-24 Amazon Technologies, Inc. Intermediate host integrated circuit between virtual machine instance and customer programmable logic
US10282330B2 (en) 2016-09-29 2019-05-07 Amazon Technologies, Inc. Configurable logic platform with multiple reconfigurable regions
US10162921B2 (en) 2016-09-29 2018-12-25 Amazon Technologies, Inc. Logic repository service
US10250572B2 (en) 2016-09-29 2019-04-02 Amazon Technologies, Inc. Logic repository service using encrypted configuration data
US10642492B2 (en) 2016-09-30 2020-05-05 Amazon Technologies, Inc. Controlling access to previously-stored logic in a reconfigurable logic device
US11115293B2 (en) 2016-11-17 2021-09-07 Amazon Technologies, Inc. Networked programmable logic service provider
JP6726648B2 (ja) * 2017-08-28 2020-07-22 日立オートモティブシステムズ株式会社 電子制御装置、回路の再構成方法
CN109079776A (zh) * 2018-07-26 2018-12-25 福州大学 一种工业机器人控制算法动态重构的方法
CN109918321B (zh) * 2019-02-25 2021-01-05 浙江中控研究院有限公司 一种基于PCIe总线的在线重构方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09298897A (ja) * 1996-04-26 1997-11-18 Sony Corp モータドライバ装置
JP2001331222A (ja) * 2000-03-13 2001-11-30 Sumitomo Heavy Ind Ltd 多軸制御システム
KR200409311Y1 (ko) * 2005-11-18 2006-02-24 엘지노텔 주식회사 통신 시스템에서 ｆｐｇａ 다운로딩 장치
JP2007014092A (ja) * 2005-06-29 2007-01-18 Digital Magic Kk モータ制御システム
KR100762366B1 (ko) * 2005-12-30 2007-10-01 삼성중공업 주식회사 Ｆｐｇａ 소자를 이용한 로봇 제어 시스템
KR100827787B1 (ko) * 2007-07-06 2008-05-07 한국전력공사 송전선 애자 청소 및 점검용 로봇 원격 제어 시스템
JP2009278858A (ja) * 2008-04-15 2009-11-26 Yaskawa Electric Corp サーボ制御装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3832557B2 (ja) * 2000-05-02 2006-10-11 富士ゼロックス株式会社 プログラマブル論理回路への回路の再構成方法および情報処理システム
JP2001322078A (ja) * 2000-05-15 2001-11-20 Sanyo Electric Co Ltd ロボットの制御装置
JP2005275938A (ja) * 2004-03-25 2005-10-06 Toshiba Corp コントローラシステムおよびメカトロニクス機器用コントローラ
CN100462985C (zh) * 2006-08-25 2009-02-18 西安交通大学 一种现场可编程门阵列的快速配置方法
KR100945884B1 (ko) * 2007-11-14 2010-03-05 삼성중공업 주식회사 내장형 로봇 제어 시스템
JP5007838B2 (ja) * 2009-03-05 2012-08-22 富士ゼロックス株式会社 情報処理装置および情報処理プログラム
JP5355152B2 (ja) * 2009-03-10 2013-11-27 三菱電機株式会社 動的再構成装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09298897A (ja) * 1996-04-26 1997-11-18 Sony Corp モータドライバ装置
JP2001331222A (ja) * 2000-03-13 2001-11-30 Sumitomo Heavy Ind Ltd 多軸制御システム
JP2007014092A (ja) * 2005-06-29 2007-01-18 Digital Magic Kk モータ制御システム
KR200409311Y1 (ko) * 2005-11-18 2006-02-24 엘지노텔 주식회사 통신 시스템에서 ｆｐｇａ 다운로딩 장치
KR100762366B1 (ko) * 2005-12-30 2007-10-01 삼성중공업 주식회사 Ｆｐｇａ 소자를 이용한 로봇 제어 시스템
KR100827787B1 (ko) * 2007-07-06 2008-05-07 한국전력공사 송전선 애자 청소 및 점검용 로봇 원격 제어 시스템
JP2009278858A (ja) * 2008-04-15 2009-11-26 Yaskawa Electric Corp サーボ制御装置

Also Published As

Publication number Publication date
DE112010005955T5 (de) 2013-08-01
CN103262405A (zh) 2013-08-21
JP5646764B2 (ja) 2014-12-24
JP2014500644A (ja) 2014-01-09
CN103262405B (zh) 2016-03-23

Similar Documents

Publication Publication Date Title
WO2012053687A1 (ko) 동작 중 재구성이 가능한 제어 시스템 및 그 방법
KR101259133B1 (ko) 동작 중 재구성이 가능한 제어 시스템 및 그 방법
US20130179622A1 (en) System and method for transmitting and receiving data using an industrial expansion bus
JPH07262128A (ja) 直列のマスター・スレーブ装置において機能ユニットを構成する方法と装置
WO2010094216A1 (zh) 主从网络设备配置方法、装置和系统
GB2364199A (en) Standby redundancy in IMA
JP2008250997A (ja) センサー用シリアル通信装置およびシリアル通信方法
WO2016141613A1 (zh) 一种芯片引脚复用的方法及系统
CN104995888A (zh) 电子设备和用于控制电子设备的方法
WO2014003510A1 (ko) 토폴로지를 이용하여 데이터를 공유하는 장치 및 방법
US20060206626A1 (en) Instrument and communications controller for instrument
WO2014117329A1 (zh) 反向供电线路测试系统及设备
JP2018525753A5 (de)
WO2019132430A1 (ko) 이중화 보드에서 마스터/슬레이브 설정방법 및 그 보드
US6088810A (en) Apparatus for synchronized data interchange between locally dedicated sources
EP0416235B1 (de) Methode zur Datenübertragung für ringartiges Netzwerk mit tragbaren Nebenstationen, die addressierbare und permanent mit dem Netzwerk verbundene Anschlüsse haben
WO2024117278A1 (ko) 다수의 센서 데이터를 자동 수집하여 이더넷 전송이 가능하게 하는 게이트웨이 장비 및 그 방법
JP2544329B2 (ja) 集線装置の診断および障害切離し方法
WO2020091256A1 (ko) 이중화 보드를 구비한 제어기 시스템 및 그 이중화 보드의 마스터/슬레이브 설정방법
WO2023085465A1 (ko) 고속통신기반의 전력변환장치용 제어장치
WO2021187887A1 (ko) 카메라 동기화 장치 및 그 동기화 처리 방법
WO2023101209A1 (ko) 모듈 확장 장치를 포함하는 스마트 배전반
WO2023058867A1 (ko) 블루투스 연결 제어 장치 및 방법
WO2013085121A1 (ko) 다수의 버스를 이용하는 논리연산 제어장치
JP2671866B2 (ja) 時分割多重化装置ネットワークにおけるパス経路探索方法及びそれに適用される時分割多重化装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 201080069761.2

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 10858695

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2013534789

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 13880700

Country of ref document: US

WWE Wipo information: entry into national phase

Ref document number: 1120100059551

Country of ref document: DE

Ref document number: 112010005955

Country of ref document: DE

122 Ep: pct application non-entry in european phase

Ref document number: 10858695

Country of ref document: EP

Kind code of ref document: A1