WO2013015569A2 - 시뮬레이션 장치 및 그의 시뮬레이션 방법 - Google Patents
시뮬레이션 장치 및 그의 시뮬레이션 방법 Download PDFInfo
- Publication number
- WO2013015569A2 WO2013015569A2 PCT/KR2012/005799 KR2012005799W WO2013015569A2 WO 2013015569 A2 WO2013015569 A2 WO 2013015569A2 KR 2012005799 W KR2012005799 W KR 2012005799W WO 2013015569 A2 WO2013015569 A2 WO 2013015569A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- simulation
- block
- communication
- calculation
- node
- Prior art date
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3466—Performance evaluation by tracing or monitoring
- G06F11/3495—Performance evaluation by tracing or monitoring for systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3457—Performance evaluation by simulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/20—Design optimisation, verification or simulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/20—Design optimisation, verification or simulation
- G06F30/25—Design optimisation, verification or simulation using particle-based methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5061—Partitioning or combining of resources
- G06F9/5066—Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3409—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
- G06F11/3419—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment by assessing time
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2209/00—Indexing scheme relating to G06F9/00
- G06F2209/50—Indexing scheme relating to G06F9/50
- G06F2209/5017—Task decomposition
Definitions
- the present invention relates to a simulation method and apparatus for quickly and accurately measuring and predicting system performance in advance. More specifically, the present invention provides a parallel simulation method for extracting computational and communication operations that are dependent on each other, grouping them into a plurality of groups, and processing each group in parallel, and between the plurality of nodes. It introduces a virtual shadow node and provides a distributed simulation method and apparatus for each that pre-processes according to the type of address area of a task requested by an arbitrary node.
- Simulation for structure and performance analysis is essential for the production of smartphones, TVs, home appliances, etc. Simulation allows you to configure an optimized system without sacrificing performance without sacrificing performance. In other words, simulation techniques for measuring and predicting system performance in advance are being used to analyze and evaluate the system and are of great importance.
- the present invention has been made to solve the above problems, and an object thereof is to provide a simulation method and apparatus for quickly and accurately measuring and predicting system performance in advance.
- the present invention provides a parallel simulation method and apparatus for extracting computational and communication operations that are dependent on each other, grouping them into a plurality of groups, and processing each group in parallel. It is done.
- the present invention also provides a distributed simulation method and apparatus for introducing a virtual shadow node between a plurality of nodes and pre-processing according to the type of address area of a task requested by an arbitrary node. It is a second object to do.
- a method of performing a simulation using a plurality of blocks of the present invention includes a computational calculation for performing block-specific functions and a data exchange between different blocks.
- the step of dividing into a communication operation (communication) the grouping step of grouping the interdependent calculation operation and the communication operation, and the operation included in each group according to whether or not to solve the dependency between the calculation operation and the communication operation using the block It characterized in that it comprises a simulation performing step to perform.
- the apparatus for performing a simulation using a plurality of blocks of the present invention includes a structure storage unit for storing at least one group constituting the simulation, an execution unit including a plurality of blocks for performing the simulation and the simulation Partitioning into computational computations that perform block-specific functions and communications computations that perform data exchange between different blocks, grouping interdependent computational and communications operations together, and computing the computational and communications operations And a control unit for controlling to perform an operation included in each group using the block according to whether or not the dependency between the two is resolved.
- a method of performing a simulation in a distributed system in which at least two or more nodes including a plurality of blocks of the present invention are interconnected may include a setting step of setting a shadow block to each node, wherein the shadow block is random. And a receiving step of receiving any operation request transmitted from a node of the node to another node, and the shadow block comprises a preprocessing step of preprocessing the requested operation.
- At least two nodes comprising a plurality of blocks, each of the nodes comprising a shadow block receiving any operation request sent from one node to another node and preprocessing the requested operation. It features.
- the system performance can be accurately evaluated at the same time without sacrificing the simulation speed. Accordingly, the simulation method of the present invention can be applied to SoC (System on Chip), a terminal, and other embedded devices to produce optimized products. In addition, rapid and accurate simulation can be used for various analysis of various situations, contributing to improved product performance.
- SoC System on Chip
- FIG. 1 shows a relationship between system simulation variables (accuracy, simulation speed, parallel processing) according to the prior art and embodiments of the present invention.
- FIG. 2 illustrates an example of a parallel processing method and a parallel system for processing a simulation in parallel, and a problem thereof.
- 3 is a diagram illustrating an example of configuring a distributed system by clustering several nodes.
- FIG. 4 shows a system block diagram according to an embodiment of the present invention for driving a simulation.
- FIG. 5 is a flow chart illustrating a process of grouping simulations according to dependencies to perform parallel simulations in accordance with a first embodiment of the present invention.
- FIG. 6 is a diagram illustrating a process of grouping according to dependencies when performing a simulation through a diagram of a calculation operation and a communication operation.
- FIG. 7 is a flowchart illustrating a process of processing a computation operation and a communication operation included in each simulation group in parallel, according to the first embodiment of the present invention.
- FIG. 8 is a diagram illustrating a process of parallel processing arithmetic operations and communication operations included in a plurality of groups included in a simulation through a diagram of arithmetic operations and communication operations.
- FIG. 9 is a block diagram showing an internal structure of a simulation apparatus according to the first embodiment of the present invention.
- FIG. 10 is a diagram showing a process in which a calculation operation and a communication operation are executed sequentially when a simulation is performed according to the first embodiment of the present invention.
- FIG. 11 is a diagram illustrating a simulation optimization method in a distributed system according to a second embodiment of the present invention.
- FIG. 12 is a flowchart showing a simulation operation procedure according to the second embodiment of the present invention.
- FIG. 13 illustrates a concept of performing communication operations between nodes using shadow blocks.
- FIG. 14 is a graph showing the results of improved simulation performance in accordance with an embodiment of the present invention.
- a device for performing a simulation may be referred to as a host, and the host may include a plurality of blocks for performing an arbitrary operation or a predetermined operation.
- the block may be replaced with a term such as master or slave.
- a simulation is performed using a computer or the like as a host.
- FIG. 1 is a diagram showing the relationship between system simulation variables (accuracy, simulation speed, parallel processing) according to the prior art and embodiments of the present invention.
- Embodiments of the present invention propose a method that can perform a simulation quickly without sacrificing simulation accuracy through parallel processing.
- FIG. 2 is a diagram illustrating an example of a parallel processing method and a parallel system for processing a simulation in parallel, and a problem thereof.
- the master and the processing block as shown in FIG.
- the master and the processing block as shown in FIG.
- the master or the slave should wait for arbitrary task processing. For example, six computational computations in FIG. 2 cannot be performed before communication communication of b is performed, so that the slave does not perform any operation until communication of b is performed from the master. You must wait.
- 3 is a diagram illustrating an example of configuring a distributed system by clustering several nodes.
- the simulation speed is considerably slowed down due to the physical link characteristics connecting the first node and the second node. Can be.
- the present invention proposes a method for solving the problems that occur when performing the simulation in the parallel system and distributed system.
- Each block (core, memory, bus, etc.) of an embedded system may be classified into computational computation and communication computation.
- a calculation operation means performing a unique function of a specific block
- a communication operation means exchanging data between different blocks. For example, in the case of a memory, receiving an address from the outside is a communication operation, and executing an internal logic to transmit data of the address to the outside is a calculation operation.
- the first embodiment describes a simulation optimization method in a parallel system using multiple cores.
- the second embodiment a simulation optimization method in a distributed system is described.
- an embodiment of the present invention may be performed through the simulation system configuration diagram shown in FIG. 4.
- a host performing a simulation is a distributed system in which at least two nodes such as a first node and a second node are connected by a link.
- the link may comprise a wire link and / or a wireless link.
- each node has a parallel computing environment consisting of at least two cores, that is, multi-cores. And arbitrary blocks located in each node may be mapped to the physical functional blocks constituting the host.
- Each core and node has a platform that simulates it, and the platform is mapped to each core.
- Each block in the platform communicates with each other and the simulation proceeds.
- the simulation in the same node is referred to as parallel simulation, and the simulation between different nodes will be referred to as distributed simulation.
- a parallel simulation method that includes the steps of independently and simultaneously processing communication operations.
- FIG. 5 is a flowchart illustrating a process of grouping simulations according to dependencies in order to perform parallel simulations according to the first embodiment of the present invention.
- FIG. 6 is a diagram illustrating a process of grouping according to dependencies in a simulation, through a calculation operation and a communication operation.
- the upper line means a calculation operation performed by a master
- the lower line means a calculation operation performed by a slave
- the line orthogonal to the upper line and the lower line means a communication operation occurring between the master and the slave.
- the simulation apparatus is assigned an arbitrary simulation operation.
- the simulation apparatus extracts a communication operation to be exchanged between the master and the slave in the simulation operation. This is the operation shown in a, b, c and the like in FIG. 6A. And the simulation apparatus arranges the extracted communication operation in time order according to the dependency. In this case, a dependency relationship is established between calculation operations arranged before and after each communication operation.
- the simulation apparatus extracts a calculation operation of a master and a slave related to the communication operation. This is an operation shown in FIG. 6B as 1, 2, 3, and the like.
- a communication operation can be thought of as performing a unique function of a master or slave block. For example, if the master is the core, processing is the processing operation. If the slave is the memory, it is the calculation operation that executes the internal logic to transfer the data of the address to the outside. have.
- the simulation apparatus divides the calculation operation into detailed units.
- the simulation apparatus groups the calculation operations and the communication operations that are dependent on each other. There is a dependency between communication operations and computational operations within the same group, and they are linked. On the other hand, operations between different groups are independent of each other. That is, there is no dependency.
- FIG. 6C illustrates an example in which the simulation operation is grouped into a first group 610 and a second group 620. More specifically, calculation operation 2 of FIG. 6C is dependent on operations 1/5 and a communication operation. In other words, the second calculation operation cannot be performed until the first and fifth calculation operations and the a communication operation are processed.
- the first calculation operation included in the first group 610 and the third calculation operation included in the second group 620 are independent. In other words, at any point before the first calculation operation is processed, the third calculation operation may be performed, and the third calculation operation is performed when the execution of the first calculation operation is interrupted, and then again the calculation operation is performed. It may be performed.
- Hardware block characteristics have a number of parallel processing elements that can be divided into groups. In the first embodiment of the present invention, each of these groups is processed in parallel.
- FIG. 7 is a flowchart illustrating a process of processing a computation operation and a communication operation included in each simulation group in parallel, according to the first embodiment of the present invention.
- FIG. 8 is a diagram illustrating a process of processing arithmetic operations and communication operations included in a plurality of groups included in the simulation in parallel through a diagram of arithmetic operations and communication operations.
- the master and the slave select the calculation operation to be executed at this point in time according to two criteria of determining whether the communication operation is close and whether the communication dependency is resolved.
- the master and the slave execute the corresponding communication operation when they reach the point where the communication operation should be performed.
- the master and the slave execute the corresponding calculation operation first.
- the master and the slave repeat this process until the assigned simulation is completed.
- the simulation device selects the calculation operation to be performed currently based on two criteria. To this end, the simulation apparatus extracts the calculation operations closest to the next communication operation among the calculation operations included in the first group 610 and the second group 620 in operation S710. Referring to FIG. 8A, the first and third calculation operations are extracted from the master and the fifth and eight calculation operations are extracted from the slave.
- the simulation apparatus determines whether there is an operation that is dependent on a communication operation among the extracted calculation operations and in which the communication operation is not yet performed.
- the first and third calculation operations of the master are independent of the communication operations. Accordingly, the third calculation operation closest to the next communication operation is selected as the calculation operation to be performed at the master.
- the eighth calculation operation in the slave can be executed only when the d communication operation is performed. That is, calculation operation 8 is dependent on the d communication operation, and the d communication operation has not been performed yet.
- operation 5 of the slave is independent of communication operation. Accordingly, the operation 5 is selected as the calculation operation to be performed at the slave.
- step S730 the simulation apparatus determines whether there is a calculation operation that is pending because no communication operation is performed. If so, the simulation apparatus proceeds to step S780 to select and perform the corresponding calculation operation.
- step S750 determines whether to perform a communication operation during the calculation operation. This means that the time at which the d communication operation is performed in FIG. 6C has been reached. In this case, the simulation apparatus proceeds to step S760 to perform a corresponding communication operation, which is illustrated in FIG. 8B. The simulation apparatus proceeds to step S770 and determines whether all calculation and communication operations have been performed, and returns to step S710 when it is not performed.
- the simulation apparatus returning to step S710 selects a target to perform a calculation operation through the same principle as the above principle through steps S710 and S720. More specifically, in the case of the master, the first calculation operation is the closest to the communication operation. Accordingly, the first calculation operation is selected as the calculation operation to be performed at the master. On the other hand, in the slave, calculation operation 5 is the closest to the communication operation. Accordingly, the fifth calculation operation is selected as the calculation operation to be performed at the slave. The figure in which the calculation operations to be performed respectively in the master and the slave are selected is shown in FIG. 8C.
- the simulation apparatus selects a target to perform a calculation operation again through steps S710 and S720.
- the calculation operation 3 is selected as the calculation operation to be currently performed.
- calculation operation 5 is selected as the calculation operation to be performed currently.
- FIGS. 8G and 8H The same principle applies to FIGS. 8G and 8H, and the above operation sequence is repeatedly performed until the currently assigned simulation is completed.
- the master and the slave performing the simulation perform the simulation by minimizing the wait time, so that a faster and more accurate simulation performance can be expected.
- the simulation apparatus may include a structure storage unit 910, an execution unit 920, and a control unit 930.
- the structure storage unit 910 stores at least one group constituting the simulation.
- the execution unit 920 may include a plurality of blocks for performing a simulation.
- the block may include a core, a memory, a bus, and the like.
- the controller 930 divides the simulation into a computational computation that performs a block-specific function and a communication computation that performs data exchange between different blocks. In addition, the controller 930 groups mutually dependent calculation operations and communication operations. In addition, the controller 930 controls to perform an operation included in each group using the block according to whether or not the dependency between the calculation operation and the communication operation is resolved.
- the controller 930 selects a random block and performs a calculation operation in each group that the selected block should perform first when the simulation is performed.
- the controller 930 selects a calculation operation that is not dependent on the communication operation and is closest to the communication operation to be generated later, and controls the selected calculation operation to be performed by the execution unit 920.
- the controller 930 controls to perform the communication operation when the communication operation execution time point is reached during the calculation operation.
- FIG. 10 is a diagram illustrating a process in which arithmetic operations and communication operations are executed sequentially when a simulation is performed according to the first embodiment of the present invention.
- the conventional parallel simulation method has a large wait time, but according to an embodiment of the present invention, the waiting time is reduced (none) to speed up the simulation. It can be seen that it can be processed.
- the second embodiment proposes a simulation optimization method applicable to a distributed system in which a plurality of nodes having at least two functional blocks (core, memory, bus, etc.) are clustered.
- the second embodiment of the present invention proposes a method for rapidly processing communication operations by introducing a virtual block called a shadow block.
- FIG. 11 is a diagram illustrating a simulation optimization method in a distributed system according to a second embodiment of the present invention.
- the distributed system in the second embodiment includes a first node 1110 having a first shadow block 1111 and a second node 1120 having a second shadow block 1121. ).
- the first shadow block 1111 located in the first node 1110 operates.
- the first shadow block 1111 preprocesses and post-adjusts the operation requested by the A block of the first node 1110. This will be described in detail below.
- the shadow block introduced in the embodiment of the present invention includes at least one address area.
- Each address area is classified according to a function to be performed, and according to an example of the present invention, a memory address area, an active device address area, and a passive device area area are described. Can be distinguished.
- the memory address area has general memory characteristics, that is, read / write characteristics, the active device address region has a characteristic in which the behavior of the corresponding device is not predetermined, and the passive device address region has a corresponding device.
- the behavior of has a predetermined characteristic.
- the A block of the first node When the A block of the first node requests a specific operation to the D block of the second node, if the operation is related to memory input / output, the A block requests a corresponding command to the memory address area of the first shadow block. On the other hand, when the A block of the first node requests a processing operation for the E block of the second node, the A block requests a corresponding command in the passive device address area of the first shadow block.
- Each shadow block set in the first node and the second node performs the following operation. If the operation requested by the shadow block corresponds to the memory address area (that is, the operation is requested for memory), then the shadow block will service it if it has the address for read, whereas write ) Is first written to the shadow block, and its contents are subsequently sent to the other node.
- the shadow block bypasses the request when the requested operation corresponds to the active device address area (that is, when the operation is requested for the active device). If the shadow block requests the operation corresponding to the passive device address range (that is, the operation is requested for the passive device), the shadow block provides a service according to a behavior model and delivers it to the corresponding block of the counterpart node. . In other words, the shadow block models the behavior of the passive device to perform a corresponding function.
- the D block when the A block instructs to output a specific string in the D block, the D block outputs the string and then sends a confirmation signal (ack) indicating that the string is output to the A block.
- ack confirmation signal
- the fact that the shadow block models the operation of the D block means that the original D block has an acknowledgment (ack) to send to the A block, and that the acknowledgment signal (A) is received when the shadow block receives a command for string output from the A block. ) Means direct transmission.
- the shadow block is provided by modeling a signal to be fed back after an arbitrary block performs a specific operation.
- the shadow block preferentially transmits a feedback signal corresponding to a block that has transmitted a random command.
- motion modeling is defined as motion modeling.
- the first shadow block 1111 when the A block requests communication from the D block, the first shadow block 1111 performs d communication first, and this communication is repeated three times (AdAdAd). Thereafter, the first shadow block 1111 performs actual communication with the D block located in the second node 1120 to receive the communication result D (DDD). The first shadow block 1111 compares the communication d preprocessed with the received D, and adjusts a stored value in the first shadow block 1111 using the comparison result.
- DDD communication result D
- FIG. 12 is a flowchart showing a simulation operation procedure according to the second embodiment of the present invention.
- FIG. 13 is a diagram illustrating the concept of performing a communication operation between nodes using a shadow block.
- the simulation apparatus generates a shadow block at each node in step S1205.
- the shadow block is defined through at least one address area as described above.
- the simulation apparatus determines whether all simulations have been processed. If all simulations have not been processed, the simulation apparatus proceeds to step S1215, in which case the shadow block receives a specific command execution request from any block included in the node to which the simulation block belongs.
- the specific command is stored in the address area corresponding to the type of device targeted for the command. For example, if the type of device that is the target of the command is a memory, the command is stored in the memory address area.
- the shadow block proceeds to step S1220 to determine whether the address area receiving the command is an active device address area. In the case of the active device address area, the shadow block proceeds to step S1250 to bypass the corresponding command (transaction, transaction).
- step S1230 determines whether the address area receiving the command is a memory address area. In the case of the memory address area, the shadow block proceeds to step S1235 to pre-process using caching data internally included in the shadow block. In this case, when the command is read, the data provided is transmitted. In the case of write, the data is first stored, and a confirmation signal ack is transmitted. On the other hand, if the command is a read first generated, since there is no data included in the shadow block in this case, it is necessary to wait until data is received from the block having the data. The shadow block stores the data when it is received and uses the preprocessing process.
- the shadow block After performing the preprocessing, the shadow block proceeds to step S1240 and delivers the corresponding transaction to the block that was the original request target.
- the shadow block receives the actual processing (post-processing) result from the block that was originally the request target, and checks an error between the timing of the preprocessed service and the timing of the postprocessed service.
- the error between the timings refers to a difference between timings (eg, number of clocks) used to perform a preprocessed service and timings used to perform a postprocessed service. That is, there may be a difference in the number of clocks required to perform each service.
- the shadow block stores timing information of the post-processed service and uses the preprocessing in the next step.
- the content of the service preprocessed by the shadow block and the content of the postprocessed service are the same, and only an error about timing occurs.
- step S1230 determines whether the address area receiving the command is a memory address area.
- the shadow block proceeds to step S1250 and preprocesses the device with a predetermined operation (in this case, an action returned to the block requesting the command).
- a predetermined operation in this case, an action returned to the block requesting the command.
- the process is illustrated in Figures 13b and 13c. That is, when the shadow block receives a specific command request (4, 6, 8), it preprocesses (7, 9) and delivers the command (10) to the corresponding block of the target node. The shadow block receives timing information 11 from the target node and updates the timing information when there is an error with the previously stored timing information.
- FIG. 14 is a graph showing a result of improved simulation performance in accordance with an embodiment of the present invention.
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- Quality & Reliability (AREA)
- Management, Administration, Business Operations System, And Electronic Commerce (AREA)
- Debugging And Monitoring (AREA)
- Monitoring And Testing Of Transmission In General (AREA)
- Mobile Radio Communication Systems (AREA)
Abstract
Description
Claims (20)
- 복수 개의 블록을 이용하여 시뮬레이션을 수행하는 방법에 있어서,상기 시뮬레이션을 블록 고유한 기능을 수행하는 계산 연산(computation)과, 서로 다른 블록 사이에서 데이터 교환을 수행하는 통신 연산(communication)으로 분할하는 단계;상호 의존적인 계산 연산과 통신 연산끼리 그룹화하는 그룹화 단계; 및상기 계산 연산과 통신 연산 사이의 의존도 해결 여부에 따라 각각의 그룹에 포함된 연산을 상기 블록을 이용하여 수행하는 시뮬레이션 수행 단계를 포함하는 것을 특징으로 하는 시뮬레이션 수행 방법.
- 제1항에 있어서, 상기 시뮬레이션 수행 단계는,임의의 블록을 선택하는 단계;상기 선택된 블록이 가장 먼저 수행해야 하는 계산 연산을 각각의 그룹에서 추출하는 단계;상기 추출된 계산 연산 중, 통신 연산에 의존적이지 않음과 동시에 차후 발생할 통신 연산에 가장 근접한 계산 연산을 선택하는 단계; 및상기 선택된 계산 연산을 수행하는 단계를 더 포함하는 것을 특징으로 하는 시뮬레이션 수행 방법.
- 제2항에 있어서, 상기 시뮬레이션 수행 단계는,상기 계산 연산 수행 도중 통신 연산 수행 시점 도달 시, 상기 통신 연산을 수행하는 단계를 더 포함하는 것을 특징으로 하는 시뮬레이션 수행 방법.
- 제1항에 있어서,동일한 그룹에 포함된 통신 연산 및 계산 연산을 서로 의존적인 것을 특징으로 하는 시뮬레이션 수행 방법.
- 복수 개의 블록을 이용하여 시뮬레이션을 수행하는 장치에 있어서,상기 시뮬레이션을 구성하는 적어도 하나 이상의 그룹을 저장하는 구조 저장부;상기 시뮬레이션을 수행하는 복수 개의 블록을 포함하는 실행부; 및상기 시뮬레이션을 블록 고유한 기능을 수행하는 계산 연산(computation)과 서로 다른 블록 사이에서 데이터 교환을 수행하는 통신 연산(communication)으로 분할하고, 상호 의존적인 계산 연산과 통신 연산끼리 그룹화하며, 상기 계산 연산과 통신 연산 사이의 의존도 해결 여부에 따라 각각의 그룹에 포함된 연산을 상기 블록을 이용하여 수행하도록 제어하는 제어부를 포함하는 것을 특징으로 하는 시뮬레이션 수행 장치.
- 제5항에 있어서, 상기 제어부는,상기 연산 수행 시,임의의 블록을 선택하고, 상기 선택된 블록이 가장 먼저 수행해야 하는 계산 연산을 각각의 그룹에서 추출하며, 상기 추출된 계산 연산 중 통신 연산에 의존적이지 않음과 동시에 차후 발생할 통신 연산에 가장 근접한 계산 연산을 선택하고, 상기 선택된 계산 연산을 수행하도록 제어하는 것을 특징으로 하는 시뮬레이션 수행 장치.
- 제6항에 있어서, 상기 제어부는,상기 계산 연산 수행 도중 통신 연산 수행 시점 도달 시, 상기 통신 연산을 수행하도록 제어하는 것을 특징으로 하는 시뮬레이션 수행 장치.
- 제5항에 있어서,동일한 그룹에 포함된 통신 연산 및 계산 연산을 서로 의존적인 것을 특징으로 하는 시뮬레이션 수행 장치.
- 복수 개의 블록을 포함하는 적어도 두 개 이상의 노드가 상호 연결된 분산 시스템에서의 시뮬레이션 수행 방법에 있어서,상기 각각의 노드에 섀도우 블록(shadow block)을 설정하는 설정 단계;상기 섀도우 블록이, 임의의 노드에서 다른 노드로 전송되는 임의의 연산 요청을 수신하는 수신 단계; 및상기 섀도우 블록이, 상기 요청된 연산을 선처리하는 선처리 단계를 포함하는 것을 특징으로 하는 시뮬레이션 수행 방법.
- 제9항에 있어서,상기 선처리 후, 상기 섀도우 블록이 상기 연산 요청을 상기 다른 노드로 전달하는 단계; 및상기 섀도우 블록이 상기 다른 노드로부터 전송되는 처리 결과를 수신하여 업데이트하는 단계를 더 포함하는 것을 특징으로 하는 시뮬레이션 수행 방법.
- 제10항에 있어서, 상기 업데이트 단계는,선처리된 서비스를 수행하는데 소요된 시간과, 후처리된 서비스를 수행하는데 소요된 시간 사이의 타이밍 오차를 업데이트하는 것을 특징으로 하는 시뮬레이션 수행 방법.
- 제10항에 있어서, 상기 선처리 단계는,상기 섀도우 블록이 메모리에 대한 연산 요청을 수신한 경우, 리드 또는 라이트 기능을 수행하는 것을 특징으로 하는 시뮬레이션 수행 방법.
- 제10항에 있어서, 상기 선처리 단계는,상기 섀도우 블록이 능동 디바이스에 대한 연산 요청을 수신한 경우, 상기 연산 요청을 바이패스(by-pass)시키는 것을 특징으로 하는 시뮬레이션 수행 방법.
- 제10항에 있어서, 상기 선처리 단계는,상기 섀도우 블록이 수동 디바이스에 대한 연산 요청을 수신한 경우, 상기 수동 디바이스에 대한 동작 모델에 따라 서비스를 수행하는 것을 특징으로 하는 시뮬레이션 수행 방법.
- 분산 시스템에서 시뮬레이션을 수행하는 시뮬레이션 수행 장치에 있어서,복수 개의 블록을 포함하는 적어도 두 개 이상의 노드들을 포함하며,상기 노드들 각각은,임의의 노드에서 다른 노드로 전송되는 임의의 연산 요청을 수신하고, 상기 요청된 연산을 선처리하는 섀도우 블록을 포함하는 것을 특징으로 하는 시뮬레이션 수행 장치.
- 제15항에 있어서, 상기 섀도우 블록은,상기 선처리 후 상기 연산 요청을 상기 다른 노드로 전달하며, 상기 다른 노드로부터 전송되는 처리 결과를 수신하여 업데이트 하는 것을 특징으로 하는 시뮬레이션 수행 장치.
- 제16항에 있어서, 싱기 섀도우 블록은,선처리된 서비스를 수행하는데 소요된 시간과, 후처리된 서비스를 수행하는데 소요된 시간 사이의 타이밍 오차를 업데이트하는 것을 특징으로 하는 시뮬레이션 수행 장치.
- 제17항에 있어서, 상기 섀도우 블록은,메모리에 대한 연산 요청을 수신한 경우, 리드 또는 라이트 기능을 수행하는 것을 특징으로 하는 시뮬레이션 수행 장치.
- 제17항에 있어서, 상기 섀도우 블록은,능동 디바이스에 대한 연산 요청을 수신한 경우, 상기 연산 요청을 바이패스(by-pass)시키는 것을 특징으로 하는 시뮬레이션 수행 장치.
- 제17항에 있어서, 상기 섀도우 블록은,상기 섀도우 블록이 수동 디바이스에 대한 연산 요청을 수신한 경우, 상기 수동 디바이스에 대한 동작 모델에 따라 서비스를 수행하는 것을 특징으로 하는 시뮬레이션 수행 장치.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014521563A JP6072028B2 (ja) | 2011-07-22 | 2012-07-20 | シミュレーション装置及びそのシミュレーション方法 |
US14/233,610 US10162913B2 (en) | 2011-07-22 | 2012-07-20 | Simulation device and simulation method therefor |
EP12818145.0A EP2735967A4 (en) | 2011-07-22 | 2012-07-20 | SIMULATION DEVICE AND CORRESPONDING SIMULATION METHOD |
CN201280036428.0A CN103748557B (zh) | 2011-07-22 | 2012-07-20 | 仿真设备及其仿真方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020110073219A KR101818760B1 (ko) | 2011-07-22 | 2011-07-22 | 시뮬레이션 장치 및 그의 시뮬레이션 방법 |
KR10-2011-0073219 | 2011-07-22 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2013015569A2 true WO2013015569A2 (ko) | 2013-01-31 |
WO2013015569A3 WO2013015569A3 (ko) | 2013-03-21 |
Family
ID=47601624
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/KR2012/005799 WO2013015569A2 (ko) | 2011-07-22 | 2012-07-20 | 시뮬레이션 장치 및 그의 시뮬레이션 방법 |
Country Status (6)
Country | Link |
---|---|
US (1) | US10162913B2 (ko) |
EP (1) | EP2735967A4 (ko) |
JP (1) | JP6072028B2 (ko) |
KR (1) | KR101818760B1 (ko) |
CN (1) | CN103748557B (ko) |
WO (1) | WO2013015569A2 (ko) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6232470B2 (ja) * | 2015-06-16 | 2017-11-15 | 株式会社日立製作所 | 分散コンピューティング環境でシステムのプロセスの検証を行うための方法 |
US10366359B2 (en) * | 2015-11-18 | 2019-07-30 | Microsoft Technology Licensing, Llc | Automatic extraction and completion of tasks associated with communications |
KR101988482B1 (ko) * | 2017-08-21 | 2019-06-12 | 국방과학연구소 | 전술 데이터 링크 시스템, 전술 데이터 링크 시스템의 데이터 처리 장치 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6948172B1 (en) * | 1993-09-21 | 2005-09-20 | Microsoft Corporation | Preemptive multi-tasking with cooperative groups of tasks |
JP3492105B2 (ja) * | 1996-08-30 | 2004-02-03 | 株式会社東芝 | ハードウェア/ソフトウェア協調シミュレーション装置及びシミュレーション方法 |
US6321363B1 (en) * | 1999-01-11 | 2001-11-20 | Novas Software Inc. | Incremental simulation using previous simulation results and knowledge of changes to simulation model to achieve fast simulation time |
JP2003067439A (ja) | 2001-08-30 | 2003-03-07 | Matsushita Electric Ind Co Ltd | システムシミュレーション方法 |
JP2003233633A (ja) | 2002-02-07 | 2003-08-22 | Sanyo Electric Co Ltd | 集積回路の設計方法 |
JP4667206B2 (ja) | 2005-10-31 | 2011-04-06 | 富士通セミコンダクター株式会社 | マルチコアモデルシミュレーションプログラム、該プログラムを記録した記録媒体、マルチコアモデルシミュレータ、およびマルチコアモデルシミュレーション方法 |
JP4806362B2 (ja) | 2007-02-14 | 2011-11-02 | 富士通株式会社 | 並列処理制御プログラム、並列処理制御システムおよび並列処理制御方法 |
CN102089752B (zh) | 2008-07-10 | 2014-05-07 | 洛克泰克科技有限公司 | 依赖性问题的有效率的并行计算 |
EP2282264A1 (en) | 2009-07-24 | 2011-02-09 | ProximusDA GmbH | Scheduling and communication in computing systems |
US9354944B2 (en) | 2009-07-27 | 2016-05-31 | Advanced Micro Devices, Inc. | Mapping processing logic having data-parallel threads across processors |
US8056080B2 (en) | 2009-08-31 | 2011-11-08 | International Business Machines Corporation | Multi-core/thread work-group computation scheduler |
US8453102B1 (en) * | 2010-03-12 | 2013-05-28 | Worldwide Pro Ltd. | Hierarchical variation analysis of integrated circuits |
CN101860752B (zh) | 2010-05-07 | 2012-02-01 | 浙江大学 | 一种针对嵌入式多核系统的视频编码流水化并行方法 |
US9317637B2 (en) * | 2011-01-14 | 2016-04-19 | International Business Machines Corporation | Distributed hardware device simulation |
-
2011
- 2011-07-22 KR KR1020110073219A patent/KR101818760B1/ko active IP Right Grant
-
2012
- 2012-07-20 JP JP2014521563A patent/JP6072028B2/ja not_active Expired - Fee Related
- 2012-07-20 CN CN201280036428.0A patent/CN103748557B/zh not_active Expired - Fee Related
- 2012-07-20 EP EP12818145.0A patent/EP2735967A4/en not_active Ceased
- 2012-07-20 US US14/233,610 patent/US10162913B2/en not_active Expired - Fee Related
- 2012-07-20 WO PCT/KR2012/005799 patent/WO2013015569A2/ko active Application Filing
Non-Patent Citations (1)
Title |
---|
See references of EP2735967A4 * |
Also Published As
Publication number | Publication date |
---|---|
CN103748557B (zh) | 2017-05-31 |
WO2013015569A3 (ko) | 2013-03-21 |
JP6072028B2 (ja) | 2017-02-01 |
EP2735967A2 (en) | 2014-05-28 |
KR101818760B1 (ko) | 2018-01-15 |
KR20130011805A (ko) | 2013-01-30 |
JP2014522029A (ja) | 2014-08-28 |
EP2735967A4 (en) | 2015-07-22 |
US20140156251A1 (en) | 2014-06-05 |
CN103748557A (zh) | 2014-04-23 |
US10162913B2 (en) | 2018-12-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9552448B2 (en) | Method and apparatus for electronic system model generation | |
JP3746371B2 (ja) | 性能シミュレーション方法 | |
US6785760B2 (en) | Performance of a PCI-X to infiniband bridge | |
WO2011053038A2 (ko) | 교착 상태의 방지를 위한 데이터 처리 방법 및 시스템 | |
WO2021034024A1 (en) | Electronic apparatus and method for controlling thereof | |
WO2016064158A1 (ko) | 재구성 가능 프로세서 및 그 동작 방법 | |
WO2013015569A2 (ko) | 시뮬레이션 장치 및 그의 시뮬레이션 방법 | |
JP2001273154A (ja) | 有限状態のマシーン制御をハードウエア実行データ構造操作により置換するパーフォーマンス向上方法およびシステム | |
KR101704751B1 (ko) | 모듈 간의 타이밍 정보를 이용하는 멀티코어 시스템의 시뮬레이터, 및 그 시뮬레이션 방법 | |
WO2018124331A1 (ko) | 그래프 처리 시스템 및 그래프 처리 시스템의 동작 방법 | |
JP2008059192A (ja) | ハード・ソフト協調検証用シミュレータ | |
WO2014137008A1 (ko) | 그래픽 자원 공유 시스템 및 방법 | |
JP3387464B2 (ja) | 通信制御システムとその制御方法 | |
EP4142217A1 (en) | Inter-node communication method and device based on multiple processing nodes | |
JP2901882B2 (ja) | 計算機システムおよび入出力命令の発行方法 | |
JPH11265297A (ja) | 分散シミュレータシステム | |
WO2020184982A1 (ko) | 이종클러스터 시스템에서 실행되는 프로그램을 실행시키는 방법 및 컴퓨터 프로그램 | |
CN104050131A (zh) | 片上系统及其操作方法 | |
WO2023085611A1 (ko) | 메모리 어레이 내의 연결 회로 | |
WO2024058615A1 (ko) | 신경 처리부를 포함하는 전자 장치 및 그 동작 방법 | |
WO2024139420A1 (zh) | 一种模型训练方法、装置、设备、系统和存储介质 | |
WO2023128357A1 (ko) | 소프트웨어 기반의 개별분리 아키텍처 시스템 시뮬레이터 및 그의 방법 | |
CN116339944B (zh) | 任务处理方法、芯片、多芯片模块、电子设备和存储介质 | |
WO2024143564A1 (ko) | 딥러닝 추론을 위한 컴퓨팅 시스템, 하드웨어 가속기 장치 및 방법 | |
WO2022030866A1 (ko) | 데이터 처리 장치 및 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 12818145 Country of ref document: EP Kind code of ref document: A2 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 14233610 Country of ref document: US |
|
ENP | Entry into the national phase |
Ref document number: 2014521563 Country of ref document: JP Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2012818145 Country of ref document: EP |
|
NENP | Non-entry into the national phase |
Ref country code: DE |