WO2013015569A3 - 시뮬레이션 장치 및 그의 시뮬레이션 방법 - Google Patents

시뮬레이션 장치 및 그의 시뮬레이션 방법 Download PDF

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Publication number
WO2013015569A3
WO2013015569A3 PCT/KR2012/005799 KR2012005799W WO2013015569A3 WO 2013015569 A3 WO2013015569 A3 WO 2013015569A3 KR 2012005799 W KR2012005799 W KR 2012005799W WO 2013015569 A3 WO2013015569 A3 WO 2013015569A3
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WIPO (PCT)
Prior art keywords
simulation
blocks
operations
computation
method therefor
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PCT/KR2012/005799
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English (en)
French (fr)
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WO2013015569A2 (ko
Inventor
김경훈
김중백
이승욱
Original Assignee
삼성전자 주식회사
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Publication date
Application filed by 삼성전자 주식회사 filed Critical 삼성전자 주식회사
Priority to JP2014521563A priority Critical patent/JP6072028B2/ja
Priority to CN201280036428.0A priority patent/CN103748557B/zh
Priority to EP12818145.0A priority patent/EP2735967A4/en
Priority to US14/233,610 priority patent/US10162913B2/en
Publication of WO2013015569A2 publication Critical patent/WO2013015569A2/ko
Publication of WO2013015569A3 publication Critical patent/WO2013015569A3/ko

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466—Performance evaluation by tracing or monitoring
    • G06F11/3495—Performance evaluation by tracing or monitoring for systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3457—Performance evaluation by simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/20—Design optimisation, verification or simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/20—Design optimisation, verification or simulation
    • G06F30/25—Design optimisation, verification or simulation using particle-based methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061—Partitioning or combining of resources
    • G06F9/5066—Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3409—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
    • G06F11/3419—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment by assessing time
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00—Indexing scheme relating to G06F9/00
    • G06F2209/50—Indexing scheme relating to G06F9/50
    • G06F2209/5017—Task decomposition

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Geometry (AREA)
  • Evolutionary Computation (AREA)
  • Quality & Reliability (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)
  • Debugging And Monitoring (AREA)
  • Monitoring And Testing Of Transmission In General (AREA)
  • Mobile Radio Communication Systems (AREA)

Abstract

본 발명은 시뮬레이션 방법 및 장치에 관한 것으로, 본 발명의 복수 개의 블록을 이용하여 시뮬레이션을 수행하는 방법은 상기 시뮬레이션을 블록 고유한 기능을 수행하는 계산 연산(computation)과, 서로 다른 블록 사이에서 데이터 교환을 수행하는 통신 연산(communication)으로 분할하는 단계, 상호 의존적인 계산 연산과 통신 연산끼리 그룹화하는 그룹화 단계 및 상기 계산 연산과 통신 연산 사이의 의존도 해결 여부에 따라 각각의 그룹에 포함된 연산을 상기 블록을 이용하여 수행하는 시뮬레이션 수행 단계를 포함하는 것을 특징으로 한다.
PCT/KR2012/005799 2011-07-22 2012-07-20 시뮬레이션 장치 및 그의 시뮬레이션 방법 WO2013015569A2 (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2014521563A JP6072028B2 (ja) 2011-07-22 2012-07-20 シミュレーション装置及びそのシミュレーション方法
CN201280036428.0A CN103748557B (zh) 2011-07-22 2012-07-20 仿真设备及其仿真方法
EP12818145.0A EP2735967A4 (en) 2011-07-22 2012-07-20 SIMULATION DEVICE AND CORRESPONDING SIMULATION METHOD
US14/233,610 US10162913B2 (en) 2011-07-22 2012-07-20 Simulation device and simulation method therefor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020110073219A KR101818760B1 (ko) 2011-07-22 2011-07-22 시뮬레이션 장치 및 그의 시뮬레이션 방법
KR10-2011-0073219 2011-07-22

Publications (2)

Publication Number Publication Date
WO2013015569A2 WO2013015569A2 (ko) 2013-01-31
WO2013015569A3 true WO2013015569A3 (ko) 2013-03-21

Family

ID=47601624

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2012/005799 WO2013015569A2 (ko) 2011-07-22 2012-07-20 시뮬레이션 장치 및 그의 시뮬레이션 방법

Country Status (6)

Country Link
US (1) US10162913B2 (ko)
EP (1) EP2735967A4 (ko)
JP (1) JP6072028B2 (ko)
KR (1) KR101818760B1 (ko)
CN (1) CN103748557B (ko)
WO (1) WO2013015569A2 (ko)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6232470B2 (ja) * 2015-06-16 2017-11-15 株式会社日立製作所 分散コンピューティング環境でシステムのプロセスの検証を行うための方法
US10366359B2 (en) * 2015-11-18 2019-07-30 Microsoft Technology Licensing, Llc Automatic extraction and completion of tasks associated with communications
KR101988482B1 (ko) * 2017-08-21 2019-06-12 국방과학연구소 전술 데이터 링크 시스템, 전술 데이터 링크 시스템의 데이터 처리 장치

Citations (4)

* Cited by examiner, † Cited by third party
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JP2008198025A (ja) * 2007-02-14 2008-08-28 Fujitsu Ltd 並列処理制御プログラム、並列処理制御システムおよび並列処理制御方法
WO2010004474A2 (en) * 2008-07-10 2010-01-14 Rocketic Technologies Ltd Efficient parallel computation of dependency problems
WO2011017026A1 (en) * 2009-07-27 2011-02-10 Advanced Micro Devices, Inc. Mapping processing logic having data parallel threads across processors
KR20110023832A (ko) * 2009-08-31 2011-03-08 인터내셔널 비지네스 머신즈 코포레이션 멀티 코어/쓰레드 워크-그룹 연산 스케쥴러

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US6948172B1 (en) 1993-09-21 2005-09-20 Microsoft Corporation Preemptive multi-tasking with cooperative groups of tasks
JP3492105B2 (ja) * 1996-08-30 2004-02-03 株式会社東芝 ハードウェア／ソフトウェア協調シミュレーション装置及びシミュレーション方法
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JP2003067439A (ja) 2001-08-30 2003-03-07 Matsushita Electric Ind Co Ltd システムシミュレーション方法
JP2003233633A (ja) 2002-02-07 2003-08-22 Sanyo Electric Co Ltd 集積回路の設計方法
JP4667206B2 (ja) * 2005-10-31 2011-04-06 富士通セミコンダクター株式会社 マルチコアモデルシミュレーションプログラム、該プログラムを記録した記録媒体、マルチコアモデルシミュレータ、およびマルチコアモデルシミュレーション方法
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JP2008198025A (ja) * 2007-02-14 2008-08-28 Fujitsu Ltd 並列処理制御プログラム、並列処理制御システムおよび並列処理制御方法
WO2010004474A2 (en) * 2008-07-10 2010-01-14 Rocketic Technologies Ltd Efficient parallel computation of dependency problems
WO2011017026A1 (en) * 2009-07-27 2011-02-10 Advanced Micro Devices, Inc. Mapping processing logic having data parallel threads across processors
KR20110023832A (ko) * 2009-08-31 2011-03-08 인터내셔널 비지네스 머신즈 코포레이션 멀티 코어/쓰레드 워크-그룹 연산 스케쥴러

Also Published As

Publication number Publication date
CN103748557B (zh) 2017-05-31
JP6072028B2 (ja) 2017-02-01
EP2735967A4 (en) 2015-07-22
KR101818760B1 (ko) 2018-01-15
EP2735967A2 (en) 2014-05-28
US10162913B2 (en) 2018-12-25
CN103748557A (zh) 2014-04-23
US20140156251A1 (en) 2014-06-05
WO2013015569A2 (ko) 2013-01-31
JP2014522029A (ja) 2014-08-28
KR20130011805A (ko) 2013-01-30

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