WO2012053687A1

WO2012053687A1 - Control system that is reconfigurable during operation, and method therefor

Info

Publication number: WO2012053687A1
Application number: PCT/KR2010/007795
Authority: WO
Inventors: 최성훈; 김민수; 박영준; 하영열
Original assignee: 삼성중공업 주식회사
Priority date: 2010-10-22
Filing date: 2010-11-05
Publication date: 2012-04-26
Also published as: JP5646764B2; CN103262405A; DE112010005955T5; JP2014500644A; CN103262405B

Abstract

Disclosed is a control system that is reconfigurable during operation, and a method therefor. The control system according to one embodiment of the present invention comprises a master controller which generates a bit stream, including reconfiguration information, according to the command of a user. The first slave controller comprises: a first dynamic reconfiguration module, which is a field programmable gate array (FPGA) reconfigured according to the reconfiguration information, and which calculates a control value; a static reconfiguration module which is an FPGA controlling the operation of a target apparatus according to the control value; and a control unit reconfiguring one or more of the first dynamic reconfiguration module and the static reconfiguration module according to the reconfiguration information.

Description

Control system capable of reconfiguring during operation and method

The present invention relates to a control system and a method thereof, and more particularly, to a control system and a method capable of reconfiguring in operation.

Devices such as robots use servo motors for operation. The operation of the device can be controlled through the control of the servo motor.

In general, operation control is performed using a master controller and a slave controller. The master controller sends a control signal to each slave controller, and the slave controller controls the corresponding servo motor according to the control signal. The master controller can be connected with a plurality of slave controllers, each slave controller controlling a corresponding servo motor.

The slave controller generally mounts a functional board package suitable for the operation of the servo motor. However, the slave controller has a problem in that it can control only the corresponding servo motor. That is, there is a problem that the slave controller needs to be replaced when changing the servo motor to another model.

An object of the present invention is to provide a control system and method capable of reconfiguring an operation of changing a control scheme of a device by reconfiguring a structure of a field array (FPGA) while maintaining control of the device.

According to an aspect of the present invention, a master controller for generating a bitstream including reconfiguration information according to a user command; And a first slave controller, wherein the first slave controller comprises: a first dynamic reconfiguration module (FPGA) which is reconfigured according to the reconfiguration information to produce a control value; A static reconfiguration module which is a gate array controlling an operation of a target device according to the control value; And a control unit configured to reconfigure at least one of the first dynamic reconfiguration module and the static reconfiguration module according to the reconfiguration information.

The controller may reconfigure the gate array structure of the dynamic reconfiguration module independently of the operation of the static reconfiguration module.

The slave controller may further include a second dynamic reconfiguration module, which is a gate array reconfigured according to the reconfiguration information to calculate a control value. The controller may further include the reconfiguration information when the capacity of the reconfiguration information is equal to or greater than a specified value. Accordingly, the second dynamic reconfiguration module may be controlled to be reconfigured, and the operation of the first dynamic reconfiguration module may be maintained until the reconfiguration of the second dynamic reconfiguration module is completed.

The controller may stop the operation of the first dynamic reconfiguration module when the reconfiguration of the second dynamic reconfiguration module is completed.

The master controller may further include a reconfiguration library storage unit for storing function information indicating a connection relationship between the gates of the first dynamic reconfiguration module or the static reconfiguration module; A reconstruction information combination unit configured to extract the function information according to the command and generate the reconstruction information by combining the extracted function information; And an entry manager to generate a bitstream including the reconfiguration information.

The slave communication unit may further include a slave communication unit configured to transmit the bitstream to the first slave controller, wherein the entry manager generates reconfiguration time information at which it is time to transmit the bitstream according to the command. The bitstream may be transmitted to the first slave controller when a predetermined period arrives or when the bitstream is generated according to time information.

The method may further include a second slave controller which is a controller having the same configuration as the first slave controller, wherein the master controller includes the bitstream including reconfiguration information corresponding to each of the first slave controller and the second slave controller. Can be generated.

In addition, the master controller, the first slave controller and the second slave controller may be connected to a network of a dual ring structure.

In addition, when the target device is changed, the static reconfiguration module may be a gate array reconfigured according to the reconfiguration information.

According to another aspect of the present invention, a method for controlling an operation of a target device by a reconfigurable control system, the method comprising: generating a bitstream including reconfiguration information according to a user's command; Reconstructing a first gate array (FPGA) that is reconstructed according to the reconstruction information to produce a control value; Calculating a control value using the reconstructed gate array; And transmitting the control value to a second gate array that controls an operation of the target device.

In addition, the reconstructing the first gate array may be independent of the operation of the second gate array.

The method may further include reconfiguring a third gate array configured to be reconfigured according to the reconstruction information and calculating a control value when the capacity of the reconstruction information is equal to or greater than a specified value, until the reconstruction of the third gate array is completed. Operation of the first gate array can be maintained.

The method may further include stopping the operation of the first gate array when the reconstruction of the third gate array is completed.

The generating of the bitstream may include extracting the function information from a storage space of the control system that stores function information indicating a connection relationship between each gate of the first gate array or the second gate array according to the command. Making; Generating the reconstruction information by combining the extracted function information; And generating a bitstream including the reconstruction information.

1 shows a control system;

2 illustrates the structure of a bitstream generated by a master controller of a control system.

3 is a block diagram conceptually illustrating a configuration of a master controller.

4 is a diagram illustrating a process in which a master controller generates reconfiguration information.

5 is a block diagram schematically illustrating a functional unit configuring a first slave controller.

6 is a flowchart illustrating a process in which a control system controls the operation of a servo motor.

1 is a view showing a control system capable of reconfiguring during operation according to an embodiment of the present invention.

Referring to FIG. 1, a control system according to an embodiment of the present invention includes a master controller 101, a first slave controller 102, and a second slave controller 103. Although two slave controllers are illustrated in FIG. 1, the control system according to an embodiment of the present invention may include various numbers of slave controllers according to an environment to which the present invention is applied. In addition, each slave controller may be connected to one or more sensors that sense acceleration, heat generation, etc. for each servo motor and the corresponding servo motor.

The master controller 101 receives a command for an operation to control the operation from an input device (for example, a PC) (not shown). At this time, the command received from the input device is a signal indicating a command to operate according to any one of the patterns of the servo motor operation. In order to operate the servo motor according to a pattern corresponding to the received command, the master controller 101 matches the received command with one or more reconfiguration information instructing reconfiguration of the field programmable gate array (FPGA) included in each slave controller. Can be stored. For example, the master controller 101 may generate a bitstream including a command received from an input device and reconfiguration information matching the command.

For example, as illustrated in FIG. 1, when there are two

slave controllers

102 and 103, the master controller 101 may include first reconfiguration information and a second slave controller corresponding to the first slave controller 102. One or more of the second reconstruction information corresponding to 103 may be generated to generate a bitstream.

Hereinafter, the structure of the bitstream will be described in detail with reference to FIG. 2.

2 illustrates a structure of a bitstream generated by a master controller of a control system according to an exemplary embodiment of the present invention.

The master controller 101 controls the first slave controller 102 and the second slave controller to control servo motors respectively connected to the first slave controller 102 and the second slave controller 103 according to a command received from the input device. A bitstream including reconfiguration information indicating reconfiguration of the FPGA included in 103 is generated.

At this time, the master controller 101 allows the reconfiguration information to be located after the slave identification information, which is information for identifying each slave controller, in the bitstream, so that each slave controller can easily extract the corresponding reconfiguration information.

For example, the first slave identification information 210 and the first reconfiguration information 220 illustrated in FIG. 2 are slave identification information and reconfiguration information corresponding to the first slave controller 102, and the second slave identification information ( 230 and the second reconfiguration information 240 are slave identification information and reconfiguration information corresponding to the second slave controller 103. The first slave controller 102 retrieves the first slave identification information 210 included in the bitstream, and reconstructs the data from the first slave identification information 210 to the first slave identification information before the next slave identification information 220. ), And the first reconstruction information 220 may be extracted from the bitstream.

Referring back to FIG. 1, the master controller 101 may periodically generate a plurality of bitstreams for a command received from an input device.

For example, assume that a command received from an input device is a command for instructing the servo motor to alternately perform a process of operation and stop every predetermined period. In this case, the master controller 101 may alternately generate a bitstream including reconfiguration information for performing the operation of the servo motor and a bitstream including reconfiguration information for stopping the servo motor at predetermined cycles. . Hereinafter, the configuration of the master controller 101 will be described in detail with reference to FIG. 3.

3 is a block diagram conceptually illustrating a configuration of a master controller. Referring to FIG. 3, the master controller 101 includes a host communication unit 310, a reconfiguration information combination unit 320, a reconfiguration library storage unit 330, an entry manager 340, and a slave communication unit 350.

The host communicator 310 receives a user's command from an input device through a network. The host communicator 310 transmits the received command to the reconfiguration information combiner 320.

The reconfiguration information combination unit 320 extracts one or more function information stored in the reconfiguration library storage unit according to a command received from the host communication unit 310, and generates reconfiguration information by combining the extracted function information.

Here, the function information according to the embodiment of the present invention may include information on the connection relationship between the gates of the FPGA of the slave controller, it may be represented in various ways such as a bit string. In addition, the FPGA according to the embodiment of the present invention may perform a specific function when reconfigured according to the function information. The process of generating reconfiguration information will be described in detail later with reference to FIG. 4. At this time, the reconstruction information combination unit 320 transmits the generated reconstruction information to the entry manager 340.

The entry manager 340 generates reconstruction time information and reconstruction mode information based on the reconstruction information received from the reconstruction information combination unit 320.

At this time, the reconfiguration time information is information indicating whether the time point at which the bitstream including the reconstruction information is transmitted is immediately transmitted or the time point at which the slave communication unit 350 periodically transmits the bitstream.

At this time, the reconfiguration mode information is information indicating whether each slave controller receiving the corresponding bitstream reconfigures the FPGA.

The entry manager 340 inserts reconfiguration mode information into reconfiguration information, generates a bitstream including each reconfiguration information and slave identification information, and transmits the reconstruction information to the slave communication unit 350 along with reconfiguration time information.

The slave communication unit 350 transmits the bitstream to the first slave controller 102 or the second slave controller 103 according to the reconfiguration time information. That is, when the slave communication unit 350 indicates that the reconstruction time information immediately transmits the bitstream, the slave communication unit 350 immediately transmits the bitstream to the slave controller, and when the reconstruction time information indicates transmitting the bitstream according to the transmission period, The stream is transmitted when the transmission period specified in the slave communication unit 350 arrives.

Referring back to FIG. 1, the master controller 101 transmits the generated bitstream to the first slave controller 102. In this case, the master controller 101 may be connected to the first slave controller 102 and the second slave controller 103 in a double ring structure. That is, the second slave controller 103 may not receive the bitstream transmitted by the master controller 101 to the first slave controller 102. In this case, using the double ring structure, the master controller 101 can transmit the generated bitstream back to the second slave controller 103. Therefore, according to the exemplary embodiment of the present invention, even if some of the networks between the master controller 101, the first slave controller 102, and the second slave controller 103 are disconnected, it can be operated normally.

The first slave controller 102 extracts reconfiguration information from the bitstream received from the master controller 101, reconfigures the FPGA according to the reconfiguration information, and controls the servo motor using the reconfigured FPGA. Hereinafter, the structure of the first slave controller 102 will be described in detail with reference to FIG. 5.

4 is a diagram illustrating a process of generating reconfiguration information by a master controller.

Referring to FIG. 4, the reconstruction information combining unit 320 of the master controller 101 receives a command from an input device. The reconstruction information combination unit 320 extracts necessary function information from the reconstruction library storage unit 330 according to the received command. The reconfiguration library storage unit 330 stores one or more function information, and the reconfiguration information combination unit 320 may store in advance a list of function information required for reconfiguration of the FPGA according to each command that may be received from a user. Therefore, upon receiving the command, the reconstruction information combination unit 320 retrieves a list of function information matching the command, extracts the function information included in the searched list from the reconstruction library storage unit 330, and combines the function information. To generate reconstruction information.

For example, the reconstruction library storage unit 330 includes function information on an algorithm to be performed by a slave controller, function information indicating a function of receiving data from a sensor performing a sensing function of a servo motor, and controlling actual motor driving. Function information indicating the function can be stored. The reconstruction information combination unit 320 receives the command 1 from the input device 410 and retrieves a list of the stored function information matching the command 1. The reconstruction information combining unit 320 confirms that the function information included in the list of the function information is algorithm 1, sensor input 1, and motor driving 2, and extracts each function information from the reconstruction library storage unit 330. The reconstruction information combination unit 320 generates the reconstruction information 420 corresponding to the command 1 by combining the extracted function information. The reconfiguration information combiner 320 may transmit the reconfiguration information 420 to the entry manager 340.

The master controller 101 has been described as generating reconstruction information by extracting and combining function information from the reconstruction information combination unit 320, but the reconstruction information itself corresponding to each command in advance in the reconstruction information combination unit 320 is described. When receiving a command, the reconfiguration information combination unit 320 may transmit reconfiguration information corresponding to the command to the entry manager 340. Accordingly, the master controller 101 may extract reconfiguration information and transmit the reconfiguration information to the entry manager 340 without a separate function information combining process.

5 is a block diagram schematically illustrating a functional unit configuring a first slave controller. Referring to FIG. 3, the first slave controller 102 includes a controller 510 and a reconstructor 520.

The controller 510 receives the bitstream from the master controller 101 and extracts reconstruction information from the bitstream. The controller 510 checks whether reconfiguration mode information included in the reconfiguration information indicates reconfiguration of the FPGA. If the reconfiguration mode information does not indicate reconfiguration of the FPGA, the controller 510 does not perform a reconfiguration process of the FPGA. When the reconfiguration mode information indicates reconstruction of the FPGA, the controller 510 reconstructs the gate array structure of the reconstruction unit 520 according to the reconstruction information. For example, an FPGA structure in which reconstruction information receives data according to sensing of a servo motor from a sensor, calculates the received data according to a predetermined algorithm, and controls the servo motor according to the calculated result. In this case, the controller 510 controls the reconstruction unit 520 to reconfigure the FPGA according to the reconfiguration information.

In this case, although the controller 510 has decided to perform the reconfiguration process according to the reconfiguration mode information, according to another embodiment of the present invention, the controller 510 may determine the reconfiguration information corresponding to the corresponding slave controller in the bitstream. It can be determined whether or not FPGA reconfiguration should be performed based on the inclusion.

The reconstruction unit 520 includes a static reconstruction module 523, a first dynamic reconstruction module 526, and a second dynamic reconstruction module 529 configured as FPGAs. The static reconfiguration module 523 controls the operation of the servo motor. The static reconfiguration module 523 controls the operation of the servo motor. The static reconfiguration module 523 controls the operation of the servo motor. It can be controlled to perform rotational acceleration, reverse rotational acceleration, stop, and the like. Since the static reconfiguration module 523 directly controls the operation of the servo motor, reconfiguration is not performed while the first slave controller 102 controls the servo motor. However, the static reconfiguration module 523 may perform reconfiguration when the servo motor is replaced with another type of device. More specifically, when the user commands the control of the other type of devices replaced through the input device, the master controller 101 includes reconfiguration information indicating the reconfiguration of the static reconfiguration unit 523 to correspond to the command For example, the bitstream may be transmitted to the controller 510 of the first slave controller 102. The controller 510 reconfigures the gate array structure of the static reconstruction unit 523 according to the reconstruction information included in the bitstream so as to control the replaced other type of device.

In addition, the first dynamic reconfiguration module 526 is reconfigured from the FPGA independently of the static reconfiguration module 523 under the control of the controller 510. That is, the first dynamic reconfiguration module 526 is reconfigured regardless of whether the static reconfiguration module 523 is currently controlling or reconfiguring the servo motor.

For example, the dynamic reconfiguration module 526 receives the rotational speed of the servo motor from a sensor that detects the rotational speed of the servo motor, and calculates according to an algorithm determined for the rotational speed of the servo motor when the rotational speed is equal to or greater than a specified speed. Can be performed. The dynamic reconfiguration module 323 may transmit the control value that is the result of the operation to the static reconfiguration module 523. In addition, the static reconstruction module 323 may adjust the rotation speed at a speed according to the received control value.

As another example of the reconfiguration process of the first dynamic reconfiguration module 526, the data is sequentially received from the first sensor, the second sensor, and the third sensor for the control of the servo motor, and operation is required through a first algorithm. Suppose that a bitstream for this is generated in the master controller 101. In this case, the controller 510 may receive the first bitstream from the master controller 101. In this case, the first bitstream includes reconfiguration information indicating an FPGA structure for receiving data from the first sensor and performing a calculation through a first predetermined algorithm. Subsequently, the controller 510 controls the first dynamic reconfiguration module 526 to reconstruct the FPGA structure according to the reconfiguration information. At this time, the first static reconfiguration module 523 may continue to control the servo motor. After completing the reconfiguration, the dynamic reconfiguration module 526 receives data from the first sensor according to the FPGA structure, and calculates a control value, which is a value calculated through the first algorithm. The dynamic reconfiguration module 526 sends control values to the static reconfiguration module 523. The static reconfiguration module 523 continues to control the servo motor according to the control value.

Thereafter, the controller 510 may receive the second bitstream from the master controller 101. In this case, the second bitstream includes reconfiguration information indicating an FPGA structure for receiving data from a second sensor and performing an operation through a first algorithm. Subsequently, the first dynamic reconfiguration module 526 is reconfigured into an FPGA structure for receiving data from the second sensor through the above-described process and performs an operation. In addition, the static reconstruction module 523 continues to control the servo motor according to the control value.

Thereafter, the controller 510 may receive the third bitstream from the master controller 101. In this case, the third bitstream includes reconfiguration information indicating an FPGA structure for receiving data from the third sensor and performing calculation through the first algorithm. Subsequently, the first dynamic reconfiguration module 526 is reconfigured into an FPGA structure for receiving data from the third sensor through the above-described process and performs an operation. In addition, the static reconstruction module 523 continues to control the servo motor according to the control value.

Therefore, a function of sequentially receiving data from the first sensor, the second sensor, and the third sensor may be performed.

In the conventional operation controller, when a process of sequentially receiving data from each sensor is to be performed, all modules for receiving data from each sensor should be provided, and accordingly, the circuit size of the operation controller has to be increased. The first slave controller 510 sequentially receives data from each sensor for controlling the servo motor using one dynamic reconfiguration module 526 while maintaining control of the servo motor using the static reconfiguration module 523. It is possible. Therefore, the above-described control system can be implemented in a relatively small size compared to the conventional operation controller.

In this case, the functions of the above-described static reconfiguration module 523 and the first dynamic reconfiguration module 526 are not limited to the above-described functions, only embodiments. That is, the functions of the static reconstruction module 523 and the first dynamic reconstruction module 526 may vary according to reconstruction information of the bitstream received by the controller 510.

The second dynamic reconfiguration module 529 is a module having the same configuration as the first dynamic reconfiguration module 526 and may be reconfigured as in the reconfiguration process of the first dynamic reconfiguration module 526 described above.

According to another embodiment of the present invention, the controller 510 may reconfigure the FPGA structure of the first dynamic reconfiguration module 526 or the second dynamic reconfiguration module 529 according to the capacity of the reconfiguration information extracted from the bitstream.

For example, assuming that the first dynamic reconfiguration module 526 is currently operating, the controller 510 controls the FPGA of the second dynamic reconfiguration module 529 that is not currently operated when the capacity of the reconfiguration information is greater than or equal to a specified capacity. Reconstruct according to the reconstruction information. After the reconfiguration is completed, the second dynamic reconfiguration module 529 transmits a reconfiguration completion signal indicating that the reconfiguration is completed, to the controller 510. When the control unit 510 receives the reconfiguration completion signal, the controller 510 transmits an operation stop request for requesting to stop the operation to the first dynamic reconfiguration module 526 currently in operation. The first dynamic reconfiguration module 526 stops the operation according to the stop operation request. At this time, the second dynamic reconfiguration module 529 having the structure of the FPGA reconstructed according to the reconfiguration information performs an operation and transmits the calculation result to the static reconfiguration module 523. In addition, the static reconfiguration module 423 may receive a calculation result from the second dynamic reconfiguration module 526 and control the servo motor.

Although the above-described control unit 510 has been described as determining that the capacity of the reconstruction information of the bitstream received from the master controller 101 is equal to or larger than a specified value, the control unit 510 of the master controller 101 reconfigures according to an implementation method. It may be determined that the capacity of the information is greater than or equal to the designated value, and the information according to the information may be inserted into the header of the reconstruction information. In this case, the controller 510 may perform the reconstruction process of the first dynamic reconfiguration module 526 or the second dynamic reconfiguration module 529 by checking the corresponding information in the header of the reconfiguration information.

6 is a flowchart illustrating a process of controlling a servo motor by a control system.

Referring to FIG. 6, in operation 610, the master controller 101 receives a command from an input device.

In operation 620, the master controller 101 generates a bitstream for controlling the servo motor according to the command received in operation 610. At this time, the master controller 101 generates a bitstream including reconfiguration information indicating the FPGA structure of the slave controller required to control the servo motor according to the command. The master controller 101 transmits the generated bitstream to the first slave controller.

In operation 630, the first slave controller 102 extracts reconfiguration information from the received bitstream. In this case, the first slave controller may extract the reconfiguration information and then transmit the bitstream to the second slave controller 103. The second slave controller 103 receiving the bitstream may perform the same process as the operation of the first slave controller 102 after step 630.

In operation 640, the first slave controller 102 reconstructs the structure of the reconstruction unit, which is an FPGA module, according to the reconfiguration information. At this time, when the first slave controller 102 reconfigures the first dynamic reconfiguration module 526 which is currently controlling the servo motor among the plurality of dynamic reconfiguration modules according to the reconfiguration information, the first slave controller 102 performs the servo motor. If it is necessary to stop the control of the, to reconfigure the configuration of the second dynamic reconfiguration module 529. When the reconfiguration of the second dynamic reconfiguration module 529 is completed, the first slave controller 102 stops the operation of the first dynamic reconfiguration module 526 and replaces the second dynamic reconfiguration module 529 and the static reconfiguration module 523. Servo motor can be controlled. Also, the first slave controller 102 may independently perform reconfiguration of the static reconfiguration module 523, the first dynamic reconfiguration module 526, and the second dynamic reconfiguration module 529 according to the reconfiguration information. That is, when the first slave controller 102 shows only the structure of the first dynamic reconfiguration module 526 or the second dynamic reconfiguration module 529 in the reconfiguration information, the static reconfiguration module 523 controls the servo motor. During the operation, the first dynamic reconfiguration module 526 or the second dynamic reconfiguration module 529 may be reconfigured.

In operation 650, the first slave controller 102 controls the operation of the servo motor using the reconstruction unit reconfigured in operation 640.

Although the above-described control system has been described as controlling the servo motor, it is apparent that the reconfiguration information can be configured to be suitable for other devices to control devices other than the servo motor.

So far I looked at the center of the embodiment for the present invention. Many embodiments other than the above-described embodiments are within the claims of the present invention. Those skilled in the art will appreciate that the present invention can be implemented in a modified form without departing from the essential features of the present invention. Therefore, the disclosed embodiments should be considered in descriptive sense only and not for purposes of limitation. The scope of the present invention is shown in the claims rather than the foregoing description, and all differences within the scope will be construed as being included in the present invention.

The control system and method thereof according to an embodiment of the present invention have the effect of flexibly controlling various devices by reconfiguring the gate array structure according to a user input.

The control system and method according to an embodiment of the present invention can reduce the size of the control device by reconfiguring the structure of the gate array and controlling the device using the reconstructed gate array.

Claims

A master controller for generating a bitstream including reconfiguration information according to a user command; And

Including a first slave controller,

The first slave controller

A first dynamic reconfiguration module (FPGA) which is reconfigured according to the reconstruction information and generates a control value;

A static reconfiguration module which is a gate array controlling an operation of a target device according to the control value; And

And a control unit configured to reconfigure at least one of the first dynamic reconfiguration module and the static reconfiguration module according to the reconfiguration information.
According to claim 1,

And the controller reconfigures the gate array structure of the dynamic reconfiguration module independently of the operation of the static reconfiguration module.
According to claim 1,

The slave controller

And a second dynamic reconfiguration module, which is a gate array reconfigured according to the reconfiguration information to calculate a control value.

The control unit

If the capacity of the reconstruction information is greater than or equal to a specified value, the control unit reconfigures the second dynamic reconstruction module according to the reconstruction information, and the operation of the first dynamic reconstruction module until the reconstruction of the second dynamic reconstruction module is completed. Reconfigurable control system during operation, characterized in that to maintain.
The method of claim 3, wherein

The control unit

And stopping the operation of the first dynamic reconfiguration module when the reconfiguration of the second dynamic reconfiguration module is completed.
According to claim 1,

The master controller

A reconstruction library storage unit for storing function information indicating a connection relationship between the gates of the first dynamic reconfiguration module or the static reconfiguration module;

A reconstruction information combination unit for extracting the function information according to the command and generating the reconstruction information by combining the extracted function information; And

An entry manager which generates a bitstream including the reconfiguration information

Reconfigurable control system during operation comprising a.
The method of claim 5,

Further comprising a slave communication unit for transmitting the bitstream to the first slave controller,

When the entry manager generates reconfiguration time information that is a point in time at which the bitstream is to be transmitted according to the command, the slave communication unit is configured when the predetermined period arrives or when the bitstream is generated according to the reconfiguration time information. Reconfigurable control system during operation, characterized in that for transmitting a bitstream to the first slave controller.
According to claim 1,

Further comprising a second slave controller which is a controller having the same configuration as the first slave controller,

And the master controller generates the bitstream including reconfiguration information corresponding to each of the first slave controller and the second slave controller.
The method of claim 7, wherein

And the master controller, the first slave controller and the second slave controller are connected in a double ring network.
The method of claim 1,

If the target device is changed,

And the static reconstruction module is a gate array reconstructed according to the reconstruction information.
In the method that the reconfigurable control system controls the operation of the target device,

Generating a bitstream including reconfiguration information according to a user command;

Reconstructing a first gate array (FPGA) that is reconstructed according to the reconstruction information to produce a control value;

Calculating a control value using the reconstructed gate array; And

And transmitting the control value to a second gate array controlling the operation of the target device.
The method of claim 10,

Reconstructing the first gate array

And a reconfigurable control method in operation which is independent of the operation of the second gate array.
The method of claim 11, wherein

If the capacity of the reconstruction information is equal to or greater than a specified value, reconstructing the third gate array reconstructed according to the reconstruction information to obtain a control value,

Operation of the first gate array is maintained until the reconstruction of the third gate array is completed.
The method of claim 12,

Stopping the operation of the first gate array when the reconstruction of the third gate array is completed.
The method of claim 10,

Generating the bitstream

Extracting the function information from a storage space of the control system that stores function information indicating a connection relationship between each gate of the first gate array or the second gate array according to the command;

Generating the reconstruction information by combining the extracted function information; And

And generating a bitstream including the reconstruction information.