CN103262405A - Control system that is reconfigurable during operation, and method therefor - Google Patents
Control system that is reconfigurable during operation, and method therefor Download PDFInfo
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- CN103262405A CN103262405A CN2010800697612A CN201080069761A CN103262405A CN 103262405 A CN103262405 A CN 103262405A CN 2010800697612 A CN2010800697612 A CN 2010800697612A CN 201080069761 A CN201080069761 A CN 201080069761A CN 103262405 A CN103262405 A CN 103262405A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/18—Numerical control [NC], i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form
- G05B19/404—Numerical control [NC], i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by control arrangements for compensation, e.g. for backlash, overshoot, tool offset, tool wear, temperature, machine construction errors, load, inertia
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/30—Nc systems
- G05B2219/34—Director, elements to supervisory
- G05B2219/34024—Fpga fieldprogrammable gate arrays
Abstract
Disclosed is a control system that is reconfigurable during operation, and a method therefor. The control system according to one embodiment of the present invention comprises a master controller which generates a bit stream, including reconfiguration information, according to the command of a user. The first slave controller comprises: a first dynamic reconfiguration module, which is a field programmable gate array (FPGA) reconfigured according to the reconfiguration information, and which calculates a control value; a static reconfiguration module which is an FPGA controlling the operation of a target apparatus according to the control value; and a control unit reconfiguring one or more of the first dynamic reconfiguration module and the static reconfiguration module according to the reconfiguration information.
Description
Technical field
The method that the present invention relates to a kind of control system and be used for it more specifically, relates to the control system of reconstruct in operation and for its method.
Background technology
Robot and similar device use servomotor to operate.Can the operation of control device by the control servomotor.
In general, can use master controller and from controller to operate control.Master controller is sent to each from controller with control signal, and each controls servomotor from controller corresponding to control signal.Master controller can link to each other from controller with a plurality of, and each controls corresponding servomotor from controller.
Usually have the feature board bag from controller, it is suitable for the operation of servomotor.Yet, be can only control corresponding servomotor from controller from the shortcoming of controller.In other words, changing under the situation of servomotor with another kind of model, also need change from controller.
Summary of the invention
Technical problem
The method that the invention provides a kind of control system and be used for it, this control system can be by reconstruct FPGA(field programmable gate array in the operation of modifier control method) structure and keep the control of this device to be reconstructed simultaneously.
Technical scheme
One aspect of the present invention has proposed a kind of control system that can be reconstructed in operation.Comprise master controller according to the described control system of one embodiment of the invention, its order according to the user generates the bit stream that comprises reconfiguration information.First comprises from controller: the first dynamic restructuring module, and it is for the field programmable gate array (FPGA) that is reconstructed according to reconfiguration information and calculate controlling value; Static reconstructed module, it is the FPGA according to the operation of described controlling value control destination apparatus; And control unit, its one or more according in the reconfiguration information reconstruct first dynamic restructuring module and the static reconstructed module.
Control unit can be independent of the operation of static reconstructed module and the FPGA structure of reconstruct dynamic restructuring module.
Also can comprise the second dynamic restructuring module from controller, it is for the FPGA that is reconstructed according to reconfiguration information and calculate controlling value, and when the capacity of reconfiguration information during greater than predetermined value, control unit can according to reconfiguration information control the second dynamic restructuring module it is reconstructed and the operation that keeps the first dynamic restructuring module up to finishing the reconstruct second dynamic restructuring module.
When finishing the reconstruct second dynamic restructuring module, control unit can stop the operation of the first dynamic restructuring module.
Master controller can comprise: reconstruct library storage unit, and it stores between the door of the indication first dynamic restructuring module or the function information of annexation between the door of static reconstructed module; The reconfiguration information combining unit, it is according to order abstraction function information and by generating reconfiguration information in conjunction with the function information that extracts; And the clauses and subclauses administrative unit, its generation comprises the bit stream of reconfiguration information.
Control system also can comprise from communication unit, it transfers to first from controller with bit stream, if and the clauses and subclauses administrative unit generates reconstitution time information according to order, be the time of transmission bit stream, then when generating bit stream, bit stream transferred to first from controller at each predetermined period or according to reconstitution time information from communication unit.
Control system also can comprise second from controller, and it is for having the controller of identical configuration with first from controller, and master controller generates bit stream, and it comprises with first from controller and second each corresponding reconfiguration information from controller.
Master controller, first can be connected by the twin nuclei of network from controller from controller with second.
Under the situation that changes destination apparatus, the FPGA of static reconstructed module for being reconstructed according to reconfiguration information.
Another aspect of the present invention proposed a kind of for the Reconfigurable Control system with control destination apparatus method of operating.Can comprise according to the described method of one embodiment of the invention: the order according to the user generates the bit stream that comprises reconfiguration information; Reconstruct primary scene programmable gate array (FPGA), it is reconstructed and calculates controlling value according to reconfiguration information; Use the FPGA of reconstruct to calculate controlling value; And described controlling value transferred to the 2nd FPGA, the operation of its control destination apparatus.
The reconstruct of the one FPGA is independent of the operation of the 2nd FPGA.
This method also comprises reconstruct the 3rd FPGA, and it is reconstructed and calculates controlling value when the capacity of reconfiguration information during greater than predetermined value according to reconfiguration information, and the operation that can keep a FPGA is up to finishing reconstruct the 3rd FPGA.
This method also comprises when finishing reconstruct the 3rd FPGA, stops the operation of a FPGA.
The generation of bit stream can comprise: from the memory space abstraction function information of control system, control system stores between the door of indication the one FPGA or the function information of annexation between the door of the 2nd FPGA according to order; By generating reconfiguration information in conjunction with the function information that extracts; And generation comprises the bit stream of reconfiguration information.
Description of drawings
Fig. 1 shows control system.
The diagram of the bit stream example that Fig. 2 generates for the master controller by control system.
Fig. 3 is the calcspar of explanation master controller concept structure.
Fig. 4 is the diagram that how to generate the example of reconfiguration information for the explanation master controller.
Fig. 5 is the calcspar of brief description composition first from the functional unit of controller.
Fig. 6 is how to control the flow chart of servomotor operation for the explanation control system.
Embodiment
Fig. 1 shows the control system that can be reconstructed in operation according to an embodiment of the invention.
With reference to Fig. 1, according to the described control system of one embodiment of the invention comprise master controller 101, first from controller 102 and second from controller 103.Though have two among Fig. 1 from controller, according to the control system of the embodiment of the invention can according to use concrete environment of the present invention have varying number from controller.In addition, each can be connected to the transducer of at least one acceleration for detection of each servomotor and described each servomotor, heat etc. from controller.
For example, if have two from controller 102, at 103 o'clock by shown in Figure 1, master controller 101 can generate bit stream from corresponding first reconfiguration information of controller 102 and with second from the second corresponding reconfiguration information of controller 103 at least one by comprising with first.
Hereinafter, describe the structure of bit stream in detail with reference to Fig. 2.
Fig. 2 is the diagram of the structure example of the bit stream that generates by the master controller of control system according to an embodiment of the invention.
Here, master controller 101 can allow with reconfiguration information place bit stream after identifying information, should from identifying information for identification each information from controller, thereby each can extract relevant reconfiguration information at an easy rate from controller.
For example in Fig. 2, first from identifying information 210 and first reconfiguration information 220 be with first from controller 102 corresponding from identifying information and reconfiguration information, and second from identifying information 230 and second reconfiguration information 240 be with second from controller 103 corresponding from identifying information and reconfiguration information.First can search for from controller 102 and to be contained in first in the middle of the bit stream from identifying information 210, identification first from identifying information 210 and next from the data between the identifying information as first reconfiguration information 220 and from this bitstream extraction first reconfiguration information 220.
Refer again to Fig. 1, master controller 101 can periodically produce the order that a plurality of bit streams receive from input unit with response.
For example, if the order indication servomotor that receives from input unit repeats operation on schedule at interval and stops step, master controller 101 can generate a bit stream, and it comprises be used to the reconfiguration information of carrying out the servomotor operation; And a bit stream, it comprises for the reconfiguration information that stops the servomotor operation on schedule at interval.Hereinafter, describe the structure of master controller 101 in detail with reference to Fig. 3.
Fig. 3 is the calcspar of explanation master controller concept structure.With reference to Fig. 3, master controller 101 comprises main-machine communication unit 310, reconfiguration information combining unit 320, reconstruct library storage unit 330, clauses and subclauses administrative unit 340 and from communication unit 350.
Main-machine communication unit 310 receives user's order by network from input unit.Main-machine communication unit 310 with the command transfer that receives to reconfiguration information combining unit 320.
Reconfiguration information combining unit 320 extracts one or more function informations that are stored in the reconstruct library storage unit according to the order that receives from main-machine communication unit 310, and by generating reconfiguration information in conjunction with the function information that extracts.
Here, function information can comprise the information of annexation between the door of relevant FPGA from controller and can pass through various forms according to an embodiment of the invention, shows as bit string.In addition, FPGA can carry out special function when being reconstructed according to this function information according to an embodiment of the invention.Below, describe the step that generates reconfiguration information in detail with reference to Fig. 4.Here, reconfiguration information combining unit 320 transfers to clauses and subclauses administrative unit 340 with the reconfiguration information that generates.
Clauses and subclauses administrative unit 340 generates reconstitution time information and reconfiguration mode information based on the reconfiguration information that receives from reconfiguration information combining unit 320.
Here, reconstitution time information indicates that the bit stream that will comprise reconfiguration information sends immediately or regularly sends bit streams from communication unit 350.
Reconfiguration mode information can indicate receive bit stream each from controller whether with reconstruct FPGA.
Clauses and subclauses administrative unit 340 is inserted reconfiguration information with reconfiguration mode information, generates to comprise each reconfiguration information and from the bit stream of identifying information, and bit stream and reconstitution time information are transferred to together from communication unit 350.
From communication unit 350 according to reconstitution time information with bit stream transfer to first from controller 102 or second from controller 103.Particularly, if reconstitution time information indicates transmission bit stream immediately, can immediately bit stream be transferred to from controller from 350 of communication units, if indicating, reconstitution time information to can bit stream be transferred to from communication unit 350 by the transmission period of each appointment from 350 of communication units by the transmission period transmission bit stream.
Refer again to Fig. 1, master controller 101 transfers to first from controller 102 with the bit stream that generates.Here, master controller 101 can link to each other from controller 103 from controller 102 with second with first by twin nuclei.Particularly, if second do not receive through master controller 101 from controller 103 and to transfer to first bit stream from controller 102, twin nuclei then can make master controller 101 again the bit stream that generates be transferred to second from controller 103.Therefore, according to one embodiment of present invention, even when master controller 101, first disconnects from any network between the controller 103 from controller 102 and second, also can carry out normal running.
First extracts reconfiguration information from controller 102 from master controller 101 bit streams that receive, according to described reconfiguration information reconstruct FPGA and use the FPGA control servomotor of reconstruct.Hereinafter, describe first structure from controller 102 in detail with reference to Fig. 5.
Fig. 4 is the diagram that how to generate the example of reconfiguration information for the explanation master controller.
With reference to Fig. 4, the reconfiguration information combining unit 320 of master controller 101 receives order from input unit.Reconfiguration information combining unit 320 extracts essential function information according to the order that receives from reconstruct memory cell 330.One or more function informations can be stored in reconstruct library storage unit 330, and reconfiguration information combining unit 320 can be according to prestoring from each order that the user receives function information tabulation that reconstruct FPGA is required.Correspondingly, in case receive order, 320 search of reconfiguration information combining unit are tabulated with the function information that order is complementary, and 330 extract the function information that is included in the tabulation that searches from reconstruct library storage unit, and by generating reconfiguration information in conjunction with function information.
For example, reconstruct library storage unit 330 can be stored and the algorithm function associated information for the treatment of by carrying out from controller, indication receives the function information of the function of data from the transducer that detects servomotor, and the function information of indicating the function of control real electrical machinery operation.Reconfiguration information combining unit 320 receives the function information tabulation that order 1 and search and order 1 are complementary from input unit.Reconfiguration information combining unit 320 confirms that the function information that is included in the function information tabulation is algorithm 1, transducer input 1 and motor-driven 2, and 330 extract each function informations from reconstruct library storage unit.Reconfiguration information combining unit 320 can be by generating in conjunction with the function information that extracts and ordering 1 corresponding reconfiguration information 420.Reconfiguration information combining unit 320 can transfer to clauses and subclauses administrative unit 340 with reconfiguration information 420.
Though master controller 101 is described as by reconfiguration information combining unit 320 being extracted and generating reconfiguration information in conjunction with function information, its also may be reconfiguration information combining unit 320 have wherein prestore corresponding to the reconfiguration information of each order and when receiving particular command, will transfer to clauses and subclauses administrative unit 340 corresponding to the reconfiguration information of particular command.Correspondingly, master controller 101 also can be by not extracting reconfiguration information and described reconfiguration information being transferred to clauses and subclauses administrative unit 340 in conjunction with the particular step of function information.
Fig. 5 is the calcspar of brief description composition first from the functional unit of controller.With reference to Fig. 5, first comprises control unit 510 and reconfiguration unit 520 from controller 102.
Here, although above-mentioned control unit 510 is determined to be reconstructed according to reconfiguration mode information, 510 of control units can determine from the corresponding reconfiguration information of controller whether needs are reconstructed FPGA according to whether comprising in the bit stream with relevant according to another embodiment of the present invention.
In addition, the first dynamic restructuring module 526 makes FPGA be reconstructed according to the control of control unit 510, but is independent of the operation of static reconstructed module 523.That is, whether no matter static reconstructed module 523 is current controls servomotor or is reconstructed, and all can be reconstructed the first dynamic restructuring module 526.
For example, dynamic restructuring module 526 receives the rotary speed of servomotor from the transducer that detects the servomotor rotary speed, and can work as rotary speed and surpass command speed the time, calculates according to the pre-defined algorithm for the servomotor rotary speed.Dynamic restructuring module 523 can transfer to the controlling value as result of calculation static reconstructed module 523.In addition, static reconstructed module 523 can be adjusted rotary speed to a value according to controlling value.
In the example of another reconstruct first dynamic restructuring module 526, the control of supposing servomotor requires to calculate from first sensor, second transducer and the 3rd transducer reception data and by first algorithm successively, and generates the bit stream that is used for this control by master controller 101.In this case, control unit 510 can receive first bit stream from master controller 101.Here, first bit stream comprises that indication FPGA structure is used for the reconfiguration information that receives data and calculate by the first predetermined algorithm from first sensor.Then, the control unit 510 controls first dynamic restructuring module 526 is reconstructed the FPGA structure according to reconfiguration information.Here, static reconstructed module 523 can continue to control servomotor.After finishing reconstruct, the first dynamic restructuring module 526 receives data and exports controlling value from first sensor according to the FPGA structure, the value of this controlling value for calculating by first algorithm.The first dynamic restructuring module 526 is sent to static reconstructed module 523 with controlling value.Static reconstructed module 523 continues to control servomotor according to controlling value.
Afterwards, control unit 510 can receive second bit stream from master controller 101.Here, second bit stream comprises that indication FPGA structure is used for the reconfiguration information that receives data and calculate by first algorithm from second transducer.Then, after above-mentioned steps, the first dynamic restructuring module 526 is reconstituted permission receives data from second transducer FPGA structure.In addition, static reconstructed module 523 continues the control servomotor according to controlling value.
Afterwards, control unit 510 can receive the 3rd bit stream from master controller 101.Here, the 3rd bit stream comprises that indication FPGA structure is used for the reconfiguration information that receives data and calculate by first algorithm from the 3rd transducer.Then, after above-mentioned steps, the first dynamic restructuring module 526 is reconstituted permission receives data from the 3rd transducer FPGA structure.In addition, static reconstructed module 523 continues the control servomotor according to controlling value.
Correspondingly, can receive data from first, second, and third transducer successively.
If receive data from each transducer successively, the routine operation controller then needs the module for each transducer, thereby receives data from each respective sensor, so it has enough big circuit inevitably.But first can use when the control of using static reconstructed module 523 to keep servomotors a dynamic restructuring module 526 receiving data from transducer successively from controller 510, thus the control servomotor.Correspondingly, the size of this control system can be relatively less than the routine operation controller.
Here, the function of static reconstructed module 523 and the first dynamic restructuring module 526 is not limited in content described herein.In other words, the reconfiguration information of the function of static reconstructed module 523 and the first dynamic restructuring module 526 bit stream that can receive according to control unit 510 changes.
The second dynamic restructuring module 529 has the configuration identical with the first dynamic restructuring module 526, and can be reconstructed by the reconstruction step identical with the first dynamic restructuring module 526.
In another embodiment of the present invention, control unit 510 can be according to being reconstructed from the capacity of the reconfiguration information of the bitstream extraction FPGA structure to the first dynamic restructuring module 526 or the second dynamic restructuring module 529.
For example, if supposing that the first dynamic restructuring module 526 is current moves, control unit 510 is reconstructed according to the FPGA of reconfiguration information to the current off-duty second dynamic restructuring module 529 during greater than predetermined volumes at the capacity of reconfiguration information.After reconstruct is finished, the second dynamic restructuring module 529 will be notified the completed reconstruct of reconstruct to finish signal and be sent to control unit 510.Finish signal in case receive reconstruct, control unit 510 will ask the operation of shut-down operation to stop to ask to be sent to the current first dynamic restructuring module of moving 526.The first dynamic restructuring module 526 stops to ask shut-down operation according to operation.Here, the second dynamic restructuring module 529 that wherein according to reconfiguration information the FPGA structure is reconstructed is calculated and result of calculation is sent to static reconstructed module 523.Then, when receiving result of calculation from the second dynamic restructuring module 529, static reconstructed module 523 can be controlled servomotor.
Though above-mentioned control unit 510 is used for determining that whether the capacity of reconfiguration information of the bit stream that receives from master controller 101 is greater than predetermined value, but in another embodiment, can also be the clauses and subclauses administrative unit 340 of master controller 101 determine reconfiguration information capacity whether greater than predetermined value and will determine in the title of corresponding information insertion reconfiguration information with this.Here, control unit 510 can check the information in the title of reconfiguration information and carry out the reconstruction step of the first dynamic restructuring module 526 or the second dynamic restructuring module 529.
Fig. 6 is how to control the flow chart of servomotor operation for the explanation control system.
With reference to Fig. 6, in step 610, master controller 101 receives order from input unit.
In step 620, master controller 101 generates the bit stream that is used for the control servomotor according to the order that receives in step 610.Here, master controller 101 generates and comprises indication from the bit stream of the reconfiguration information of controller FPGA structure, thereby according to order control servomotor.Master controller 101 is sent to first from controller 102 with the bit stream that generates.
In step 630, first from the bitstream extraction reconfiguration information of controller 102 from receiving.Here, after extracting reconfiguration information, first can be sent to bit stream second from controller 103 from controller 102.After step 630 can by with first from the identical mode of controller 102 operate receive bit stream second from controller 103.
In step 640, first from controller 102 according to the structure of reconfiguration information to reconfiguration unit, namely the FPGA module is reconstructed.Here, if the first dynamic restructuring module 526 of the current positive control servomotor in a plurality of dynamic restructuring modules is reconstructed according to reconfiguration information, need stop to control under the situation of servomotor from controller 102 first so, first can the reconstruct second dynamic restructuring module 529 from 102 of controllers.In case the reconstruct of the second dynamic restructuring module 529 is finished, first can be by using the second dynamic restructuring module 529 and static reconstructed module 523 stop the operation of the first dynamic restructuring module 526 and controlling servomotor from controller 102.In addition, first can be according to the reconfiguration information static reconstructed module 523 of reconstruct, the first dynamic restructuring module 526 and the second dynamic restructuring module 529 independently from controller 102.Namely, only show in reconfiguration information under the situation of structure of the first dynamic restructuring module 526 or the second dynamic restructuring module 529, when static reconstructed module 523 was controlled servomotors, first can the reconstruct first dynamic restructuring module 526 or the second dynamic restructuring modules 529 from controller 102.
In step 650, first from the operation of controller 102 by the reconfiguration unit control servomotor of use reconstruct step 640.
Though the control system of having described is the control servomotor, is understood that and is applicable to that by configuration the reconfiguration information of other devices controls other devices except servomotor.
So far, invention has been described according to specific embodiment, but except described embodiment, also has many other embodiment in claim of the present invention.It should be understood that those of ordinary skill in the art can the form with change show the present invention under the prerequisite that does not break away from essential characteristic of the present invention.Correspondingly, the disclosed embodiments should be understood as that illustrative and be nonrestrictive.Scope of the present invention should be by claims but not top explanation and limiting, and any and all variations in equivalent scope all should be understood as that and are included among the scope of the present invention.
Industrial applicability
According to an embodiment of the invention control system and be used for its method can be by each device of control according to user's input reconstruct gate array architecture and neatly.
Control system and the method that is used for it can and use the gate array of reconstruct to control the minimized in size that this device makes control device by the reconstruct gate array architecture according to an embodiment of the invention.
Claims (14)
1. control system that can be reconstructed in operation, described control system comprises:
Master controller, it is configured to generate the bit stream that comprises reconfiguration information according to user's order; And
First from controller,
Wherein, described first comprises from controller:
The first dynamic restructuring module, it is for the FPGA that is reconstructed according to described reconfiguration information and calculate controlling value;
Static reconstructed module, it is the FPGA according to the operation of described controlling value control destination apparatus; And
Control unit, its one or more according in the described first dynamic restructuring module of described reconfiguration information reconstruct and the described static reconstructed module.
2. control system according to claim 1, wherein said control unit can be independent of the operation of described static reconstructed module and the FPGA structure of the described dynamic restructuring module of reconstruct.
3. control system according to claim 1 wherein saidly also comprises the second dynamic restructuring module from controller, and it is for the FPGA that is reconstructed according to described reconfiguration information and calculate controlling value, and
Wherein, when the capacity of described reconfiguration information during greater than predetermined value, described control unit is controlled the described second dynamic restructuring module according to described reconfiguration information makes it by reconstruct, and the operation that keeps the described first dynamic restructuring module is up to finishing described second reconstructed module of reconstruct.
4. control system according to claim 3, wherein, when finishing the described second dynamic restructuring module of reconstruct, described control unit stops the operation of the described first dynamic restructuring module.
5. control system according to claim 1, wherein said master controller comprises:
Reconstruct library storage unit, it stores between the door of the described first dynamic restructuring module of indication or the function information of annexation between the door of described static reconstructed module;
The reconfiguration information combining unit, it extracts described function information according to described order and by generating described reconfiguration information in conjunction with the function information that extracts; And
The clauses and subclauses administrative unit, its generation comprises the bit stream of described reconfiguration information.
6. control system according to claim 5 also comprises from communication unit, and it transfers to described first from controller with described bit stream,
Wherein, if described clauses and subclauses administrative unit generates reconstitution time information according to described order, namely transmit the time of described bit stream, describedly then at each predetermined period or when generating described bit stream according to described reconstitution time information described bit stream is transferred to described first from controller from communication unit.
7. control system according to claim 1 also comprises second from controller, and it is for having the controller of identical configuration with described first from controller,
Wherein said master controller generates described bit stream, and it comprises with described first from controller and described second each corresponding reconfiguration information from controller.
8. control system according to claim 7, wherein said master controller, described first is connected from the twin nuclei of controller by network from controller with described second.
9. control system according to claim 1, wherein under the situation that changes described destination apparatus, the FPGA of described static reconstructed module for being reconstructed according to described reconfiguration information.
10. one kind is used for the Reconfigurable Control system with control destination apparatus method of operating, and described method comprises:
Order according to the user generates the bit stream that comprises reconfiguration information;
Reconstruct primary scene programmable gate array (FPGA), it is reconstructed and calculates controlling value according to described reconfiguration information;
Use the FPGA of described reconstruct to calculate controlling value; And
Described controlling value is transferred to the 2nd FPGA, and it controls the operation of described destination apparatus.
11. method according to claim 10, the reconstruct of a wherein said FPGA is independent of the operation of described the 2nd FPGA.
12. method according to claim 11 also comprises reconstruct the 3rd FPGA, when the capacity of described reconfiguration information during greater than predetermined value, described the 3rd FPGA is reconstructed and calculates controlling value according to described reconfiguration information,
Wherein keep the operation of a described FPGA up to finishing described the 3rd FPGA of reconstruct.
13. method according to claim 12 also comprises when finishing described the 3rd FPGA of reconstruct, stops the operation of a described FPGA.
14. method according to claim 10, the generation of wherein said bit stream comprises:
According to the memory space abstraction function information of described order from described control system, described control system stores between the door of the described FPGA of indication or the described function information of annexation between the door of described the 2nd FPGA;
By generating described reconfiguration information in conjunction with the function information that extracts; And
Generation comprises the bit stream of described reconfiguration information.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020100103627A KR101259133B1 (en) | 2009-11-11 | 2010-10-22 | Reconfigurable control system during operation and method there of |
| KR10-2010-0103627 | 2010-10-22 | ||
| PCT/KR2010/007795 WO2012053687A1 (en) | 2010-10-22 | 2010-11-05 | Control system that is reconfigurable during operation, and method therefor |
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| CN103262405A true CN103262405A (en) | 2013-08-21 |
| CN103262405B CN103262405B (en) | 2016-03-23 |
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| CN201080069761.2A Active CN103262405B (en) | 2010-10-22 | 2010-11-05 | The control system that can reconstruct in operation and for its method |
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| Country | Link |
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| JP (1) | JP5646764B2 (en) |
| CN (1) | CN103262405B (en) |
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Also Published As
| Publication number | Publication date |
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| JP5646764B2 (en) | 2014-12-24 |
| CN103262405B (en) | 2016-03-23 |
| WO2012053687A1 (en) | 2012-04-26 |
| DE112010005955T5 (en) | 2013-08-01 |
| JP2014500644A (en) | 2014-01-09 |
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