CN109918321B - PCIe bus-based online reconstruction method - Google Patents
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Abstract
The invention discloses an online reconstruction method based on PCIe bus, comprising the following steps: s1: the FPGA receives a general description file of the reconstructed file through a PCIe bus and stores the general description file, wherein the general description file is used for recording a general logic relation between analysis blocks in the reconstructed file; s2: the FPGA receives an analysis block message of the reconstructed file through a PCIe bus, and analyzes and stores PCIe bus data of each frame of the analysis block message; s3: after the FPGA finishes analyzing one frame of PCIe bus data, each analysis block in the currently analyzed frame of PCIe bus data is subjected to online reconstruction logic operation processing to obtain a processing result of the analysis block until each frame of PCIe bus data of an analysis block message is processed; s4: and the FPGA analyzes the total logic relationship among the analysis blocks and the processing result of each analysis block to obtain the online reconfiguration logic. The invention has the technical characteristics of simple structure, quick response, high-speed bus online reconstruction, simplicity and convenience.
Description
Technical Field
The invention belongs to the technical field of industrial control automation, and particularly relates to an online reconstruction method based on a PCIe bus.
Background
With the development of industrial control technology, the control task and environment change continuously, and the controller has great requirements on the characteristics of universality, reliability, instantaneity, flexibility, expandability and the like. Industrial ethernet technology and field buses are widely used in the fields of industrial automation, ship automation, and vehicle automation. Most of traditional methods adopt industrial Ethernet technology or field bus technology to carry out on-line reconstruction on a controller, and the specific scheme is that a microprocessor and FPGA architecture is used for realizing the on-line reconstruction of the industrial controller. The FPGA mainly completes interface and time sequence control, and the microprocessor mainly completes flow control, complex algorithm and online reconstruction. The layout and wiring of the main processing chip of the card and the data interaction process are relatively complex. The microprocessor adopts an embedded system, a large number of interrupt registers are required to be arranged when multitask management is carried out, task scheduling is not flexible, and instantaneity is poor. The architecture and the bus technology are adopted to realize the online reconstruction of the industrial controller, the real-time performance of the industrial controller is low, the processing response time is long, and the data transmission frequency is low.
Disclosure of Invention
The technical purpose of the invention is to provide an online reconstruction method based on PCIe bus, which has the technical characteristics of simple structure, quick response, online reconstruction of high-speed bus, simplicity and convenience.
In order to solve the problems, the technical scheme of the invention is as follows:
an online reconstruction method based on PCIe bus comprises the following steps:
s1: the FPGA receives a general description file of the reconstructed file through the PCIe bus and stores the general description file, wherein the general description file is used for recording a general logic relation between analysis blocks in the reconstructed file;
s2: the FPGA receives an analysis block message of the reconstructed file through the PCIe bus, and analyzes and stores PCIe bus data of each frame of the analysis block message;
s3: after the FPGA finishes analyzing one frame of the PCIe bus data, each analysis block in the current analyzed frame of the PCIe bus data is subjected to online reconstruction logic operation processing to obtain a processing result of the analysis block until each frame of the PCIe bus data of the analysis block message is processed, wherein the analysis block comprises a common analysis block and an output analysis block;
s4: and the FPGA analyzes the total logic relationship among the analysis blocks and the processing result of each analysis block to obtain an online reconfiguration logic.
According to an embodiment of the present invention, the on-line reconfiguration logical operation processing is:
a1: if the analysis block is the common analysis block, performing the following analysis:
if the number of lines of the common analysis block is greater than 1, performing logical AND operation on each element in the series relation of each line of the common analysis block to obtain an analysis result of the series relation of each line, and performing logical OR operation on the analysis results corresponding to the series relation of each line to obtain a processing result of the common analysis block;
if the line number of the common analysis block is equal to 1, performing logical AND operation on each element of the common analysis block to obtain a processing result of the common analysis block;
a2: if the analysis block is the output analysis block, performing the following analysis:
if the output line number of the output analysis block is larger than 1, establishing a recording mark shared by multiple lines of the output analysis block, and outputting a result by each line of the output analysis block according to the recording mark;
and if the output line number of the output analysis block is equal to 1, directly outputting the result.
According to an embodiment of the present invention, the step S4 includes the following steps:
the FPGA scans the types of the analysis blocks:
if the analysis block is the output analysis block, directly outputting a result;
if the analysis blocks are the common analysis blocks, substituting the processing results of the analysis blocks into the total logical relationship among the analysis blocks to execute: if the analysis blocks are in a serial relation, executing logic and operation; and if the analysis blocks are in parallel relation, executing logic OR operation.
According to an embodiment of the present invention, the types of the reconstructed file include a ladder diagram, a function block diagram, a sequential function diagram, a structured text, and an instruction list.
According to an embodiment of the present invention, the step S1 is preceded by a step B1, and the step B1 includes the following steps:
b11: initializing the FPGA and reading the reconstructed data stored last time;
b12: and the FPGA receives the online reconstructed control instruction through the PCIe bus.
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages and positive effects:
the invention reliably transmits the reconstruction file in a PCIe bus mode at high speed through a system structure of a single FPGA without a peripheral microprocessor or a DSP device, separately stores and processes the reconstruction file according to blocks, simultaneously adopts a high-speed parallel flexible processing mechanism of the FPGA to perform high-speed parallel logic reconstruction logic operation processing on each analysis block in the reconstruction file, and receives data to be reconstructed on line by a PCIe high-speed bus, thereby solving the technical problems of inflexible data transmission mode, weak real-time property, poor reliability and low transmission rate of the current industrial controller, and achieving the technical effects of simple structure, quick response, online reconstruction of the high-speed bus, simplicity and convenience.
Drawings
Fig. 1 is a main flow diagram of an online reconfiguration method based on PCIe bus according to the present invention;
fig. 2 is a schematic diagram illustrating an online reconfiguration logical operation process of the online reconfiguration method based on the PCIe bus according to the present invention.
Detailed Description
The PCIe bus-based online reconfiguration method proposed in the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims.
Referring to fig. 1, the present embodiment provides an online reconfiguration method based on PCIe bus, including the following steps:
s1: the FPGA receives a general description file of the reconstructed file through a PCIe bus and stores the general description file, wherein the general description file is used for recording a general logic relation between analysis blocks in the reconstructed file;
s2: the FPGA receives an analysis block message of the reconstructed file through a PCIe bus, and analyzes and stores PCIe bus data of each frame of the analysis block message;
s3: after the FPGA finishes analyzing one frame of PCIe bus data, each analysis block in the currently analyzed frame of PCIe bus data is subjected to online reconstruction logic operation processing to obtain a processing result of the analysis block until each frame of PCIe bus data of an analysis block message is processed, wherein the analysis block comprises a common analysis block and an output analysis block;
s4: and the FPGA analyzes the total logic relationship among the analysis blocks and the processing result of each analysis block to obtain the online reconfiguration logic.
Referring to fig. 1, the present embodiment will now be described in detail:
the FPGA chip in the embodiment adopts a Kintex-7 series device of Xilinx, takes the FPGA chip as a core, has no peripheral DSP or is a scheme framework of a microprocessor device, and simultaneously completes main interface time sequence bus and online reconstruction logic processing by the FPGA. The data memory in this embodiment is a non-power-down data memory, and may be other memories.
The reconstruction file of the embodiment is an IEC61131-3 ladder diagram compiling file generated by the controller programming software. Likewise, the type of the reconstructed file can also be a function block diagram, a sequential function diagram, a structured text, and an instruction list.
In the embodiment, the ladder diagram compiling file is reliably transmitted at a high speed in a PCIe bus mode, the received IEC61131-3 ladder diagram compiling file is separately and independently stored and processed according to the analysis blocks, and meanwhile, a high-speed parallel flexible processing mechanism of an FPGA is adopted to perform high-speed parallel processing on each analysis block in the processed ladder diagram compiling file, so that high-speed control and online reconstruction control of an industrial controller are realized.
Specifically, step S1 is preceded by step B1, and step B1 includes the following steps: b11: initializing the FPGA and reading the reconstructed data stored last time; b12: and the FPGA receives the online reconstructed control instruction through a PCIe bus.
Specifically, in step B1, the apparatus is powered on, the FPGA device reads the code program from the configuration memory for analysis and execution, the FPGA device reads the last saved reconstructed data from the non-power-down data memory, the FPGA starts PCIe bus communication, sends a control instruction that the FPGA has completed initialization to the FPGA bus, and can start PCIe bus communication, if the FPGA receives an online reconstructed control instruction via the PCIe bus, the online reconstruction based on the PCIe bus is started, and if a corresponding instruction is not received, the reconstructed data read from the external non-power-down memory last time is used.
Specifically, in step S1, after the online reconfiguration is started, the compiled IEC61131-3 ladder diagram file is sent in a high-speed, bidirectional, point-to-point, high-reliability, and anti-interference PCIe bus manner. Firstly, a general description for a file to be reconstructed online is transmitted, namely, the IEC61131-1 ladder diagram compiling file is composed of a number of analysis blocks and a series-parallel relation among the analysis blocks, and the general description is used for substituting the results of other analysis blocks into a logic relation among the general analysis blocks after the FPGA analyzes the results to obtain a final online reconstruction logic operation result. The FPGA places the general description of the file to be reconstructed online in a certain block area of the running memory and an external non-power-down memory.
Specifically, in step S2, the analysis block message in the IEC61131-1 ladder compilation file is continuously transmitted in the PCIe bus manner according to the customized transmission format, each frame of PCIe bus data received is analyzed, and the FPGA places the analysis block message in a certain block area of the operating memory and the external non-power-down memory.
Specifically, in step S3, it is determined whether the IEC61131-1 ladder compilation file is completely transmitted, and if not, the FPGA continues to receive the PCIe bus data of the next frame and process the message data, and the FPGA chip starts the online reconfiguration logical operation processing of the PCIe bus data of the last frame that is completely processed; if the transfer is complete, the next step is performed.
Specifically, referring to fig. 2, the on-line reconstruction logic operation process is:
a1: if the analysis block is a normal analysis block, performing the following analysis: if the number of lines of the common analysis block is larger than 1, performing logical AND operation on each element in the series relation of each line of the common analysis block to obtain an analysis result of the series relation of each line, and performing logical OR operation on the analysis results corresponding to the series relation of each line to obtain a processing result of the common analysis block; if the line number of the common analysis block is equal to 1, performing logical AND operation on each element of the common analysis block to obtain a processing result of the common analysis block;
a2: if the analysis block is an output analysis block, performing the following analysis: if the output line number of the output analysis block is larger than 1, establishing a multi-line shared recording mark of the output analysis block, and outputting a result according to the recording mark by each line of the output analysis block; and if the output line number of the output analysis block is equal to 1, directly outputting the result.
Specifically, in step S4, if the total number of analysis blocks included in the IEC61131-1 ladder diagram compilation file is large, multiple PCIe bus transmissions are required, and multiple on-line reconstruction logic operation processes are performed to complete the analysis processing of each analysis block until the PCIe bus transmissions complete all analysis block messages and the FPGA chip processes all analysis blocks to complete logic analysis in all analysis blocks. After the FPGA completes the analysis of each analysis block in the IEC61131-1 ladder diagram compilation file, the analysis blocks are combined with the total logic relation among the analysis blocks, and the FPGA analyzes the final on-line reconstruction logic and stores the final on-line reconstruction logic into a memory.
Specifically, step S4 includes the steps of:
PGA scans the type of each analysis block: if the analysis block is an output analysis block, directly outputting a result; if the analysis blocks are common analysis blocks, substituting the processing results of the analysis blocks into the total logical relationship among the analysis blocks to execute: if the analysis blocks are in a serial relation, executing logic and operation; and if the analysis blocks are in parallel relation, executing logic or operation.
The embodiment has the following technical effects:
in view of the shortcomings of the prior art, the present embodiment provides an online reconfiguration method based on PCIe bus. Under the system structure of a single-chip FPGA and the solution without a peripheral microprocessor or a DSP device, the system overcomes the defects of low data transmission frequency, long control response time, weak real-time performance, complex comprehensive processing process and the like of the existing industrial control field bus. The technology for the industrial controller to analyze the IEC61131-1 ladder diagram on line at a high speed for high-speed reconstruction is realized, the advantages of high universality, reliability, real-time performance, flexibility and expandable characteristics are further improved, the size of the controller is further reduced, and the complexity of a scheme is reduced.
According to the embodiment, through a system structure of a single FPGA, a peripheral microprocessor or a DSP device is not provided, a reconstructed file is reliably transmitted in a PCIe bus mode at a high speed, the reconstructed file is separately stored and processed according to blocks, meanwhile, a high-speed parallel flexible processing mechanism of the FPGA is adopted, high-speed parallel logic reconstruction logic operation processing is carried out on each analysis block in the reconstructed file, meanwhile, data to be reconstructed is received on line through a PCIe high-speed bus, the technical problems that the data transmission mode of the existing industrial controller is inflexible, the real-time performance is weak, the reliability is poor and the transmission rate is low are solved, and the technical effects of simple structure, quick response, high-speed bus on-line reconstruction, simplicity and convenience are achieved.
The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments. Even if various changes are made to the present invention, it is still within the scope of the present invention if they fall within the scope of the claims of the present invention and their equivalents.
Claims (5)
1. An online reconfiguration method based on PCIe bus is characterized by comprising the following steps:
s1: the FPGA receives a general description file of a reconstructed file through the PCIe bus and stores the general description file, wherein the general description file is used for recording a general logic relation between analysis blocks in the reconstructed file;
s2: the FPGA receives an analysis block message of the reconstructed file through the PCIe bus, and analyzes and stores PCIe bus data of each frame of the analysis block message;
s3: after the FPGA finishes analyzing one frame of the PCIe bus data, each analysis block in the current analyzed frame of the PCIe bus data is subjected to online reconstruction logic operation processing to obtain a processing result of the analysis block until each frame of the PCIe bus data of the analysis block message is processed, wherein the analysis block comprises a common analysis block and an output analysis block;
s4: and the FPGA analyzes the total logic relationship among the analysis blocks and the processing result of each analysis block to obtain an online reconfiguration logic.
2. The PCIe bus based on-line reconfiguration method according to claim 1, wherein the on-line reconfiguration logical operation process is:
a1: if the analysis block is the common analysis block, performing the following analysis:
if the number of lines of the common analysis block is greater than 1, performing logical AND operation on each element in the series relation of each line of the common analysis block to obtain an analysis result of the series relation of each line, and performing logical OR operation on the analysis results corresponding to the series relation of each line to obtain a processing result of the common analysis block;
if the line number of the common analysis block is equal to 1, performing logical AND operation on each element of the common analysis block to obtain a processing result of the common analysis block;
a2: if the analysis block is the output analysis block, performing the following analysis:
if the output line number of the output analysis block is larger than 1, establishing a recording mark shared by multiple lines of the output analysis block, and outputting a result by each line of the output analysis block according to the recording mark;
and if the output line number of the output analysis block is equal to 1, directly outputting the result.
3. The PCIe bus-based online reconfiguration method according to claim 1 or 2, wherein said step S4 comprises the steps of:
the FPGA scans the types of the analysis blocks:
if the analysis block is the output analysis block, directly outputting a result;
if the analysis blocks are the common analysis blocks, substituting the processing results of the analysis blocks into the total logical relationship among the analysis blocks to execute: if the analysis blocks are in a serial relation, executing logic and operation; and if the analysis blocks are in parallel relation, executing logic OR operation.
4. The PCIe bus based on-line reconstruction method according to claim 3, wherein the type of the reconstructed file comprises ladder diagram, function block diagram, sequential function diagram, structured text, instruction list.
5. The PCIe bus based on-line reconstruction method according to claim 3, wherein the step S1 is further preceded by a step B1, and the step B1 comprises the steps of:
b11: initializing the FPGA and reading the reconstructed data stored last time;
b12: and the FPGA receives the online reconstructed control instruction through the PCIe bus.
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