CN111078611A - PLC high-speed backplate bus based on FPGA - Google Patents
PLC high-speed backplate bus based on FPGA Download PDFInfo
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- CN111078611A CN111078611A CN201911306737.5A CN201911306737A CN111078611A CN 111078611 A CN111078611 A CN 111078611A CN 201911306737 A CN201911306737 A CN 201911306737A CN 111078611 A CN111078611 A CN 111078611A
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- 230000006854 communication Effects 0.000 claims description 29
- 238000004891 communication Methods 0.000 claims description 27
- 238000003745 diagnosis Methods 0.000 claims description 15
- 238000012790 confirmation Methods 0.000 claims description 14
- 230000002159 abnormal effect Effects 0.000 claims description 12
- 238000012545 processing Methods 0.000 claims description 5
- 230000005540 biological transmission Effects 0.000 abstract description 14
- 230000005855 radiation Effects 0.000 abstract description 5
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention discloses a PLC high-speed backboard bus based on an FPGA, which comprises a CPU module and a high-speed backboard bus, wherein the CPU module and the high-speed backboard bus are in bidirectional connection through a wire. The PLC high-speed backboard bus based on the FPGA is connected with the input end of a PCI express interface through the output end of the high-speed backboard bus, the output end of the PCI express interface is connected with the output end of an IO module, a CPU module comprises a CPU processor, an FPGA chip, a storage module and a system cutting module, bidirectional connection is realized between the CPU processor and the FPGA chip, bidirectional connection is realized between the CPU processor and the storage module, point-to-point and point-to-multipoint data transmission is realized by utilizing the PCI express interface, data transmission is carried out by adopting an LVDS interface, the highest speed can reach 48Mbit/s, the high-speed backboard bus has the characteristics of low power consumption, low error rate, low crosstalk and low radiation, and the output transmission efficiency of the high-speed backboard bus is greatly improved.
Description
Technical Field
The invention relates to the technical field of high-speed backboard buses, in particular to a PLC high-speed backboard bus based on an FPGA.
Background
With the rapid development and the increasing popularization of electronic technology, computer technology, communication network control technology and industrial automation control technology, in the field of industrial control systems, the functions of Programmable Logic Controllers (PLC) born in the last 60 th century are increasingly powerful, the traditional single-machine PLC control/network communication is developed towards networked large-scale PLC systems, and the application requirements of large-scale PLC systems of more than ten thousand points are met in the fields of rail transit, petrifaction and the like.
The realization of the PLC backplane bus is a technical difficulty of the development of the PLC system toward the large scale, the PLC system usually adopts the conventional serial communication technology to realize the backplane bus, the serial communication technology CAN improve the reliability of the automation device in the harsh factory and industrial environment, the conventional serial communication technology includes CAN, I2C, UART, SPI, USB, ethernet, etc., generally, many processors as the main chips of the PLC system integrate these peripheral components, but the communication rate of the peripheral integrated IC, UART, SPI, etc. inside the processors is too slow to meet the communication rate requirement of the backplane bus, the communication speed of the USB and ethernet is fast, but because they are all universal interfaces, the intervention of the processors is required during the communication protocol processing, the processing speed of the processors is slow, so the overall communication speed is still slow, and the error rate is high in the communication processing process of the backplane bus, and higher crosstalk and radiation exist, and communication cannot be processed in time when abnormality occurs in the communication process, so that data transmission fails.
Disclosure of Invention
Technical problem to be solved
Aiming at the defects of the prior art, the invention provides a PLC high-speed backplane bus based on an FPGA, which solves the problems that the conventional high-speed backplane bus cannot meet the communication speed requirement of a backplane bus, in addition, the error rate is higher in the process of carrying out communication processing on the backplane bus, higher crosstalk and radiation exist, and communication cannot be processed in time when an abnormality occurs in the communication process, so that the data transmission fails.
(II) technical scheme
In order to achieve the purpose, the invention is realized by the following technical scheme: the utility model provides a PLC high-speed backplate bus based on FPGA, includes CPU module and high-speed backplate bus, realize two-way connection through the wire between CPU module and the high-speed backplate bus, the output of high-speed backplate bus is connected with the input of PCI express interface to the output of PCI express interface is connected with the output of IO module, the CPU module includes that CPU treater, FPGA chip, storage module and system decide the module, realize two-way connection between CPU treater and the FPGA chip to realize two-way connection between CPU treater and the storage module, realize two-way connection between CPU treater and the system decide the module, and the output of CPU treater is connected with the input of high-speed backplate bus.
Preferably, the system cutting module comprises a system diagnosis module, an abnormality confirmation module and an abnormality interruption module.
Preferably, the input end of the system diagnosis module is connected with the output end of the CPU processor, the output end of the abnormal interruption module is connected with the input end of the CPU processor, the output end of the system diagnosis module is connected with the input end of the abnormal confirmation module, and the output end of the abnormal confirmation module is connected with the input end of the abnormal interruption module.
Preferably, the high-speed backplane bus comprises an LVDS interface, and an input end of the LVDS interface is connected to an output end of the CPU module.
Preferably, the FPGA chip includes a configurable logic module, an input/output module, and an internal connection module.
Preferably, the CPU processor adopts a dual-core ARMCortex-A9 processor, and the FPGA chip adopts one of a Virtex-5 series XC5VLX110T model chip and a Zynq-7000 series XC7Z045 model chip of Xilinx.
Preferably, the high speed backplane bus supports dynamic communication protocols, and new communication protocol support is added by downloading a new communication protocol IP core on the operating system.
Preferably, the output end of the high-speed backplane bus is connected with 64I 0 modules at most through a pci express interface.
(III) advantageous effects
The invention provides a PLC high-speed backboard bus based on an FPGA. Compared with the prior art, the method has the following beneficial effects:
(1) the PLC high-speed backboard bus based on the FPGA is connected with the input end of a PCI express interface through the output end of the high-speed backboard bus, the output end of the PCI express interface is connected with the output end of an IO module, a CPU module comprises a CPU processor, an FPGA chip, a storage module and a system cutting module, the CPU processor is in bidirectional connection with the FPGA chip, the CPU processor is in bidirectional connection with the storage module, the CPU processor is in bidirectional connection with the system cutting module, the output end of the CPU processor is connected with the input end of the high-speed backboard bus, the high-speed backboard bus comprises an LVDS interface, the input end of the LVDS interface is connected with the output end of the CPU module, point-to-point and point-to-multipoint data transmission is realized by the PCI express interface, the LVDS interface is used for data transmission, the highest speed can reach 48Mbit/s, and the high-speed backboard bus has low power consumption, The low bit error rate, low crosstalk and low radiation characteristics, and the output transmission efficiency of the high-speed backplane bus is greatly improved.
(2) The PLC high-speed backboard bus based on the FPGA is connected with the input end of a PCI express interface through the output end of the high-speed backboard bus, the output end of the PCI express interface is connected with the output end of an IO module, a CPU module comprises a CPU processor, an FPGA chip, a storage module and a system cutting module, the CPU processor is bidirectionally connected with the FPGA chip, the CPU processor is bidirectionally connected with the storage module, the CPU processor is bidirectionally connected with the system cutting module, the output end of the CPU processor is connected with the input end of the high-speed backboard bus, the system cutting module comprises a system diagnosis module, an abnormity confirmation module and an abnormity interruption module, the input end of the system diagnosis module is connected with the output end of the CPU processor, the output end of the abnormity interruption module is connected with the input end of the CPU processor, the output end of the system diagnosis module is connected with the input end of the abnormity confirmation module, and the output end of the abnormal confirmation module is connected with the input end of the abnormal interruption module, the system cutting module arranged in the CPU module can be used for diagnosing each module in real time, and the data transmission can be interrupted in time when a fault is found, so that the transmitted data is protected.
(3) The PLC high-speed backboard bus based on the FPGA comprises a configurable logic module, an output/input module and an internal connection module through an FPGA chip, wherein a CPU processor adopts a dual-core ARMCortex-A9 processor, the FPGA chip adopts one of a Virtex-5 series XC5VLX110T model chip and a Zynq-7000 series XC7Z045 model chip of Xilinx, the high-speed backboard bus supports a dynamic communication protocol, a new communication protocol IP core is downloaded on an operating system to add new communication protocol support, the output end of the high-speed backboard bus is connected with 64I 0 modules at most through a PCIxpress interface, when power is applied, the FPGA chip reads data in an EPROM into an on-chip programming RAM, after configuration is completed, the FPGA enters a working state, after power failure, the FPGA recovers to a white chip, the internal logic relation disappears, the FPGA chip is repeatedly used, and the flexibility is high.
Drawings
FIG. 1 is a schematic block diagram of the architecture of the system of the present invention;
FIG. 2 is a schematic block diagram of the CPU module of the present invention;
FIG. 3 is a schematic block diagram of the structure of the cutting module of the system of the present invention;
FIG. 4 is a schematic block diagram of the architecture of the high speed backplane bus of the present invention;
FIG. 5 is a schematic block diagram of the FPGA chip of the present invention.
In the figure, 1-CPU module, 11-CPU processor, 12-FPGA chip, 121-configurable logic module, 122-output/input module, 123-internal connection module, 13-storage module, 14-system cutting module, 141-system diagnosis module, 142-abnormity confirmation module, 143-abnormity interruption module, 2-high speed backboard bus, 21-LVDS interface, 3-PCIExpress interface and 4-IO module.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1-5, an embodiment of the present invention provides a technical solution: a PLC high-speed backboard bus based on FPGA comprises a CPU module 1 and a high-speed backboard bus 2, the output end of the high-speed backboard bus 2 is connected with 64 IO modules 4 at most through a PCI express interface 3, a CPU processor 11 adopts a dual-core ARMCortex-A9 processor, an FPGA chip 12 adopts one of a Virtex-5 series XC5VLX110T model chip and a Zynq-7000 series XC7Z045 model chip of Xilinx, the high-speed backboard bus 2 supports a dynamic communication protocol, a new communication protocol support is added by downloading a new communication protocol IP core on an operating system, the high-speed backboard bus 2 comprises an LVDS interface 21, the input end of the LVDS interface 21 is connected with the output end of the CPU module 1, the CPU module 1 is bidirectionally connected with the high-speed backboard bus 2 through a lead, the output end of the high-speed backboard bus 2 is connected with the input end of the LVDS interface 3, and the output end of the PCI express interface 3 is connected with the output end of the IO module 4, the CPU module 1 comprises a CPU processor 11, an FPGA chip 12, a storage module 13 and a system cutting module 14, the FPGA chip 12 comprises a configurable logic module 121, an output-input module 122 and an internal connection module 123, the FPGA sets the working state of the FPGA by a program stored in an on-chip RAM, therefore, the RAM in the on-chip RAM needs to be programmed during working, a user can adopt different programming modes according to different configuration modes, the FPGA chip reads data in an EPROM into the on-chip programming RAM when the FPGA is powered on, the FPGA enters the working state after the configuration is finished, the FPGA is recovered to be a white chip after the power failure, the internal logic relation disappears, therefore, the FPGA can be repeatedly used, the FPGA programming does not need a special FPGA programmer, the PROM only needs a universal EPROM and the programmer, when the FPGA function needs to be modified, only one EPROM needs to be replaced, thus, different programming data of the same FPGA can generate different circuit functions, the system cutting module 14 is very flexible to use, and comprises a system diagnosis module 141, an abnormality confirmation module 142 and an abnormality interruption module 143, wherein the input end of the system diagnosis module 141 is connected with the output end of the CPU processor 11, and the output terminal of the exception interrupt module 143 is connected to the input terminal of the CPU processor 11, the output terminal of the system diagnosis module 141 is connected to the input terminal of the exception confirmation module 142, and the output end of the abnormal confirmation module 142 is connected with the input end of the abnormal interruption module 143, the CPU processor 11 and the FPGA chip 12 are connected in both directions, and the CPU processor 11 and the memory module 13 realize bidirectional connection, the CPU processor 11 and the system cutting module 14 realize bidirectional connection, and the output of the CPU processor 11 is connected to the input of the high-speed backplane bus 2, while those not described in detail in this specification are well known in the art.
During operation, the FPGA chip 12 arranged in the CPU module 1 is used for improving the integration level and reliability of the system, when the high-speed backplane bus 2 is used for data transmission, point-to-point and point-to-multipoint data transmission can be realized through the PCI express interface 3, the data transmission is carried out through the LVDS interface in the high-speed backplane bus 2, the highest speed can reach 48Mbit/s, and the high-speed backplane bus 2 has the characteristics of low power consumption, low error rate, low crosstalk and low radiation, so that the output transmission efficiency of the high-speed backplane bus 2 is greatly improved, the system cutting module 14 arranged in the CPU module 1 is used, the system diagnosis module 141 in the system cutting module 14 is used for carrying out real-time diagnosis on each module, the abnormity is determined through the abnormity confirmation module 142, and the data transmission is interrupted in time through the abnormity interruption module 143 when a fault is found, the method plays a good role in protecting the transmitted data.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (8)
1. The utility model provides a high-speed backplate bus of PLC based on FPGA, includes CPU module (1) and high-speed backplate bus (2), realize two-way connection, its characterized in that through the wire between CPU module (1) and high-speed backplate bus (2): the output end of the high-speed backplane bus (2) is connected with the input end of the PCI express interface (3), the output end of the PCI express interface (3) is connected with the output end of the IO module (4), the CPU module (1) comprises a CPU (central processing unit) processor (11), an FPGA (field programmable gate array) chip (12), a storage module (13) and a system cutting module (14), the CPU processor (11) and the FPGA chip (12) are connected in a bidirectional mode, the CPU processor (11) and the storage module (13) are connected in a bidirectional mode, the CPU processor (11) and the system cutting module (14) are connected in a bidirectional mode, and the output end of the CPU processor (11) is connected with the input end of the high-speed backplane bus (2).
2. The PLC high-speed backplane bus based on the FPGA of claim 1, wherein: the system cutting module (14) comprises a system diagnosis module (141), an abnormity confirmation module (142) and an abnormity interruption module (143).
3. The PLC high-speed backplane bus based on the FPGA of claim 2, wherein: the input end of the system diagnosis module (141) is connected with the output end of the CPU processor (11), the output end of the abnormal interruption module (143) is connected with the input end of the CPU processor (11), the output end of the system diagnosis module (141) is connected with the input end of the abnormal confirmation module (142), and the output end of the abnormal confirmation module (142) is connected with the input end of the abnormal interruption module (143).
4. The PLC high-speed backplane bus based on the FPGA of claim 1, wherein: the high-speed backplane bus (2) comprises an LVDS interface (21), and the input end of the LVDS interface (21) is connected with the output end of the CPU module (1).
5. The PLC high-speed backplane bus based on the FPGA of claim 1, wherein: the FPGA chip (12) comprises a configurable logic module (121), an output-input module (122) and an internal wiring module (123).
6. The PLC high-speed backplane bus based on the FPGA of claim 1, wherein: the CPU processor (11) adopts a dual-core ARMCortex-A9 processor, and the FPGA chip (12) adopts one of Xilinx Virtex-5 series XC5VLX110T type chips and Zynq-7000 series XC7Z045 type chips.
7. The PLC high-speed backplane bus based on the FPGA of claim 1, wherein: the high speed backplane bus (2) supports dynamic communication protocols, adding new communication protocol support by downloading new communication protocol IP cores on the operating system.
8. The PLC high-speed backplane bus based on the FPGA of claim 1, wherein: the output end of the high-speed backboard bus (2) is connected with 64 IO modules (4) at most through a PCI express interface (3).
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| Application Number | Priority Date | Filing Date | Title |
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| CN201911306737.5A CN111078611A (en) | 2019-12-17 | 2019-12-17 | PLC high-speed backplate bus based on FPGA |
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| CN201911306737.5A CN111078611A (en) | 2019-12-17 | 2019-12-17 | PLC high-speed backplate bus based on FPGA |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114338273A (en) * | 2021-12-30 | 2022-04-12 | 上海钜成锐讯科技有限公司 | PROFIBUS-DP slave station control system based on FPGA |
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Application publication date: 20200428 |