CN106528474A - RapidIO and PCI-E (Peripheral Component Interconnect-Express) interconnection system constructed on the basis of bridging chip - Google Patents
RapidIO and PCI-E (Peripheral Component Interconnect-Express) interconnection system constructed on the basis of bridging chip Download PDFInfo
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- CN106528474A CN106528474A CN201610947059.0A CN201610947059A CN106528474A CN 106528474 A CN106528474 A CN 106528474A CN 201610947059 A CN201610947059 A CN 201610947059A CN 106528474 A CN106528474 A CN 106528474A
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- chip
- tsi721
- bridging
- pci
- rapidio
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4009—Coupling between buses with data restructuring
- G06F13/4018—Coupling between buses with data restructuring with data-width conversion
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
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- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Mobile Radio Communication Systems (AREA)
Abstract
The invention discloses a RapidIO and PCI-E (Peripheral Component Interconnect-Express) interconnection system constructed on the basis of a bridging chip. The system comprises a main control panel, a switching board, a signal processing board and a radio frequency board, wherein the main control panel, the switching board, the signal processing board and the radio frequency board are connected in sequence; the main control panel comprises a domestic CPU (Central Processing Unit) chip, a configuration circuit, a memory, an RS232 interface, a JTAG (Joint Test Action Group) interface, a power conversion module, a clock processing module, a reset chip, a Tsi721 type bridging chip, a network chip and a bus, wherein the configuration circuit, the memory, the RS232 interface, the JTAG interface, the power conversion module, the clock processing module, the reset chip, the Tsi721 type bridging chip and the network chip are all connected with the domestic CPU chip; and the power conversion module, the clock processing module, the reset chip, the Tsi721 type bridging chip and the network chip are all connected with the bus. By use of the system, the domestic CPU chip Loongson 2H can be used, and the import substitution rate of a core component is improved.
Description
Technical field
The present invention relates to a kind of interacted system, more particularly to a kind of mutual based on bridging chip structure RapidIO and PCI-E
Contact system.
Background technology
Intel just proposes PCI Express concepts early in December, 2000, is initially in commercial PC, some require more
The application of high bandwidth and design, it grows up on the basis of PCI, is mainly used in business computing market, due to it
Many performances of Modern Communication System requirement are met (such as direct peer-to-peer communicationss, type service, multicast support, message transmission
Agreement and topological flexibility) in terms of there is inborn error to a certain degree, the RapidIO technologies competed with which are embedded logical
News field has more advantage.RapidIO be take the lead in advocating by companies such as Motorola and Mercury a kind of high-performance, low pin
Number, the interconnection architecture based on packet-switching, are for meeting high performance embedded system demand and one kind for designing is open
Formula interconnection technique standard.RapidIO is mainly used in embedded system intraconnection, supports chip to chip, plate between plate
Communication, can connect as the backboard of embedded device.
On the novel radio radio station of research and development, the domestic cpu chip Loongson 2H of PCI-E EBIs are supported not
RapidIO technologies are supported, it is designed as being mainly directed towards the mobile processors such as mobile terminal, notebook computer, panel computer, in order to
The core devices localization rate of parts and components is improved, needs mutually to merge this kind of legacy equipment and new RapidIO architectural frameworks, built a set of
Complete interacted system.
The content of the invention
The technical problem to be solved is to provide a kind of based on bridging chip structure RapidIO and PCI-E interconnections
System, its present invention can use domestic cpu chip Loongson 2H, improve the localization rate of parts and components of core devices.
The present invention is solving above-mentioned technical problem by following technical proposals：It is a kind of to be built based on bridging chip
RapidIO and PCI-E interacted systems, it is characterised in that master control borad which includes being sequentially connected, power board, signal-processing board and
Rf board；
Master control borad includes domestic cpu chip, configuration circuit, memorizer, RS232 interfaces, jtag interface, Power convert mould
Block, clock processing module, reset chip, Tsi721 type bridging chips, network chip, bus, configuration circuit, memorizer, RS232
Interface, jtag interface, power transfer module, clock processing module, reset chip, Tsi721 type bridging chips, network chip are all
It is connected with domestic cpu chip, power transfer module, clock processing module, reset chip, Tsi721 type bridging chips, network core
Piece is all connected with bus；
Power board include backplane interface, security module, Tsi578 type exchange chips, audio coding decoding chip, vocoder,
Fpga chip, volume control module, backplane interface, security module, Tsi578 type exchange chips, audio coding decoding chip, acoustic code
Device is all connected with fpga chip, and audio coding decoding chip is connected with volume control module.
Preferably, the bridging chip that the Tsi721 types bridging chip is mutually changed as RapidIO and PCI-E.
Preferably, one end of the Tsi721 types bridging chip passes through PCI-E buses on master control borad with domestic cpu chip
Connection, the other end of Tsi721 type bridging chips access backboard by S-RIO interfaces.
The present invention positive effect be：The present invention can use domestic cpu chip Loongson2H, improve core
The localization rate of parts and components of heart device, also meets design requirement in performance；The system that legacy equipment is accessed new architecture by Tsi721
In, existing equipment is inherited, the cost that reduction updates is realized with preferably compatible, open and dynamical mutual
Connection system scheme.
Description of the drawings
Fig. 1 is the theory diagram that the present invention builds RapidIO and PCI-E interacted systems based on bridging chip.
Fig. 2 is the theory diagram of master control borad of the present invention.
Fig. 3 is the theory diagram of power board of the present invention.
Specific embodiment
Present pre-ferred embodiments are given below in conjunction with the accompanying drawings, to describe technical scheme in detail.
As shown in Figure 1 to Figure 3, the present invention builds RapidIO and PCI-E interacted systems based on bridging chip and includes connecting successively
Master control borad, power board, signal-processing board and the rf board for connecing.
Master control borad includes domestic cpu chip（Such as Loongson 2H chips etc.）, configuration circuit, memorizer, RS232 connect
It is mouth, jtag interface, power transfer module, clock processing module, reset chip, Tsi721 type bridging chips, network chip, total
Line, configuration circuit, memorizer, RS232 interfaces, jtag interface, power transfer module, clock processing module, reset chip,
Tsi721 type bridging chips, network chip are all connected with domestic cpu chip, power transfer module, clock processing module, reset coil
Piece, Tsi721 type bridging chips, network chip are all connected with bus.RapidIO and PCI-E is interconnected by Tsi721 types bridging chip
Novel radio radio station is built, the equipment for supporting PCI-E EBIs is accessed in the system of RapidIO architectures, is utilized
Tsi721 types bridging chip can make to carry out the transmission of mass data bag between PCI-E device and each RapidIO terminal parts, make to lead to
News data can be transmitted between PCI-E device and each RapidIO terminal parts through high-speed serial bus, by the group to data
Bag, unpacking, the parsing of waveform parameter, corresponding unit is distributed to, controls the Efficient Operation of whole interacted system, support platform waveform
Reconstruct, this design meet the requirement interconnected between chip chamber and plate to bandwidth, cost, motility and reliability, realize at a high speed
The purpose of data communication.
Power board include backplane interface, security module, Tsi578 type exchange chips, audio coding decoding chip, vocoder,
Fpga chip, volume control module, backplane interface, security module, Tsi578 type exchange chips, audio coding decoding chip, acoustic code
Device is all connected with fpga chip, and audio coding decoding chip is connected with volume control module.
RapidIO's and PCI-E is interconnected by bridging chip realization, and Tsi721 type bridging chips are developed by Integrated Device Technology, Inc.
Mutually turn the solution that bridging device is provided for PCI-E Gen2 and RapidIO Gen2 agreements, it is possible to achieve RapidIO systems
With the seamless connection of PCI-E systems.As the disposal ability of this bridging chip is strong, postpone it is low, veneer across between backboard and
It is easier that peer-to-peer network process cluster is built between wall of computer case, but high cost.
The bridging chip that Tsi721 types bridging chip is mutually changed as RapidIO and PCI-E, can be very good to solve
RapidIO and PCI-E interconnection problems.Tsi721 type bridging chips are placed on master control borad, by PCI-E EBIs and
Loongson 2H are connected, and recycle RapidIO interfaces to access core bus, and other boards are handed over by the interconnection of RapidIO technologies
Change data.
Master control borad issues waveform program, the FPGA of Jing power boards by Tsi721 type bridging chip transceiving data relevant interfaces
Chip, then the loading fpga chip of signal-processing board is sent to by high speed SPI, it is loaded into waveform processing fpga chip and DSP is complete
Dispose into swift waveform and switch.
In view of exchange chip the layout, signal-processing board waveform processing fpga chip and DSP of hardware configuration control
Program needs the factors such as dynamic load, and communication foundation is divided into two steps to be carried out, first by the fpga chip of power board to exchanging
The each port of chip is associated configuration with each board Master control chip target devices ID；Then treat that each board program is loaded successfully
Afterwards, used as main frame, Tsi721 type bridging chips need by safeguarding bag Remote configuration exchange chip between straddle master control borad, are each plate
Card Master control chip redefines target devices ID, opens corresponding ports and is communicated.
One end of Tsi721 type bridging chips and domestic cpu chip（Such as Loongson 2H chips etc.）On master control borad
Connected by PCI-E buses, the other end of Tsi721 type bridging chips accesses backboard by S-RIO interfaces.
Interacted system hardware configuration is mainly by a master control borad, two power boards, two signal-processing boards and four radio frequencies
Plate is constituted, and realizes the multimodal design of multiband multichannel multitask, and master control borad is required to into line number with other boards
According to interaction, Tsi721 type bridging chips are the keys that master control borad is connected into RapidIO architectures.System Backplane bus is adopted
VPX high-speed serial bus are designed, and support the serial switching fabric of the current industry standards such as RapidIO, PCI-E, there is provided higher
Backboard broadband, satisfaction can be also applied in the adverse circumstances such as military affairs.
Domestic cpu chip of the master control borad using a support PCI-E EBI（Loongson 2H）With a Tsi721
Type bridging chip, the waveform parameter configuration information that master control borad reception host computer sends are distributed to corresponding unit, and by signal
The synchronizing indication information reporting that reason plate sends is to host computer.
Development prospect of the fpga chip on personal key algorithm is realized is considered in design, on power board, by FPGA
Chip is combined with Tsi578 type exchange chips, security module, is played a part of to audio frequency and key safeguard protection.Audio frequency
Signal is encoded by audio coding decoding chip, and fpga chip is distinguished voice mode and selects to be 2.4Kbps or 16Kbps
CVSD speeches, if 2.4Kbps speeches, Jing security modules encryption after group bag, then master control borad waveform components are issued, if
16Kbps CVSD speeches, Jing security modules encryption after group bag, then issue signal-processing board DSP waveform components；And from these waveforms
Component voice data Jing after the demodulation that Tsi578 exchange chips are sent, is decrypted by security module, if 2.4Kbps speeches, send
To vocoder, if 16Kbps CVSD speeches, audio coding decoding chip decoding is delivered to.
With fpga chip and DSP as core devices, this modular design has given full play to powerful fast of DSP to signal-processing board
Fast calculation processing power and the flexible comparison rule computing advantage of fpga chip.By RapidIO interfaces, DSP waveform components are sent out
Penetrate the PCM speech group packet encoders that power board sends by link master control borad waveform components, FPGA sets of waveforms is issued into CVSD speeches
Part receives the speech data message that master control borad waveform components are sent, and is processed, receives link process
Then in contrast.And send instructions under master control borad with after program to be loaded, power board receives RapidIO packets, then Jing is at a high speed
SPI is first stored in each frame complete data in dpram, then loading FPGA of the SPI_dpram modules to signal-processing board
Chip produces an interruption, and program to be loaded is downloaded to ripple by Avalon buses with dma mode by loading fpga chip respectively
Shape processes fpga chip and HPI interfaces are loaded to waveform processing DSP.
Rf board from fpga chip as Master control chip, by RapidIO receive instruction that master control borad issues and on
Report working condition, also has data interaction with signal-processing board.
Each board is connected by RapidIO technologies and builds novel radio radio station, Tsi721 drive softwares provide master control borad with
The software interface of other board communications realizes that Tsi721 drivers designs are adopted and shown a C language, carry according to Software functional requirements
Call to upper level applications for external interface, realize that communication data is transmitted in PCI-E device and RapidIO equipment rooms.
After present invention employs above technical scheme, the fusion of two architecture of RapidIO and PCI-E, structure are realized
The interacted system of a high speed data transfer is built.Bring domestic processor and domestic operating system into radio set from now on
In R＆D mode, allow two kinds of bussing techniques to display one's respective advantages, improve systematic function, extend application, reached pre-
The design object of phase.
Particular embodiments described above, the technical problem, technical scheme and beneficial effect to the solution of the present invention are carried out
Further describe, it is be should be understood that to the foregoing is only specific embodiment of the invention, it is not limited to
The present invention, all any modification, equivalent substitution and improvements within the spirit and principles in the present invention, done etc., should be included in this
Within the protection domain of invention.
Claims (3)
1. it is a kind of that RapidIO and PCI-E interacted systems are built based on bridging chip, it is characterised in which includes what is be sequentially connected
Master control borad, power board, signal-processing board and rf board；
Master control borad include domestic cpu chip, configuration circuit, memorizer, RS232 interfaces, jtag interface, power transfer module, when
Clock processing module, reset chip, Tsi721 type bridging chips, network chip, bus, configuration circuit, memorizer, RS232 interfaces,
Jtag interface, power transfer module, clock processing module, reset chip, Tsi721 type bridging chips, network chip all with it is domestic
Cpu chip connect, power transfer module, clock processing module, reset chip, Tsi721 type bridging chips, network chip all with
Bus connects；
Power board includes backplane interface, security module, Tsi578 type exchange chips, audio coding decoding chip, vocoder, FPGA cores
Piece, volume control module, backplane interface, security module, Tsi578 type exchange chips, audio coding decoding chip, vocoder all with
Fpga chip connects, and audio coding decoding chip is connected with volume control module.
2. RapidIO and PCI-E interacted systems are built based on bridging chip as claimed in claim 1, it is characterised in that described
The bridging chip that Tsi721 types bridging chip is mutually changed as RapidIO and PCI-E.
3. RapidIO and PCI-E interacted systems are built based on bridging chip as claimed in claim 1, it is characterised in that described
One end of Tsi721 type bridging chips is connected by PCI-E buses on master control borad with domestic cpu chip, Tsi721 types bridge joint core
The other end of piece accesses backboard by S-RIO interfaces.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610947059.0A CN106528474A (en) | 2016-11-02 | 2016-11-02 | RapidIO and PCI-E (Peripheral Component Interconnect-Express) interconnection system constructed on the basis of bridging chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610947059.0A CN106528474A (en) | 2016-11-02 | 2016-11-02 | RapidIO and PCI-E (Peripheral Component Interconnect-Express) interconnection system constructed on the basis of bridging chip |
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| CN106528474A true CN106528474A (en) | 2017-03-22 |
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| CN201610947059.0A Pending CN106528474A (en) | 2016-11-02 | 2016-11-02 | RapidIO and PCI-E (Peripheral Component Interconnect-Express) interconnection system constructed on the basis of bridging chip |
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Cited By (5)
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| CN109542817A (en) * | 2018-11-09 | 2019-03-29 | 中国船舶重工集团公司第七二三研究所 | A kind of general ECM set control framework |
| CN109783413A (en) * | 2017-11-14 | 2019-05-21 | 北京中科晶上科技股份有限公司 | Master control borad and control method based on VPX standard |
| CN111078611A (en) * | 2019-12-17 | 2020-04-28 | 昆明联诚科技股份有限公司 | PLC high-speed backplate bus based on FPGA |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109783413A (en) * | 2017-11-14 | 2019-05-21 | 北京中科晶上科技股份有限公司 | Master control borad and control method based on VPX standard |
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| WO2020200113A1 (en) * | 2019-03-29 | 2020-10-08 | 新华三技术有限公司 | Network device |
| CN111078611A (en) * | 2019-12-17 | 2020-04-28 | 昆明联诚科技股份有限公司 | PLC high-speed backplate bus based on FPGA |
| CN112199315A (en) * | 2020-09-28 | 2021-01-08 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | RapidIO network management device and network management method of integrated electronic information system |
| CN112199315B (en) * | 2020-09-28 | 2023-10-20 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Comprehensive electronic information system rapidIO network management device and network management method |
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Application publication date: 20170322 |