CN114338273A - PROFIBUS-DP slave station control system based on FPGA - Google Patents
PROFIBUS-DP slave station control system based on FPGA Download PDFInfo
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Abstract
The invention provides a PROFIBUS-DP slave station control system based on FPGA, wherein a PROFIBUS-DP slave station and a PROFIBUS-DP master station are connected to a PROFIBUS-DP bus, and comprise an FPGA chip and a plurality of expansion peripherals, wherein the FPGA chip is connected with the expansion peripherals and the PROFIBUS-DP bus; in the FPGA chip, a logic module and an MCU soft core are realized through logic design, the logic module receives data sent by the PROFIBUS-DP bus, preprocesses the data sent by the PROFIBUS-DP bus and sends the data to the MCU soft core, and the MCU soft core analyzes the data sent by the logic module and executes control over the PROFIBUS-DP master station, the expansion peripheral and the MCU soft core according to the analyzed data; the invention has the characteristics of high speed, low cost, high flexibility and easy expansion.
Description
Technical Field
The invention relates to the technical field of data communication and control, in particular to a PROFIBUS-DP slave station control system based on an FPGA.
Background
The Process Field Bus (PROFIBUS, Process Field Bus) is completely open, is widely applied to international standard Bus protocols of factory automation and Process automation, and is used for realizing data communication and control of monitoring and Field equipment layers. PROFIBUS is classified into three types according to applicable objects and occasions, and differences in usage specifications: PROFIBUS-FMS (field bus information specification), PROFIBUS-DP (distributed perimeter), PROFIBUS-PA (process automation). The DP (decentralized peripheral) is optimized and specially used for digital high-speed communication between the field I/O equipment and the automatic control system, and the data transmission rate range is 9.6 Kbit/s-12 Mbit/s; in practice, 90% of PROFIBUS usage is DP usage, so DP technology is the most influential of PROFIBUS.
The PROFIBUS-DP slave station system comprises a hardware circuit part and a software control part, wherein the hardware circuit part ensures the normal work and the signal transmission quality of a communication chip, and the software control part mainly comprises the initialization of the PROFIBUS-DP and the control of normal data communication.
As a completely open protocol, the design of the existing PROFIBUS-DP slave station control system mainly includes the following three cases:
1. the design of a PROFIBUS-DP slave station control system is realized by using a single chip microcomputer, the system is suitable for simple and low-speed occasions, and high-speed communication cannot be met;
2. the design of the control system of the PROFIBUS-DP slave station is realized by combining a special communication protocol chip with a CPU/FPGA chip or combining the CPU chip with a soft core and a hard core in the FPGA chip, although the functions are complete, the special communication protocol chip has higher cost and limited flexibility, and the two chips occupy larger space of a PCB board in the hardware design;
3. the design of the PROFIBUS-DP slave station control system is realized by using the internal logic of the FPGA chip, and is realized by only using Verilog hardware language, but the flexibility of the whole framework is deficient due to the characteristics of the hardware language, so that the expansion development of application is not convenient to carry out.
Disclosure of Invention
The invention aims to provide a PROFIBUS-DP slave station control system based on an FPGA, which has the characteristics of high speed, low cost, high flexibility and easy expansion.
In order to achieve the aim, the invention provides a PROFIBUS-DP slave station control system based on FPGA, wherein the PROFIBUS-DP slave station and the PROFIBUS-DP master station are connected to a PROFIBUS-DP bus;
in the FPGA chip, a logic module and an MCU soft core are realized through logic design, the logic module receives data sent by the PROFIBUS-DP bus, preprocesses the data sent by the PROFIBUS-DP bus and sends the data to the MCU soft core, and the MCU soft core analyzes the data sent by the logic module and executes control over the PROFIBUS-DP master station, the expansion peripheral and the MCU soft core according to the analyzed data.
Optionally, the MCU soft core sends the data stored in the MCU soft core and/or the acquired data of the peripheral expansion device to the logic module according to the analysis data.
Optionally, the logic module includes a UART sub-module and a signal buffering sub-module, the UART sub-module receives data sent by the PROFIBUS-DP bus and sends the data to the signal buffering sub-module, and the signal buffering sub-module receives, pre-processes and sends the data sent by the UART sub-module to the MCU soft core; or, the signal buffer submodule receives the data sent by the MCU soft core, packages the data and sends the data to the UART submodule.
Optionally, the data sent by the PROFIBUS-DP bus is serial data, and the data sent by the signal buffering submodule to the UART submodule is parallel data; the UART sub-modules comprise a data receiving unit, a data sending unit and a baud rate generating unit, the data receiving unit receives serial data sent by the PROFIBUS-DP bus, the data sending unit converts parallel data sent by the signal buffering sub-modules into serial data and sends the serial data to the PROFIBUS-DP bus, and the baud rate generating unit provides a baud rate clock signal to the data receiving unit and the data sending unit.
Optionally, the baud rate generating unit includes a baud rate automatic detection subunit and a baud rate manual configuration subunit, and the baud rate automatic detection subunit or the baud rate manual configuration subunit provides the baud rate clock signal to the data receiving unit and the data sending unit.
Optionally, the data receiving unit performs double-edge sampling on the serial data sent by the PROFIBUS-DP bus under the baud rate clock signal and sends the sampled data to the signal buffering submodule.
Optionally, the signal buffering submodule includes a data buffering unit, a protocol preprocessing unit and a bus data interface unit, and the data buffering unit and the protocol preprocessing unit buffer and preprocess data sent by the UART submodule in sequence and then send the data to the MCU soft core through the bus data interface unit; or, the data sent by the MCU soft core passes through the bus data interface unit, is sequentially packed and buffered by the protocol preprocessing unit and the data buffer unit, and is sent to the UART sub-module.
Optionally, the data caching unit includes a data receiving caching subunit and a data sending caching subunit, the protocol preprocessing unit includes a protocol pre-parsing subunit and a protocol packing subunit, and the bus data interface unit includes a bus data receiving caching subunit, a bus data sending caching subunit, a bus data receiving interface and a bus data sending interface;
the data receiving cache subunit, the protocol pre-analysis subunit and the bus data receiving cache subunit sequentially cache, pre-analyze and convert data sent by the UART submodule and then send the data to the MCU soft core through the bus data receiving interface; alternatively, the first and second electrodes may be,
and data transmitted by the MCU soft core passes through the bus data transmitting interface, is sequentially subjected to data conversion, data packaging and buffering by the bus data transmitting buffer subunit, the protocol packaging subunit and the data transmitting buffer subunit, and is transmitted to the UART submodule.
Optionally, the MCU soft core includes a central control module, an interrupt control module, a bus control module and an input/output control module, where the bus control module receives data sent by the logic module and sends the data to the central control module, or receives data sent by the central control module and sends the data to the logic module; the interrupt control module receives and responds to an interrupt signal sent by the logic module to control the central control module to realize interrupt; the expansion peripheral device realizes bidirectional communication with the central control module through the input and output control module.
Optionally, the input/output control module includes a UART control unit, an SPI control unit, and an I2C control unit, UART control unit, SPI control unit and I2The C control unit is respectively provided with a UART control interface, an SPI control interface and an I2C control interface, UART control unit, SPI control unit and I2And the C control unit is connected with the expansion peripheral through the UART control interface, the SPI control interface and the I2C control interface respectively.
The FPGA-based PROFIBUS-DP slave station control system comprises an FPGA chip and a plurality of expansion peripherals, wherein the FPGA chip is connected with the expansion peripherals and a PROFIBUS-DP bus; in the FPGA chip, a logic module and an MCU soft core are realized through logic design, the logic module receives data sent by the PROFIBUS-DP bus, preprocesses the data sent by the PROFIBUS-DP bus and sends the preprocessed data to the MCU soft core, and the logic module has high data processing rate and good real-time performance and meets the requirement of high rate on the PROFIBUS-DP bus; the MCU soft core analyzes data sent by the logic module, executes control over the PROFIBUS-DP main station, the expansion peripheral and the MCU according to the analyzed data, increases application flexibility by realizing the MCU soft core in the FPGA chip, and can expand and reduce functions of the MCU soft core according to application requirements. Therefore, the invention has the characteristics of high speed, low cost, high flexibility and easy expansion.
Drawings
Fig. 1 is a hardware framework diagram of a slave station control system of PROFIBUS-DP based on FPGA according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a frame of an FPGA chip in the FPGA-based PROFIBUS-DP slave station control system according to an embodiment of the present invention.
Fig. 3 and fig. 4 are schematic frame diagrams of logic modules in an FPGA chip in the FPGA-based PROFIBUS-DP slave station control system according to an embodiment of the present invention.
Fig. 5 is a schematic diagram of a frame of an MCU soft core in an FPGA chip in an FPGA-based PROFIBUS-DP slave station control system according to an embodiment of the present invention.
Fig. 6 is a schematic diagram of an overall framework of an FPGA chip in the FPGA-based PROFIBUS-DP slave station control system according to an embodiment of the present invention.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Fig. 1 is a hardware frame schematic diagram of the FPGA-based PROFIBUS-DP slave station control system according to this embodiment. Please refer to fig. 1, this embodiment provides a FPGA-based control system for a slave of a PROFIBUS-DP, in which a slave of the PROFIBUS-DP and a master of the PROFIBUS-DP are connected to a PROFIBUS-DP bus, the FPGA-based control system for the slave of the PROFIBUS-DP includes a FPGA chip and a plurality of expansion peripherals, the FPGA chip is connected to the plurality of expansion peripherals, and the expansion peripherals can be a temperature sensor, an expansion test interface, an expansion serial port, etc. And the FPGA chip is connected to the PROFIBUS-DP bus to receive the data sent by the PROFIBUS-DP bus and process the data sent by the PROFIBUS-DP bus so as to realize data communication and system control of the PROFIBUS-DP slave station and the PROFIBUS-DP master station through the PROFIBUS-DP bus. For example, the FPGA chip receives data sent by the PROFIBUS-DP bus in real time and identifies the data sent by the PROFIBUS-DP bus, determines whether the data sent by the PROFIBUS-DP bus needs to be processed by the PROFIBUS-DP slave station, ignores the data sent by the PROFIBUS-DP bus if not needed, and responds to the data sent by the PROFIBUS-DP bus to perform corresponding operations if needed, for example, the data sent by the PROFIBUS-DP bus requires to acquire data of the expansion peripheral, the FPGA chip acquires data of the expansion peripheral, and then the FPGA chip packages the acquired data of the expansion peripheral and sends the packaged data to the PROFIBUS-DP bus.
Furthermore, an isolation circuit is arranged between the PROFIBUS-DP bus and the FPGA chip, the PROFIBUS-DP bus belongs to an industrial bus, the FPGA chip is applied to weak current, and the isolation circuit arranged between the PROFIBUS-DP bus and the FPGA chip can play roles of avoiding surge, eliminating ground potential difference and the like. In this embodiment, from the hardware perspective, the main function of the PROFIBUS-DP slave station can be realized by one FPGA chip, and a dedicated protocol analysis chip and a special interface module are not needed, so that the hardware cost and the PCB board space can be saved.
Fig. 2 is a schematic diagram of a frame of an FPGA chip in the FPGA-based PROFIBUS-DP slave station control system according to this embodiment. Referring to fig. 2, in the FPGA chip, a logic module and an MCU soft core are implemented through logic design, and the MCU soft core is embedded in the FPGA chip through a programming language, which may be C language, and can flexibly extend functions according to actual needs, for example, the FPGA chip needs to be connected with more extension peripherals to implement more functions, and then the MCU soft core can be developed with extended functions according to the functions that need to be implemented; and a logic module is arranged in the FPGA chip through a programming language, the programming language is a hardware Verilog language, the logic module is mainly used for receiving and transmitting data sent by the PROFIBUS-DP bus, and the logic module can enable the processing data rate of the system to be high and the real-time performance to be good, so that the requirement of high rate on the PROFIBUS-DP bus is met.
In this embodiment, the logic module receives data sent by the PROFIBUS-DP bus, preprocesses the data sent by the PROFIBUS-DP bus, and sends the preprocessed data to the MCU soft core, and the MCU soft core parses the data sent by the logic module and executes control over the PROFIBUS-DP master station, the expansion peripheral, and the MCU soft core according to the parsed data. The logic module also sends an interrupt signal to the MCU soft core, and the MCU soft core receives and responds to the interrupt signal to realize the interrupt control of the MCU soft core; and the MCU soft core can send the data stored by the MCU soft core and/or the acquired data of the expansion peripheral to the logic module according to the analysis data.
Fig. 3 and fig. 4 are schematic diagrams of frames of logic modules in an FPGA chip in the FPGA-based PROFIBUS-DP slave station control system according to this embodiment. Referring to fig. 3 and 4, the logic module includes a UART sub-module and a signal buffering sub-module, the UART sub-module receives data sent by the PROFIBUS-DP bus and sends the data to the signal buffering sub-module, and the signal buffering sub-module pre-processes the received data sent by the UART sub-module and sends the preprocessed data to the MCU soft core; or the signal buffer submodule receives the data sent by the MCU soft core and packages the data to the UART submodule.
Furthermore, the UART submodule data receiving unit, the data sending unit and the baud rate generating unit are used, data sent by the PROFIBUS-DP bus are serial data, and data sent by the signal buffering submodule to the UART submodule are parallel data; the data receiving unit receives serial data of data sent by the PROFIBUS-DP bus, and the data sending unit converts parallel data sent by the signal buffering submodule into serial data and sends the serial data to the PROFIBUS-DP bus; the baud rate generating unit provides a baud rate clock signal to the data receiving unit and the data sending unit, specifically, the baud rate generating unit receives an input clock signal, the clock signal can be an external system clock input, the baud rate generating unit converts the input clock signal into a required baud rate clock, and then the baud rate clock signal is sent to the data receiving unit and the data sending unit. In this embodiment, the baud rate generating unit includes a baud rate automatic detection subunit and a baud rate manual configuration subunit, and baud rate clock signals are provided to the data receiving unit and the data sending unit through the baud rate automatic detection subunit or the baud rate manual configuration subunit, where the baud rate automatic detection subunit has a wider application scenario, but has a relatively higher complexity and a higher requirement on hardware; the baud rate manual configuration subunit is suitable for scenes with fixed and unchanged baud rate, has low requirement on hardware, and occupies less internal resources of an FPGA chip.
Furthermore, the data receiving unit carries out double-edge sampling on serial data sent by the PROFIBUS-DP bus under baud rate clock signals and sends the sampled data to the signal buffering sub-module, the double-edge sampling can reduce a system clock, the requirement on selecting FPGA chips is low, and the FPGA chip is suitable for FPGA chips of different models.
Furthermore, the signal buffering submodule comprises a data buffering unit, a protocol preprocessing unit and a bus data interface unit, and the data buffering unit and the protocol preprocessing unit sequentially buffer and preprocess data sent by the UART submodule and then send the data to the MCU soft core through the bus data interface unit; or, the data sent by the MCU soft core passes through the bus data interface unit, is sequentially packed and buffered by the protocol preprocessing unit and the data buffer unit, and is sent to the UART submodule.
The bus data interface unit comprises a bus data receiving cache subunit, a bus data sending cache subunit, a bus data receiving interface and a bus data sending interface. The data receiving cache subunit, the protocol pre-analysis subunit and the bus data receiving cache subunit sequentially cache, pre-analyze and convert data sent by the UART submodule and then send the data to the MCU soft core through the bus data receiving interface; or, the data transmitted by the MCU soft core passes through the bus data transmitting interface, is sequentially subjected to data conversion, data packaging and buffering by the bus data transmitting buffer subunit, the protocol packaging subunit and the data transmitting buffer subunit, and is transmitted to the UART submodule. The method comprises the steps that a data receiving unit receives serial data sent by a PROFIBUS-DP bus and then sends the serial data to a data receiving cache subunit, the data receiving cache subunit temporarily stores the data sent by the data receiving unit in the data receiving cache subunit and then sends the data to a protocol pre-analysis subunit for preliminary analysis, the preliminary analysis mainly comprises data verification and analysis, the data after the preliminary analysis are sent to the bus data receiving cache subunit, and the bus data receiving cache subunit performs data conversion according to a bus interface protocol of an MCU soft core and then sends the data to the MCU soft core through a bus data receiving interface. Or the bus data sending cache subunit receives the data sent by the MCU soft core through the bus data sending interface, the data is converted according to a bus interface protocol of the logic module through the bus data sending cache subunit and then sent to the protocol packing subunit, the protocol packing subunit packs the data according to a fixed mode and then sends the packed data to the data sending cache subunit, the fixed mode is a mode which can be identified by a receiver, and the data sending cache subunit temporarily stores the packed data in the data sending cache subunit and then sends the packed data to the PROFIBUS-DP bus through the data sending unit.
Fig. 5 is a schematic diagram of a frame of the MCU soft core in the FPGA chip in the FPGA-based PROFIBUS-DP slave station control system according to this embodiment. Referring to fig. 5, the MCU soft core includes a central control module, an interrupt control module, a bus control module, an input/output control module, a program storage module, a random storage module, and a timing module/counting module; the bus control module is provided with a bus data interface, the bus data interface of the bus data module is connected with a bus data receiving interface and a bus data sending interface in the logic module, and the bus control module receives data sent by the logic module and sends the data to the central control module or receives data sent by the central control module and sends the data to the logic module; the method comprises the steps that clock signals are input to a central control module, the central control module comprises a control module and an operation module, a bus control module is in two-way communication with the central control module, an input and output control module, a random storage module, a two-way communication module and a timing module/counting module, the central control module can obtain data stored in a program storage module, an interrupt signal is input to an interrupt control module from the outside, and the interrupt control module can obtain the data of the program storage module and responds to the interrupt signal so as to control the central control module to realize interruption and execute corresponding operation; the expansion peripheral is connected with the input and output control module, and the expansion peripheral realizes data interaction with the central control module through the input and output control module.
In this embodiment, the input/output control module includes a UART control unit, an SPI control unit, and an I2C control unit, but not limited to the above control unit; UART control unit, SPI control unit and I2The C control unit is respectively provided with a UART control interface, an SPI control interface and an I2C control interface, the above-mentioned interfaces are input/output bidirectional interface, UART control unit, SPI control unit and I2The C control unit is respectively connected with different expansion peripherals through a UART control interface, an SPI control interface and an I2C control interface so as to realize the bidirectional communication between the expansion peripherals and the central control module.
Furthermore, the MCU soft core can flexibly realize function expansion according to actual requirements, for example, the FPGA chip needs to be connected with more expansion peripherals to realize more functions, the MCU soft core can be developed according to the functions required to be realized, an expansion interface is also arranged after the function expansion, and the expansion interface is connected with the expansion peripherals to realize the bidirectional communication between more expansion peripherals and the central control module.
Fig. 6 is a schematic diagram of an overall framework of an FPGA chip in the FPGA-based PROFIBUS-DP slave station control system according to this embodiment. Referring to fig. 6, after data on the PROFIBUS-DP bus is input to the FPGA chip and is pre-processed by the data receiving module, the data receiving buffer subunit, the protocol pre-analysis module and the bus data receiving buffer subunit in sequence, the logic module sends the pre-processed data to the bus control module through the bus receiving interface, the bus control module sends the data sent by the logic module to the central control module, the central control module combines the program storage module, the random storage module and the timing module/counting module to analyze the data sent by the logic module, the central control module executes a corresponding process in response to the analyzed data, for example, the analyzed data requires to obtain data of the expansion peripheral, the central control module obtains data of the expansion peripheral, and then sends the obtained data of the expansion peripheral to the logic module through the bus control module, the method comprises the steps that when data of the expansion peripheral are sent to a logic module through a bus control module, a write mark is sent through the bus control module, and the logic module is marked to write in the data sent from an MCU kernel, namely the data of the expansion peripheral; the data of the expansion peripheral is sent to the bus data sending cache subunit through the bus data sending interface, and after being processed by the bus data sending cache subunit, the data of the expansion peripheral is sent to the PROFIBUS-DP bus through the protocol packing subunit, the data sending cache subunit and the data sending unit in sequence. In this embodiment, the FPGA chip further has a watchdog, and when the system crashes, the logic module and the MCU soft core are reset by the watchdog, and the watchdog inputs a clock signal, which may be an external system clock input.
In fig. 1 to 6, the direction of the arrow indicates an input and/or an output, and in the above, the data or signal direction of the input and output of each module, sub-module, unit and sub-unit has been clearly illustrated, that is, the meaning of the direction of the arrow has been illustrated. For example, in fig. 4, an input arrow of the data receiving unit indicates that data sent by the PROFIBUS-DP bus is input to the data receiving unit, that is, the data receiving unit receives data sent by the PROFIBUS-DP bus, an output arrow of the data sending unit indicates that the data sending unit sends data to the PROFIBUS-DP bus, an input arrow of the baud rate generating unit indicates that an external clock signal is input to the baud rate generating unit, an output arrow of the bus data receiving interface indicates that data is sent to the MCU soft core through the bus data receiving interface, and an input arrow of the bus data sending interface indicates that data sent by the MCU soft core is input through the bus data sending interface; in fig. 5, an input arrow of the interrupt control module indicates that an interrupt signal sent by the logic module is sent to the interrupt control module, one of two input arrows of the central control module indicates that data sent by the interrupt control module is sent to the central control module, and the other indicates that an external interrupt signal is input to the central control module, a bidirectional arrow of the bus control module indicates that data sent by the logic module can be received and also sent to the logic module, a bidirectional arrow of the input/output control module indicates that data sent by the expansion peripheral can be received, that is, data of the expansion peripheral can be obtained and also sent to the expansion peripheral, and a bidirectional arrow of the function expansion similarly can both send data and receive data.
In summary, the FPGA-based PROFIBUS-DP slave station control system comprises an FPGA chip and a plurality of expansion peripherals, wherein the FPGA chip is connected with the expansion peripherals and a PROFIBUS-DP bus; in the FPGA chip, a logic module and an MCU soft core are realized through logic design, the logic module receives data sent by the PROFIBUS-DP bus, preprocesses the data sent by the PROFIBUS-DP bus and sends the preprocessed data to the MCU soft core, and the logic module has high data processing rate and good real-time performance and meets the requirement of high rate on the PROFIBUS-DP bus; the MCU soft core analyzes data sent by the logic module, executes control over the PROFIBUS-DP main station, the expansion peripheral and the MCU according to the analyzed data, increases application flexibility by realizing the MCU soft core in the FPGA chip, and can expand and reduce functions of the MCU soft core according to application requirements. Therefore, the invention has the characteristics of high speed, low cost, high flexibility and easy expansion.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A PROFIBUS-DP slave station control system based on FPGA, the PROFIBUS-DP slave station and the PROFIBUS-DP master station are connected to a PROFIBUS-DP bus, characterized by comprising an FPGA chip and a plurality of expansion peripherals, wherein the FPGA chip is connected with the expansion peripherals and the PROFIBUS-DP bus;
in the FPGA chip, a logic module and an MCU soft core are realized through logic design, the logic module receives data sent by the PROFIBUS-DP bus, preprocesses the data sent by the PROFIBUS-DP bus and sends the data to the MCU soft core, and the MCU soft core analyzes the data sent by the logic module and executes control over the PROFIBUS-DP master station, the expansion peripheral and the MCU soft core according to the analyzed data.
2. The FPGA-based PROFIBUS-DP slave station control system of claim 1, wherein the MCU soft core transmits data stored in the MCU soft core and/or the acquired data of the extended peripheral to the logic module according to the parsed data.
3. The FPGA-based PROFIBUS-DP slave station control system of claim 1, wherein the logic module comprises a UART sub-module and a signal buffering sub-module, the UART sub-module receives data sent by the PROFIBUS-DP bus and sends the data to the signal buffering sub-module, and the signal buffering sub-module receives and pre-processes the data sent by the UART sub-module and sends the data to the MCU soft core; or, the signal buffer submodule receives the data sent by the MCU soft core, packages the data and sends the data to the UART submodule.
4. The FPGA-based PROFIBUS-DP slave station control system of claim 3, wherein the data transmitted by the PROFIBUS-DP bus is serial data, and the data transmitted by the signal buffering sub-module to the UART sub-module is parallel data; the UART sub-modules comprise a data receiving unit, a data sending unit and a baud rate generating unit, the data receiving unit receives serial data sent by the PROFIBUS-DP bus, the data sending unit converts parallel data sent by the signal buffering sub-modules into serial data and sends the serial data to the PROFIBUS-DP bus, and the baud rate generating unit provides a baud rate clock signal to the data receiving unit and the data sending unit.
5. The FPGA-based PROFIBUS-DP slave control system of claim 4, wherein the baud rate generating unit comprises an automatic baud rate detecting subunit and a manual baud rate configuring subunit, the automatic baud rate detecting subunit or the manual baud rate configuring subunit providing the baud rate clock signal to the data receiving unit and the data transmitting unit.
6. The FPGA-based PROFIBUS-DP slave station control system of claim 4 or 5, wherein the data receiving unit performs double edge sampling on serial data transmitted by the PROFIBUS-DP bus under the baud rate clock signal and transmits the sampled data to the signal buffering submodule.
7. The FPGA-based PROFIBUS-DP slave station control system of claim 3, wherein the signal buffering sub-module comprises a data buffering unit, a protocol preprocessing unit and a bus data interface unit, the data buffering unit and the protocol preprocessing unit buffer and preprocess data transmitted by the UART sub-module in sequence and then transmit the data to the MCU soft core through the bus data interface unit; or, the data sent by the MCU soft core passes through the bus data interface unit, is sequentially packed and buffered by the protocol preprocessing unit and the data buffer unit, and is sent to the UART sub-module.
8. The FPGA-based PROFIBUS-DP slave control system of claim 7, wherein said data buffering unit comprises a data receiving buffering subunit and a data transmitting buffering subunit, said protocol preprocessing unit comprises a protocol pre-parsing subunit and a protocol packing subunit, and said bus data interface unit comprises a bus data receiving buffering subunit, a bus data transmitting buffering subunit, a bus data receiving interface and a bus data transmitting interface;
the data receiving cache subunit, the protocol pre-analysis subunit and the bus data receiving cache subunit sequentially cache, pre-analyze and convert data sent by the UART submodule and then send the data to the MCU soft core through the bus data receiving interface; alternatively, the first and second electrodes may be,
and data transmitted by the MCU soft core passes through the bus data transmitting interface, is sequentially subjected to data conversion, data packaging and buffering by the bus data transmitting buffer subunit, the protocol packaging subunit and the data transmitting buffer subunit, and is transmitted to the UART submodule.
9. The FPGA-based PROFIBUS-DP slave station control system of claim 1, wherein the MCU soft core comprises a central control module, an interrupt control module, a bus control module and an input-output control module, the bus control module receives data sent by the logic module and sends the data to the central control module or receives data sent by the central control module and sends the data to the logic module; the interrupt control module receives and responds to an interrupt signal sent by the logic module to control the central control module to realize interrupt; the expansion peripheral device realizes bidirectional communication with the central control module through the input and output control module.
10. The FPGA-based PROFIBUS-DP slave control system of claim 9, wherein said input output control module comprises a UART control unit, a SPI control unit, and I2C control unit, UART control unit, SPI control unit and I2The C control unit is respectively provided with a UART control interface, an SPI control interface and an I2C control interface, UART control unit, SPI control unit and I2And the C control unit is connected with the expansion peripheral through the UART control interface, the SPI control interface and the I2C control interface respectively.
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