CN110069429B - ZYNQ-based real-time high-performance SRIO controller and control method - Google Patents

Abstract

The invention discloses a ZYNQ-based real-time high-performance SRIO controller and a control method thereof.A PS (integrated ARM processing system) sends an active transaction control instruction or an active read transaction control instruction when an transaction is active; the programmable logic PL invokes corresponding SRIO data in the DDR memory according to the active transaction control instruction, generates an SRIO active transaction request packet and sends the SRIO active transaction request packet to the opposite-end transceiver; or, analyzing the response packet of the opposite-end transceiver according to the active read transaction control instruction, and sending SRIO data of the response packet to the DDR memory; in the passive transaction, the PL parses the passive request packet, stores the data in the DDR memory, and generates an interrupt signal and a response packet. The method solves the problems of high transmission delay and low transmission rate caused by adopting the PS part to realize SRIO interface control, and satisfies the real-time high-performance data transmission application.

Description

ZYNQ-based real-time high-performance SRIO controller and control method

Technical Field

The invention relates to the technical field of computer bus communication, in particular to a ZYNQ-based real-time high-performance SRIO controller and a control method.

Background

The Xilinx ZYNQ-7000 series full-programmable on-chip system adopts a structure of a microprocessor and programmable logic, integrates a dual-core ARM Cortex A9 processing system and the programmable logic of up to 500 more than ten thousand gates, and provides a more flexible solution for an embedded system. The Programmable Logic (PL) part of Zynq has rich IP resources that users can use for logic design. Serial RapaidIO Gen2 is an IP core for developing an SRIO bus, which realizes the conversion of an AXI4Stream interface and an SRIO physical layer interface, thereby realizing the high-speed data transmission of ZYNQ in an embedded system.

The design and implementation of the SRIO protocol is divided into three layers: logical, transport, and physical layers. At present, ZYNQ is used for designing and developing an SRIO interface, a PS part is mainly used for realizing a logic layer and a transmission layer, the method is simple and quick in software realization, but protocol and interrupt signal processing is needed through the software of the PS part, and the SRIO transmission delay is high and the transmission rate is low due to low running efficiency and long execution period of the software of the PS part, so that the real-time high-performance data transmission application cannot be met.

Disclosure of Invention

Aiming at the defects existing in the problems, the invention provides a ZYNQ-based real-time high-performance SRIO controller and a control method.

The invention discloses a ZYNQ-based real-time high-performance SRIO controller, which comprises: the DDR memory, the integrated ARM processing system PS and the programmable logic PL are connected in sequence;

under active transactions:

the DDR memory is used for:

storing data sent and received by SRIO;

the integrated ARM processing system PS is used for:

an active transaction control instruction or an active read transaction control instruction is sent, wherein the active transaction control instruction or the active read transaction control instruction comprises a transaction type, a destination ID and a data packet size;

the programmable logic PL is configured to:

according to the active transaction control instruction, corresponding SRIO data in the DDR memory is called, an SRIO active transaction request packet is generated and sent to an opposite-end transceiver;

and analyzing the response packet of the opposite-end transceiver according to the active read transaction control instruction, and sending SRIO data of the response packet to the DDR memory.

As a further improvement of the invention, under passive transactions:

the programmable logic PL is configured to:

analyzing an SRIO passive transaction request packet of the opposite-end transceiver, and storing generated data into the DDR memory;

analyzing an SRIO passive transaction request packet of the opposite-end transceiver, and notifying the integrated ARM processing system PS by an interrupt signal generated by the SRIO passive transaction request packet;

analyzing the SRIO passive task request packet of the opposite-end transceiver, and sending corresponding SRIO data in the DDR memory to the opposite-end transceiver according to the generated passive control instruction;

the integrated ARM processing system PS is used for:

and receiving the interrupt signal.

As a further development of the invention, the integrated ARM processing system PS is interconnected with the programmable logic PL via an AXI bus.

As a further development of the invention, the integrated ARM processing system PS comprises:

the DDR controller is connected with the DDR memory;

the high-speed interface HP0 is connected with the DDR controller and is used for transmitting SRIO data under an active transaction;

the common interface GP is used for sending the active transaction control instruction or the active reading transaction control instruction;

the high-speed interface HP1 is connected with the DDR controller and is used for transmitting SRIO data under a passive transaction;

an interrupt controller interface INT for receiving the interrupt signal.

As a further improvement of the present invention, the programmable logic PL includes:

the request processing module is connected with the high-speed interface HP0 and the common interface GP through an AXI bus and is used for:

according to the active transaction control instruction, corresponding SRIO data in the DDR memory is called, an SRIO active transaction request packet is generated and sent to an opposite-end transceiver;

analyzing a response packet of the opposite-end transceiver according to the active read transaction control instruction, and sending SRIO data of the response packet to the DDR memory;

the response processing module is connected with the high-speed interface HP1 and the interrupt controller interface INT through an AXI bus and is used for:

analyzing an SRIO passive transaction request packet of the opposite-end transceiver, and storing generated data into the DDR memory;

analyzing an SRIO passive transaction request packet of the opposite-end transceiver, and notifying the integrated ARM processing system PS by an interrupt signal generated by the SRIO passive transaction request packet;

analyzing the SRIO passive task request packet of the opposite-end transceiver, and sending corresponding SRIO data in the DDR memory to the opposite-end transceiver according to the generated passive control instruction;

the SRIO IP core is connected with the request processing module and the response processing module through an AXI bus, and is connected with the opposite-end transceiver through an SRIO physical layer interface; the method is used for realizing conversion of an AXI bus interface and an SRIO physical layer interface.

As a further improvement of the present invention, the request processing module includes:

a first dataframe IP core for providing MM2S and S2MM data flows between SRIO active transactions and DDR memory;

a first transmit data FIFO for buffering MM2S data streams between the SRIO active transaction and the DDR memory;

the first received data FIFO is used for caching S2MM data stream data between the SRIO active transaction and the DDR memory;

the request packet generation module is used for generating a request packet of the SRIO active transaction according to the GP port instruction;

and the analysis response packet module is used for analyzing the response data packet of the SRIO active transaction.

As a further improvement of the present invention, the response processing module includes:

a second dataframe IP core for providing MM2S and S2MM data flows between SRIO passive transactions and DDR memory;

a receiving instruction FIFO for caching the request packet header frame data of the SRIO passive transaction;

the second receiving data FIFO is used for caching S2MM data stream data between the SRIO passive transaction and the DDR memory;

the second sending data FIFO is used for caching MM2S data stream data between the SRIO passive transaction and the DDR memory;

the analysis request packet module is used for analyzing a request data packet of the SRIO passive transaction and generating an interrupt signal according to the transaction type of the request data packet;

and the response packet module is used for generating a response packet of the SRIO passive request transaction.

The invention also discloses a control method of the real-time high-performance SRIO controller, which comprises the following steps:

under active transactions:

the integrated ARM processing system PS sends an active transaction control instruction which comprises a transaction type, a destination ID and a data packet size;

and the programmable logic PL invokes corresponding SRIO data in the DDR memory according to the initiative transaction control instruction, generates an SRIO initiative transaction request packet and sends the SRIO initiative transaction request packet to a peer transceiver.

As a further improvement of the present invention, there is also included:

under active transactions:

the integrated ARM processing system PS sends an active read transaction control instruction which comprises a transaction type, a destination ID and a data packet size;

and the programmable logic PL analyzes the response packet of the opposite-end transceiver according to the active read transaction control instruction, and sends SRIO data of the response packet to the DDR memory.

As a further improvement of the present invention, there is also included:

under passive transactions:

the programmable logic PL analyzes an SRIO passive transaction request packet of the opposite-end transceiver, and the generated data is stored in the DDR memory;

the programmable logic PL analyzes an SRIO passive transaction request packet of the opposite terminal transceiver, and the generated interrupt signal informs the integrated ARM processing system PS;

and the programmable logic PL analyzes the SRIO passive event request packet of the opposite-end transceiver, and sends corresponding SRIO data in the DDR memory to the opposite-end transceiver according to the generated passive control instruction.

Compared with the prior art, the invention has the beneficial effects that:

the invention realizes the SRIO interface logic layer, the transmission layer and the data flow control through the PL part, and the PS part can realize the SRIO interface control only by simple register operation; the problems of high transmission delay and low transmission rate caused by adopting the PS part to realize SRIO interface control are solved, and the real-time high-performance data transmission application is satisfied.

Drawings

FIG. 1 is a block diagram of a ZYNQ-based real-time high performance SRIO controller according to one embodiment of the present invention;

FIG. 2 is a schematic diagram of the request processing module of FIG. 1;

fig. 3 is a schematic diagram of the response processing module in fig. 1.

In the figure:

10. DDR memory; 20. an integrated ARM processing system PS; 30. programmable logic PL; 31. a request processing module; 311. a first dataover IP core; 312. a first transmit data FIFO; 313. a first receive data FIFO; 314. a request packet generation module; 315. a response packet analyzing module; 32. a response processing module; 321. a second dataover IP core; 322. receive instruction FIFO; 323. a second receive data FIFO; 324. a second transmit data FIFO; 325. the request packet analysis module; 326. a response packet module; 33. SRIO IP core.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The invention is described in further detail below with reference to the attached drawing figures:

as shown in fig. 1, the present invention provides a real-time high-performance SRIO controller based on ZYNQ, comprising: a DDR memory 10, an integrated ARM processing system PS 20, and a programmable logic PL 30 connected in sequence; DDR memory 10, is used for SRIO sending and storage of the received data; an integrated ARM Processing System (PS) 20 for executing application software and sending active control instructions when an active transaction is performed; the system comprises a high-speed interface HP, a common interface GP and a DDR controller; programmable Logic (PL) 30 for implementing SRIO control logic, including a request processing module 31, a reply processing module 32, and an SRIO IP core 33; the DDR memory is connected with the PS part DDR controller; the PS and PL portions are interconnected by an AXI bus. Through the framework structure, PL is adopted to replace PS, the problems of high transmission delay and low transmission rate caused by adopting a PS part to realize SRIO interface control are solved, and the real-time high-performance data transmission application is satisfied.

Wherein:

under active transactions:

DDR memory 10 for:

storing data sent and received by SRIO;

an integrated ARM processing system PS 20 for:

transmitting an active transaction control instruction or an active read transaction control instruction, wherein the active transaction control instruction or the active read transaction control instruction comprises a transaction type, a destination ID and a data packet size;

programmable logic PL 30 for:

according to the active transaction control instruction, corresponding SRIO data in the DDR memory is called (data of corresponding address of the DDR is moved to the FIFO), and is packed, an SRIO active transaction request packet (comprising a protocol frame header and a data frame) is generated and sent to an opposite-end transceiver; and waiting for SRIO response transaction, after confirming the response transaction, the programmable logic PL 30 sends the next initiative transaction request until all data transmission is completed (because 256 bytes of data are transmitted at most each time, if the size of a data packet sent by PS is 1024 bytes, four write transactions need to be initiated);

and analyzing the response packet of the opposite-end transceiver according to the active read transaction control instruction, and sending SRIO data of the response packet to the DDR memory.

Under passive transactions:

DDR memory 10 for:

storing data sent and received by SRIO;

programmable logic PL 30 for:

analyzing an SRIO passive transaction request packet of the opposite-end transceiver, and storing the generated data into a DDR (double data rate) storage;

analyzing an SRIO passive transaction request packet of the opposite-end transceiver, and notifying an integrated ARM processing system PS 20 of the generated interrupt signal;

analyzing an SRIO passive task request packet of the opposite-end transceiver, and sending corresponding SRIO data in the DDR memory to the opposite-end transceiver according to the generated passive control instruction;

an integrated ARM processing system PS 20 for:

an interrupt signal is received.

Specific:

the PS 20 of the present invention includes:

the DDR controller is connected with the DDR memory and is used for responding to related instructions, and sending corresponding data outwards from the DDR memory or receiving data transmitted from the outside;

the high-speed interface HP0, the high-speed interface HP0 links with DDR controller, and interconnect with request processing module of PL part through AXI bus; for transmitting SRIO data under active transactions, i.e. providing MM2S and S2MM data flows between SRIO active transactions and DDR memory over the interface;

the common interface GP is interconnected with the request processing module 31 of the PL part through an AXI bus; the method comprises the steps of sending an active control instruction, namely setting control parameters of an SRIO active transaction and checking the completion state of the active transaction; that is, an active transaction control instruction or an active read transaction control instruction is sent, where the active transaction control instruction or the active read transaction control instruction includes a transaction type, a destination ID, a packet size, and the like;

the high-speed interface HP1, the high-speed interface HP1 links with DDR controller, and interconnect with answer processing module 32 of PL part through AXI bus; for transferring SRIO data under passive transactions, i.e. providing MM2S and S2MM data flows between SRIO passive transactions and DDR memory;

the interrupt controller interface INT is interconnected with the response processing module 32 of the PL section via an AXI bus; for receiving the interrupt signal generated by the reply processing module.

The PL 30 of the present invention includes:

the request processing module 31 is connected with the high-speed interface HP0 and the common interface GP through an AXI bus, and is configured to:

generating an SRIO active transaction request packet and an analytic SRIO active transaction response packet;

further, the step of generating the SRIO active transaction request packet is to invoke corresponding SRIO data in the DDR memory according to the active transaction control instruction, generate the SRIO active transaction request packet and send the SRIO active transaction request packet to the SRIO IP core, and send the SRIO active transaction request packet to the external opposite-end transceiver through the SRIO IP core;

further, the SRIO active transaction response packet is analyzed according to the active read transaction control instruction, and SRIO data of the response packet is sent to the DDR memory through the PS part HP 0;

the response processing module 32 is connected with the high-speed interface HP1 and the interrupt controller interface INT through an AXI bus and is used for analyzing the SRIO passive transaction request packet, generating the SRIO passive transaction response packet and generating an interrupt signal;

further, the SRIO passive transaction request packet is an SRIO passive transaction request packet of the transceiver of the analysis opposite terminal, and the generated data is stored into the DDR memory through the HP1 port of the PS part;

further, the generation of the SRIO passive transaction response packet is to analyze the SRIO passive transaction request packet of the opposite-end transceiver, and send the corresponding SRIO data in the DDR memory to the SRIO IP core according to the generated passive control instruction, and send the SRIO data to the external opposite-end transceiver through the SRIO IP core;

further, the interrupt signal is generated by parsing the SRIO passive transaction request packet of the opposite transceiver, and the generated interrupt signal notifies the integrated ARM processing system PS.

The SRIO IP core 33 implements conversion between an AXI bus interface and an SRIO physical layer interface (opposite-end transceiver interface), and is connected to the request processing module 31 and the response processing module 32 of the PL portion through AXI buses, respectively.

More specifically:

as shown in fig. 2, the request processing module 31 of the present invention includes:

a first dataframe IP core 311 for providing MM2S and S2MM data flows between SRIO active transactions and DDR memory;

a first transmit data FIFO312 for buffering MM2S data streams between SRIO active transactions and DDR memory;

a first receive data FIFO313 for buffering S2MM data stream data between the SRIO active transaction and the DDR memory;

a request packet generation module 314, configured to generate a request packet of an SRIO active transaction according to the GP port command;

the parsing response packet module 315 is configured to parse a response packet of the SRIO active transaction.

As shown in fig. 3, the response processing module 32 of the present invention includes:

a second dataframe IP core 321 for providing MM2S and S2MM data flows between SRIO passive transactions and DDR memory;

a receive instruction FIFO322 for buffering request header frame data for SRIO passive transactions; the request header frame data includes a transaction ID, a transaction type, a data length, address information, priority, and the like.

A second receive data FIFO323 for buffering S2MM data stream data between the SRIO passive transaction and the DDR memory;

a second transmit data FIFO324 for buffering MM2S data stream data between the SRIO passive transactions and the DDR memory;

the parsing request packet module 325 is configured to parse a request packet of the SRIO passive transaction, and generate an interrupt signal according to a transaction type of the request packet;

the reply packet module 326 is configured to generate a reply packet of the SRIO passive request transaction.

The invention provides a control method of a real-time high-performance SRIO controller, which comprises the following steps:

under active transactions:

the integrated ARM processing system PS sends an active transaction control instruction which comprises a transaction type, a destination ID and a data packet size;

the programmable logic PL invokes corresponding SRIO data in the DDR memory (moves data of corresponding address of the DDR into the FIFO) according to the active transaction control instruction, and performs grouping, generates an SRIO active transaction request packet (comprising a protocol frame header and a data frame) and sends the SRIO active transaction request packet to the opposite-end transceiver; and waits for an SRIO reply transaction, after which the programmable logic PL 30 sends the next active transaction request until all data transmission is completed (because 256 bytes of data are sent at most each time, if the size of the packet sent by the PS is 1024 bytes, four write transactions need to be initiated).

Under active transactions:

the integrated ARM processing system PS sends an active read transaction control instruction, wherein the active read transaction control instruction comprises a transaction type, a destination ID and a data packet size;

and the programmable logic PL analyzes the response packet of the opposite-end transceiver according to the active read transaction control instruction, and sends SRIO data of the response packet to the DDR memory.

Under passive transactions:

the programmable logic PL analyzes the SRIO passive transaction request packet of the opposite terminal transceiver, and the generated data is stored in the DDR memory;

the programmable logic PL analyzes the SRIO passive transaction request packet of the opposite terminal transceiver, and the generated interrupt signal informs the integrated ARM processing system PS;

the programmable logic PL analyzes the SRIO passive event request packet of the opposite-end transceiver, and sends corresponding SRIO data in the DDR memory to the opposite-end transceiver according to the generated passive control instruction.

In summary, by adopting the technical method, the beneficial effects of the invention are as follows: the SRIO interface logic layer, the transmission layer and the data flow control are realized through the PL part, and the PS part can realize the SRIO interface control only by simple register operation. The method solves the problems of high transmission delay and low transmission rate caused by adopting the PS part to realize SRIO interface control, and satisfies the real-time high-performance data transmission application.

The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (6)

1. A ZYNQ-based real-time high performance SRIO controller, comprising: the DDR memory, the integrated ARM processing system PS and the programmable logic PL are connected in sequence;

under active transactions:

the DDR memory is used for:

storing data sent and received by SRIO;

the integrated ARM processing system PS is used for:

an active transaction control instruction or an active read transaction control instruction is sent, wherein the active transaction control instruction or the active read transaction control instruction comprises a transaction type, a destination ID and a data packet size; wherein, the liquid crystal display device comprises a liquid crystal display device,

the integrated ARM processing system PS comprises:

the DDR controller is connected with the DDR memory;

the high-speed interface HP0 is connected with the DDR controller and is used for transmitting SRIO data under an active transaction;

the common interface GP is used for sending the active transaction control instruction or the active reading transaction control instruction;

the high-speed interface HP1 is connected with the DDR controller and is used for transmitting SRIO data under a passive transaction;

an interrupt controller interface INT for receiving an interrupt signal;

the programmable logic PL is configured to:

according to the active transaction control instruction, corresponding SRIO data in the DDR memory is called, an SRIO active transaction request packet is generated and sent to an opposite-end transceiver; the method comprises the following steps: the programmable logic PL invokes corresponding SRIO data in the DDR memory according to the active transaction control instruction, namely, moves data of corresponding address of the DDR into the FIFO; grouping packets, generating an SRIO active transaction request packet and sending the SRIO active transaction request packet to a transceiver at the opposite end, wherein the transaction request packet comprises a protocol frame header and a data frame; waiting for SRIO response transaction, and after confirming the response transaction, the programmable logic PL sends the next initiative transaction request until all data transmission is completed;

analyzing a response packet of the opposite-end transceiver according to the active read transaction control instruction, and sending SRIO data of the response packet to the DDR memory; wherein, the liquid crystal display device comprises a liquid crystal display device,

the programmable logic PL includes:

the request processing module is connected with the high-speed interface HP0 and the common interface GP through an AXI bus and is used for:

according to the active transaction control instruction, corresponding SRIO data in the DDR memory is called, an SRIO active transaction request packet is generated and sent to an opposite-end transceiver;

analyzing a response packet of the opposite-end transceiver according to the active read transaction control instruction, and sending SRIO data of the response packet to the DDR memory;

the response processing module is connected with the high-speed interface HP1 and the interrupt controller interface INT through an AXI bus and is used for:

analyzing an SRIO passive transaction request packet of the opposite-end transceiver, and storing generated data into the DDR memory;

analyzing an SRIO passive transaction request packet of the opposite-end transceiver, and notifying the integrated ARM processing system PS by an interrupt signal generated by the SRIO passive transaction request packet;

analyzing the SRIO passive task request packet of the opposite-end transceiver, and sending corresponding SRIO data in the DDR memory to the opposite-end transceiver according to the generated passive control instruction;

the SRIO IP core is connected with the request processing module and the response processing module through an AXI bus, and is connected with the opposite-end transceiver through an SRIO physical layer interface; the method is used for realizing conversion of an AXI bus interface and an SRIO physical layer interface;

the request processing module includes:

a first dataframe IP core for providing MM2S and S2MM data flows between SRIO active transactions and DDR memory;

a first transmit data FIFO for buffering MM2S data streams between the SRIO active transaction and the DDR memory;

the first received data FIFO is used for caching S2MM data stream data between the SRIO active transaction and the DDR memory;

the request packet generation module is used for generating a request packet of the SRIO active transaction according to the GP port instruction;

the analysis response packet module is used for analyzing a response data packet of the SRIO active transaction;

the response processing module comprises:

a second dataframe IP core for providing MM2S and S2MM data flows between SRIO passive transactions and DDR memory;

a receiving instruction FIFO for caching the request packet header frame data of the SRIO passive transaction;

the second receiving data FIFO is used for caching S2MM data stream data between the SRIO passive transaction and the DDR memory;

the second sending data FIFO is used for caching MM2S data stream data between the SRIO passive transaction and the DDR memory;

the analysis request packet module is used for analyzing a request data packet of the SRIO passive transaction and generating an interrupt signal according to the transaction type of the request data packet;

and the response packet module is used for generating a response packet of the SRIO passive request transaction.

2. The real-time high performance SRIO controller of claim 1, wherein, under passive transactions:

the programmable logic PL is configured to:

analyzing an SRIO passive transaction request packet of the opposite-end transceiver, and storing generated data into the DDR memory;

analyzing an SRIO passive transaction request packet of the opposite-end transceiver, and notifying the integrated ARM processing system PS by an interrupt signal generated by the SRIO passive transaction request packet;

analyzing the SRIO passive task request packet of the opposite-end transceiver, and sending corresponding SRIO data in the DDR memory to the opposite-end transceiver according to the generated passive control instruction;

the integrated ARM processing system PS is used for:

and receiving the interrupt signal.

3. The real-time high performance SRIO controller of claim 1, wherein the integrated ARM processing system PS and programmable logic PL are interconnected by an AXI bus.

4. A control method of the real-time high-performance SRIO controller according to any of claims 1 to 3, comprising:

under active transactions:

the integrated ARM processing system PS sends an active transaction control instruction which comprises a transaction type, a destination ID and a data packet size;

and the programmable logic PL invokes corresponding SRIO data in the DDR memory according to the initiative transaction control instruction, generates an SRIO initiative transaction request packet and sends the SRIO initiative transaction request packet to a peer transceiver.

5. The control method as set forth in claim 4, further comprising:

under active transactions:

the integrated ARM processing system PS sends an active read transaction control instruction which comprises a transaction type, a destination ID and a data packet size;

and the programmable logic PL analyzes the response packet of the opposite-end transceiver according to the active read transaction control instruction, and sends SRIO data of the response packet to the DDR memory.

6. The control method as set forth in claim 4, further comprising:

under passive transactions:

the programmable logic PL analyzes an SRIO passive transaction request packet of the opposite-end transceiver, and the generated data is stored in the DDR memory;

the programmable logic PL analyzes an SRIO passive transaction request packet of the opposite terminal transceiver, and the generated interrupt signal informs the integrated ARM processing system PS;

and the programmable logic PL analyzes the SRIO passive event request packet of the opposite-end transceiver, and sends corresponding SRIO data in the DDR memory to the opposite-end transceiver according to the generated passive control instruction.