WO2012053133A1 - Amplificateur à hacheur, filtre actif et circuit générateur de fréquence de référence - Google Patents

Amplificateur à hacheur, filtre actif et circuit générateur de fréquence de référence Download PDF

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Publication number
WO2012053133A1
WO2012053133A1 PCT/JP2011/003475 JP2011003475W WO2012053133A1 WO 2012053133 A1 WO2012053133 A1 WO 2012053133A1 JP 2011003475 W JP2011003475 W JP 2011003475W WO 2012053133 A1 WO2012053133 A1 WO 2012053133A1
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voltage
signal
node
oscillation
signal level
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PCT/JP2011/003475
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English (en)
Japanese (ja)
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徳永　祐介
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パナソニック株式会社
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/38—DC amplifiers with modulator at input and demodulator at output; Modulators or demodulators specially adapted for use in such amplifiers
    • H03F3/387—DC amplifiers with modulator at input and demodulator at output; Modulators or demodulators specially adapted for use in such amplifiers with semiconductor devices only
    • H03F3/393—DC amplifiers with modulator at input and demodulator at output; Modulators or demodulators specially adapted for use in such amplifiers with semiconductor devices only with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H03F3/45192—Folded cascode stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/04—Frequency selective two-port networks
    • H03H11/12—Frequency selective two-port networks using amplifiers with feedback
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45424—Indexing scheme relating to differential amplifiers the CMCL comprising a comparator circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45614—Indexing scheme relating to differential amplifiers the IC comprising two cross coupled switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45616—Indexing scheme relating to differential amplifiers the IC comprising more than one switch, which are not cross coupled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45724—Indexing scheme relating to differential amplifiers the LC comprising two cross coupled switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45726—Indexing scheme relating to differential amplifiers the LC comprising more than one switch, which are not cross coupled

Definitions

  • the present invention relates to a differential amplifier that generates an output voltage corresponding to a difference between two input voltages, and more particularly to an amplifier to which a chopper technique is applied.
  • a differential amplifier that generates an output voltage corresponding to a difference between two input voltages.
  • Such differential amplifiers are used in various technical fields.
  • an active filter including a differential amplifier is used to perform feedback control so that the amplitudes of two oscillation signals generated by the oscillation circuit are constant.
  • Patent Document 1 describes that flicker noise of the differential amplifier can be reduced by incorporating a chopper mechanism in the differential amplifier provided in the active filter.
  • the settling time of the output voltage of the differential amplifier becomes longer than the chopper period, so that the settling error of the output voltage of the differential amplifier becomes an offset voltage. May be included in the output voltage.
  • the offset voltage fluctuates due to temperature changes and power supply voltage fluctuations. As a result, the output voltage of the differential amplifier fluctuates.
  • Patent Documents 2 and 3 describe techniques for reducing such an offset voltage. More specifically, in Patent Document 2, a half circuit of a differential amplifier is provided as a correction replica circuit, and the back gate voltage of a pair of MOS transistors constituting a load current mirror of the differential amplifier is calculated using the correction replica circuit. It is described that the offset voltage is removed from the output voltage of the differential amplifier by correcting. Patent Document 3 discloses a chopper mechanism by reducing the impedance of a path switching node by inserting a cascode transistor between an output node (a node for outputting an output voltage) of a differential amplifier and a chopper mechanism. The response speed of the differential amplifier is increased, and as a result, the offset voltage of the differential amplifier (that is, the settling error of the output voltage) is reduced.
  • an object of the present invention is to provide a chopper amplifier capable of reducing the offset voltage and suppressing the increase in noise of the output voltage without being influenced by the response speed of the chopper mechanism.
  • the chopper amplifier is a chopper amplifier that generates an output voltage corresponding to a difference between the first and second input voltages while alternately switching the first and second operation modes, In the first operation mode, the first input voltage is supplied to the first input node and the second input voltage is supplied to the second input node. In the second operation mode, the first input voltage is supplied to the first input node.
  • An input switching unit for supplying the first input voltage to the second input node and supplying the second input voltage to the first input node; and a first between the first intermediate node and the reference node.
  • the connection switching unit connected to the second intermediate node supplies the first intermediate voltage generated at the first intermediate node to the third intermediate node and the second intermediate node. Is supplied to an output node for outputting the output voltage.
  • the first intermediate voltage is supplied to the output node and the second intermediate voltage is output.
  • An output switching unit that supplies a voltage to the third intermediate node; and a voltage control unit that controls the control voltage so that a voltage applied to the third intermediate node approaches a voltage applied to the output node; Is provided.
  • the fluctuation range of the output voltage can be reduced by controlling the control voltage so that the voltage applied to the third intermediate node approaches the voltage applied to the output node. Accordingly, the settling error of the output voltage that occurs when the settling time of the output voltage is shorter than the chopper cycle (the switching cycle of the first and second operation modes) can be reduced. Therefore, the offset voltage included in the output voltage can be reduced without being influenced by the response speed of the chopper mechanism. Thereby, it is possible to suppress the output voltage from fluctuating due to a temperature change or a power supply voltage fluctuation.
  • the voltage control unit is generated in the voltage control unit by controlling the control voltage corresponding to the power source of the main differential amplification unit (differential amplification unit constituted by the voltage-current conversion unit and the first and second transconductance elements). Since the generated noise can be reduced by the power supply voltage fluctuation rejection ratio (PSRR) of the main differential amplifier, an increase in output voltage noise can be suppressed.
  • PSRR power supply voltage fluctuation rejection ratio
  • the figure which shows the structural example of a chopper amplifier The figure for demonstrating the chopper operation
  • FIG. 1 shows a configuration example of the chopper amplifier 1.
  • the chopper amplifier 1 generates an output voltage Vout corresponding to the difference between the input voltages Vin1 and Vin2 while alternately switching the first and second operation modes.
  • the chopper amplifier 1 includes an input switching unit 101, a voltage / current conversion unit 102, a load transistor 1031 (mutual conductance element), a load transistor 1032 (mutual conductance element), a connection switching unit 104, an output switching unit 105, And a voltage control unit 106.
  • the input switching unit 101 supplies the input voltage Vin1 to the input node Nin1 and supplies the input voltage Vin2 to the input node Nin2.
  • the input switching unit 101 supplies the input voltage Vin1 to the input node Nin2 and supplies the input voltage Vin2 to the input node Nin1.
  • the input switching unit 101 may include switches SW1 to SW4.
  • the switch SW1 is connected between the voltage node NN1 to which the input voltage Vin1 is applied and the input node Nin1.
  • Switch SW2 is connected between voltage node NN1 and input node Nin2.
  • the switch SW3 is connected between the voltage node NN2 to which the input voltage Vin2 is applied and the input node Nin1.
  • Switch SW4 is connected between voltage node NN2 and input node Nin2.
  • the switches SW1 and SW4 are turned on / off in response to the control clock CKc.
  • the switches SW2 and SW3 are turned on / off in response to a control clock CKd (for example, an inverted clock of the control clock CKc).
  • CKd for example, an inverted clock of the control clock CKc.
  • the voltage-current converter 102 has a first current path between the intermediate node N1 and the ground node (a reference node to which the ground voltage GND is applied) and a second current path between the intermediate node N2 and the ground node.
  • a current corresponding to a voltage (either one of the input voltages Vin1 and Vin2) applied to the input node Nin1 is generated in the first current path, and a voltage applied to the input node Nin2 (input voltage Vin1, Vin1) is generated.
  • a current corresponding to the other one of Vin2 is generated in the second current path.
  • the voltage-current converter 102 may include a current source CS, input transistors Tin1, Tin2, and current mirrors CM1, CM2.
  • Current source CS is connected between a power supply node (a reference node to which power supply voltage VDD is applied) and intermediate node N102.
  • the input transistor Tin1 is provided in a current path between the intermediate node N102 and the input end of the current mirror CM1, and generates an input current corresponding to the voltage applied to the input node Nin1.
  • the current mirror CM1 generates a current corresponding to the input current generated by the input transistor Tin1 in the first current path (current path between the intermediate node N1 and the ground node).
  • the input transistor Tin2 is provided in a current path between the intermediate node N102 and the input end of the current mirror CM2, and generates an input current corresponding to the voltage applied to the input node Nin2.
  • the current mirror CM2 generates a current corresponding to the input current generated by the input transistor Tin2 in the second current path (current path between the intermediate node N2 and the ground node).
  • the load transistor 1031 is provided in a third current path between the control node Ncnt (a node to which the control voltage Vcnt is applied) and the intermediate node N1, and supplies a current corresponding to the common voltage Vnc generated at the common node Nc. 3 current paths.
  • the load transistor 1032 is provided in the fourth current path between the control node Ncnt and the intermediate node N2, and generates a current corresponding to the common voltage Vnc generated at the common node Nc in the fourth current path.
  • the load transistors 1031 and 1032 are pMOS transistors.
  • connection switching unit 104 connects the common node Nc to the intermediate node N1 in the first operation mode. Further, the connection switching unit 104 connects the common node Nc to the intermediate node N2 in the second operation mode.
  • the connection switching unit 104 may include switches SW5 and SW6.
  • the switch SW5 is connected between the common node Nc and the intermediate node N1, and switches on / off in response to the control clock CKc.
  • the switch SW6 is connected between the common node Nc and the intermediate node N2, and switches on / off in response to the control clock CKd.
  • the switch SW5 changes from the off state to the on state and the switch SW6 changes from the on state to the off state.
  • the load transistor 1031 enters a diode connection state. That is, the load transistors 1031 and 1032 constitute a load current mirror having the intermediate nodes N1 and N2 as input terminals and output terminals, respectively.
  • the switch SW5 changes from the on state to the off state and the switch SW6 changes from the off state to the on state.
  • the load transistor 1032 is in a diode connection state.
  • the load transistors 1031 and 1032 form a load current mirror having the intermediate nodes N1 and N2 as output terminals and input terminals, respectively. In this way, the input end and the output end of the current mirror constituted by the load transistors 1031 and 1032 are periodically switched.
  • the output switching unit 105 supplies the intermediate voltage V1 generated at the intermediate node N1 to the intermediate node N105 and outputs the intermediate voltage V2 generated at the intermediate node N2 to the output node Nout (output voltage Vout). To the node).
  • the output switching unit 105 supplies the intermediate voltage V1 to the output node Nout and supplies the intermediate voltage V2 to the intermediate node N105.
  • the output switching unit 105 may include switches SW7 to SW10.
  • the switch SW7 is connected between the intermediate node N1 and the output node Nout.
  • Switch SW8 is connected between intermediate node N1 and intermediate node N105.
  • the switch SW9 is connected between the intermediate node N2 and the output node Nout.
  • Switch SW10 is connected between intermediate node N2 and intermediate node N105.
  • the switches SW7 and SW10 are turned on / off in response to a control clock CKd (for example, an inverted clock of the control clock CKc).
  • the switches SW8 and SW9 are turned on / off in response to the control clock CKc.
  • the voltage control unit 106 controls the voltage applied to the intermediate node N105 (any one of the intermediate voltages V1 and V2) to approach the voltage applied to the output node Nout (the other one of the intermediate voltages V1 and V2).
  • the control voltage Vcnt applied to the node Ncnt is controlled.
  • the voltage control unit 106 may include a differential amplifier AMP, a control transistor TC, a capacitor CC, and a resistor RR.
  • the differential amplifier AMP generates an output voltage corresponding to the difference (difference between the intermediate voltages V1 and V2) between the voltage applied to the intermediate node N105 and the voltage applied to the output node Nout.
  • Control transistor TC is provided in a current path between a power supply node (a node to which power supply voltage VDD is applied) and control node Ncnt.
  • the capacitor CC smoothes the output voltage of the differential amplifier AMP.
  • Resistor RR limits the amplification gain of the main differential amplifier so that the amplification gain of the main differential amplifier configured by voltage-current converter 102 and load transistors 1031 and 1032 does not exceed a predetermined upper limit value.
  • the voltage control unit 106 may not include the capacitor CC and the resistor RR.
  • the input switching unit 101 transfers the input voltages Vin1 and Vin2 to the input node.
  • the connection switching unit 104 disconnects the common node Nc from the intermediate node N2 and connects the common node Nc to the intermediate node N1.
  • the load transistors 1031 and 1032 form a load current mirror having the intermediate nodes N1 and N2 as input terminals and output terminals, respectively.
  • the voltage value of the intermediate voltage V1 gradually increases from the convergence value (voltage value Vrd) of the output voltage Vout toward the convergence value (voltage value Vdio) of the common voltage Vnc, and the voltage value of the intermediate voltage V2 is The value gradually decreases from the value Vdio toward the voltage value Vrd. Further, the output switching unit 105 disconnects the output node Nout from the intermediate node N1 and connects the output node Nout to the intermediate node N2. As a result, the output node Nout is charged / discharged by the intermediate voltage V2.
  • the input switching unit 101 causes the input voltages Vin1 and Vin2 to be input.
  • the connection switching unit 104 disconnects the common node Nc from the intermediate node N1 and connects the common node Nc to the intermediate node N2.
  • the load transistors 1031 and 1032 constitute a load current mirror having the intermediate nodes N1 and N2 as output terminals and input terminals, respectively.
  • the voltage value of the intermediate voltage V2 gradually increases from the convergence value (voltage value Vrd) of the output voltage Vout toward the convergence value (voltage value Vdio) of the common voltage Vnc, and the voltage value of the intermediate voltage V1 is The value gradually decreases from the value Vdio toward the voltage value Vrd. Further, the output switching unit 105 disconnects the output node Nout from the intermediate node N2 and connects the output node Nout to the intermediate node N1. As a result, the output node Nout is charged / discharged by the intermediate voltage V1.
  • flicker noise in a portion of the chopper amplifier 1 excluding the input switching unit 101 is an integral multiple of the chopper frequency (frequency of the control clocks CKc and CKb). It can be distributed in the vicinity of harmonics having a frequency.
  • the voltage values of the intermediate voltages V1 and V2 are the convergence value of the common voltage Vnc (voltage value Vdio) and the convergence value of the output voltage Vout (voltage value Vrd). Fluctuate in a complementary manner.
  • the settling time Ts of the output voltage Vout becomes longer than the chopper period (for example, the period from time t1 to t2), the voltage value of the output voltage Vout cannot reach the convergence value (voltage value Vrd) during the chopper period. (The chopper amplifier 1 is not balanced). Therefore, a settling error occurs in the output voltage Vout, and the settling error is included in the output voltage Vout as an offset voltage.
  • the settling error (offset voltage) of the output voltage Vout that occurs when the settling time Ts of the output voltage Vout is shorter than the chopper period increases as the fluctuation range (Vdio ⁇ Vrd) of the output voltage Vout increases.
  • the convergence value (voltage value Vdio) of the common voltage Vnc varies according to the voltage value of the control voltage Vcnt.
  • the convergence value (voltage value Vrd) of the output voltage Vout varies according to the voltage difference between the input voltages Vin1 and Vin2 and the load connected to the output node Nout.
  • control of the control voltage Vcnt in the chopper amplifier 1 will be described with reference to FIG.
  • the mutual conductance values of the load transistors 1031 and 1032 are assumed to be equal to each other.
  • the voltage control unit 106 decreases the voltage value of the control voltage Vcnt according to the difference (V1 ⁇ V2) between the intermediate voltages V1 and V2 during the period from time t1 to time t2, and from time t2 to time t3. In the period, the voltage value of the control voltage Vcnt is decreased according to the difference (V2 ⁇ V1) between the intermediate voltages V1 and V2.
  • the convergence value of the common voltage Vnc decreases from the voltage value Vdio1 to the voltage value Vdio2, and the convergence value of the common voltage Vnc approaches the convergence value of the output voltage Vout.
  • the fluctuation range of the output voltage Vout decreases from the fluctuation range (Vdio1-Vrd) to the fluctuation range (Vdio2-Vrd).
  • the fluctuation range of the output voltage Vout can be reduced by bringing the convergence value of the common voltage Vnc closer to the convergence value of the output voltage Vout. Therefore, the settling error of the output voltage Vout that occurs when the settling time Ts of the output voltage Vout becomes longer than the chopper period can be reduced. Therefore, the offset voltage included in the output voltage Vout can be reduced without being influenced by the response speed of the chopper mechanism. Thereby, as shown in FIG. 4, it is possible to suppress the output voltage Vout from fluctuating due to a temperature change or a power supply voltage fluctuation.
  • FIG. 4 it is possible to suppress the output voltage Vout from fluctuating due to a temperature change or a power supply voltage fluctuation.
  • the dotted line corresponds to the temperature characteristics when the control voltage Vcnt is not controlled (when the control voltage Vcnt is a constant voltage), and the solid line indicates the case where the control voltage Vcnt is controlled by the voltage control unit 106. Corresponds to temperature characteristics.
  • the control voltage corresponding to the power source of the main differential amplifier (the differential amplifier configured by the voltage / current converter 102 and the load transistors 1031 and 1032)
  • noise generated in the voltage controller 106 is reduced. Since it can be reduced by the power supply voltage fluctuation rejection ratio (PSRR) of the main differential amplifier, an increase in noise of the output voltage Vout can be suppressed.
  • PSRR power supply voltage fluctuation rejection ratio
  • the chopper amplifier 1 may be switched from the first operation mode to the second operation mode through the transient mode, and from the second operation mode to the first operation mode through the transient mode.
  • the input switching unit 101 does not supply the input voltages Vin1 and Vin2 to any of the input nodes Nin1 and Nin2, and the connection switching unit 104 connects the common node Nc to any of the intermediate nodes N1 and N2.
  • the output switching unit 105 does not supply the intermediate voltages V1 and V2 to either the intermediate node N105 or the output node Nout.
  • the control clocks CKc and CKd may be non-overlapping clocks whose effective output periods (here, high-level output periods) do not overlap each other.
  • FIG. 5 shows a configuration example of an active filter including the chopper amplifier 1 shown in FIG.
  • the active filter 2 includes a resistor R1 and a capacitor C1 in addition to the chopper amplifier 1.
  • One end of the resistor R1 is connected to the input node N21, and the other end of the resistor R1 is connected to the intermediate node N20.
  • Signal voltages VS21 and VS22 are applied to input nodes N21 and N22, respectively.
  • One end of the capacitor C1 is connected to the intermediate node N20, and the other end of the capacitor C1 is connected to the output node Nout of the chopper amplifier 1.
  • the chopper amplifier 1 receives the intermediate voltage Vn generated at the intermediate node N20 as one of the input voltages Vin1 and Vin2, and receives the signal voltage VS22 applied to the input node N22 as the other of the input voltages Vin1 and Vin2.
  • the function of extracting the intermediate voltage Vn proportional to the amplitude of the signal voltage VS21 (signal extraction function) and the function of outputting the output voltage Vout corresponding to the difference between the intermediate voltage and the signal voltage VS22 (difference) An active filter having an output function can be realized.
  • FIG. 6 shows a first modification of the active filter.
  • the active filter 2a includes a capacitor C2 in addition to the configuration of the active filter 2 shown in FIG.
  • One end of the capacitor C2 is connected to the output node Nout of the chopper amplifier 1, and the other end of the capacitor C2 is connected to a ground node (a reference node to which the ground voltage GND is applied).
  • the other end of the capacitor C1 is connected not to the output node Nout of the chopper amplifier 1 but to the ground node.
  • Other configurations are the same as those in FIG. Even in such a configuration, an active filter having a signal extraction function and a differential output function can be realized.
  • FIG. 7 shows a second modification of the active filter.
  • the active filter 2b includes a resistor R2 in addition to the configuration of the active filter 2 shown in FIG.
  • One end of the resistor R2 is connected to the input node N23, and the other end of the resistor R2 is connected to the intermediate node N20.
  • a signal voltage VS23 is applied to the input node N23.
  • FIG. 8 shows a third modification of the active filter.
  • the active filter 2c includes a resistor R2 in addition to the configuration of the active filter 2a shown in FIG.
  • One end of the resistor R2 is connected to the input node N23, and the other end of the resistor R2 is connected to the intermediate node N20.
  • a signal voltage VS23 is applied to the input node N23. Even in such a configuration, an active filter having a signal extraction function and a differential output function can be realized.
  • FIG. 9 shows a configuration example of a reference frequency generation circuit including the active filter 2 shown in FIG.
  • the reference frequency generation circuit 100 generates reference clocks CKa and CKb, and includes an oscillation circuit 11, an oscillation control circuit 12, a reference voltage generation circuit 13, and a reference control circuit 14.
  • Each of the reference clocks CKa and CKb has a frequency corresponding to the time constant of the oscillation circuit 11, and the respective signal levels fluctuate complementarily.
  • the oscillation circuit 11 increases or decreases the signal levels of the oscillation signals OSCa and OSCb in a complementary manner in response to the transition of the signal levels of the reference clocks CKa and CKb.
  • the oscillation circuit 11 includes capacitors Ca and Cb for generating oscillation signals OSCa and OSCb, constant current sources CS111a and CS111b for supplying constant current, and a switch SW1a for switching the connection state of the capacitors Ca and Cb. , SW2a, SW1b, SW2b (connection switching unit).
  • the oscillation control circuit 12 When the oscillation control circuit 12 detects that the signal level of the oscillation signal OSCa (or the signal level of the oscillation signal OSCb) is higher than the comparison voltage VR, the oscillation control circuit 12 transitions the signal levels of the reference clocks CKa and CKb.
  • the oscillation control circuit 12 includes a comparator CMPa that compares the comparison voltage VR and the signal level of the oscillation signal OSCa, a comparator CMPb that compares the comparison voltage VR and the signal level of the oscillation signal OSCb, and comparators CMPa and CMPb.
  • RS latch circuit 112 which receives output signals OUTa and OUTb and outputs reference clocks CKa and CKb.
  • the reference voltage generation circuit 13 generates a constant voltage having a predetermined voltage difference as the reference voltage Vref with respect to the ground voltage GND.
  • the reference voltage generation circuit 13 includes a band gap reference circuit (BGR) 113 and a constant voltage circuit (pMOS transistor T113, resistors R112, R113, differential amplifier circuit A113).
  • the reference control circuit 14 determines the difference between the signal level of the intermediate signal proportional to the amplitude of each of the oscillation signals OSCa and OSCb (here, the cumulative average voltage of each time constant waveform of the oscillation signals OSCa and OSCb) and the reference voltage Vref.
  • the comparison voltage VR is increased or decreased so as to decrease.
  • the reference control circuit 14 includes switches 114 a and 114 b (switch circuit) and the active filter 2.
  • the switch 114a When the signal level of the reference clock CKb is high, the switch 114a is turned on to pass the oscillation signal OSCa. On the other hand, since the signal level of the reference clock CKa is low, the switch 114b is turned off and cuts off the oscillation signal OSCb. On the other hand, when the signal level of the reference clock CKb is low, the switch 114a is turned off to cut off the oscillation signal OSCa. On the other hand, since the signal level of the reference clock CKa is high, the switch 114a is turned on to pass the oscillation signal OSCb.
  • the respective time constant waveform components of the reference clocks CKa and CKb (the time constant of the oscillation circuit 11). (The waveform component that increases in step) is supplied to the active filter 2.
  • the active filter 2 has a function (signal extraction function) for extracting an intermediate signal proportional to the amplitude of the oscillation signal from the oscillation signals OSCa and OSCb that have passed through the switches 114a and 114b, and the signal level of the intermediate signal and the reference voltage Vref.
  • the active filter 2 receives the oscillation signal Sx (one of the oscillation signals OSCa and OSCb) that has passed through the switches 114a and 114b as the signal voltage VS21 and the reference voltage Vref as the signal voltage VS22.
  • the output voltage Vout is supplied as the comparison voltage VR.
  • the frequency fluctuations of the reference clocks CKa and CKb due to the fluctuation of the delay time can be suppressed.
  • the frequency of the reference clocks CKa and CKb can be increased while suppressing an increase in power consumption (particularly, power consumption of the comparators CMPa and CMPb).
  • a noise component lower than the loop band of the feedback control is attenuated, low frequency noise in the reference frequency generation circuit (for example, low frequency noise of the comparison voltage VR, output noise of the comparators CMPa and CMPb, etc.) ) Can be reduced.
  • the resonance characteristic (Q value) of the reference frequency generating circuit 100 can be improved, and the frequency variation of the reference clocks CKa and CKb can be reduced.
  • the reference voltage generation circuit 13 since the reference voltage generation circuit 13 generates the reference voltage Vref with reference to the ground voltage GND, the reference voltage Vref does not change even if the power supply voltage VDD changes. Therefore, unnecessary fluctuations in the comparison voltage VR are suppressed, and as a result, frequency fluctuations in the reference clocks CKa and CKb caused by fluctuations in the power supply voltage VDD can be suppressed.
  • the chopper operation of the chopper amplifier 1 included in the active filter 2 can disperse flicker noise superimposed on the comparison voltage VR (output voltage Vout) in the vicinity of harmonics having a frequency that is an integral multiple of the chopper frequency. Since the flicker noise dispersed in the harmonics can be attenuated by the active filter 2, the resonance characteristic (Q value) of the reference frequency generation circuit can be further improved.
  • the control voltage in the chopper amplifier 1 it is possible to suppress the occurrence of a settling error in the comparison voltage VR (output voltage Vout). Therefore, as shown in FIG. 10, the reference clock CKa due to a temperature change or a power supply voltage change. , CKb frequency fluctuation can be suppressed.
  • the dotted line corresponds to the temperature characteristic when the control voltage Vcnt is not controlled (when the control voltage Vcnt is a constant voltage), and the solid line corresponds to the temperature characteristic when the control voltage Vcnt is controlled.
  • the chopper amplifier 1 included in the active filter 2 may receive the reference clocks CKa and CKb divided by a frequency dividing circuit (not shown) as control clocks CKc and CKd.
  • the load capacity for example, the signal path of the signal path
  • the chopper amplifier 1 can be improved as compared with the case where the reference clocks CKa and CKb are directly supplied to the chopper amplifier 1 as control clocks CKc and CKd without using a frequency divider.
  • the charge / discharge time of (parasitic capacitance) can be increased. Thereby, since the driving capability of the chopper amplifier 1 can be lowered, the power consumption of the chopper amplifier 1 can be reduced.
  • the chopper amplifier 1 may receive the reference clocks CKa and CKb as they are as the control clocks CKc and CKd without going through the frequency dividing circuit, or the internal signals of the reference frequency generation circuit 100 (for example, the oscillation signals OSCa and OSCb). May be received as control clocks CKc and CKd.
  • reference control circuit 14 may include an active filter 2a shown in FIG. 6 instead of the active filter 2 shown in FIG. 6
  • FIG. 11 shows a first modification of the reference frequency generation circuit.
  • the reference frequency generation circuit 200 includes an oscillation circuit 21, an oscillation control circuit 12, a reference voltage generation circuit 23, and a reference control circuit 24.
  • the oscillation circuit 21 includes resistors R211a and R211b instead of the constant current sources CS111a and CS111b shown in FIG.
  • resistors R211a and R211b instead of the constant current sources CS111a and CS111b shown in FIG.
  • 1 / f noise noise component inversely proportional to the frequency generated in the constant current source
  • the frequency stability of the reference clocks CKa and CKb can be improved compared to the generation circuit 100.
  • the resistors R211a and R211b have less aging degradation than the constant current sources CS111a and CS111b, the reference clocks CKa and CKb can be accurately generated over a long period of time.
  • the reference voltage generation circuit 23 includes resistors R212 and R213. Resistors R212 and R213 generate reference voltage Vref by dividing resistance between power supply voltage VDD and ground voltage GND.
  • the reference control circuit 24 includes resistors 211a and 211b instead of the switches 114a and 114b shown in FIG.
  • One end of each of the resistors 211a and 211b is connected to the active filter 2, and an oscillation signal OSCa is supplied to the other end of the resistor 211a, and an oscillation signal OSCb is supplied to the other end of the resistor 211b.
  • the active filter 2 receives the oscillation signal Sx (a signal generated by resistance-dividing the oscillation signals OSCa and OSCb by the resistors 211a and 211b) as the signal voltage VS21 and the reference voltage Vref as the signal voltage VS22.
  • the output voltage Vout of the active filter 2 is supplied as the comparison voltage VR.
  • the reference control circuit 24 may include an active filter 2a shown in FIG. 6 instead of the active filter 2 shown in FIG.
  • the reference frequency generation circuit 200 may include the reference control circuit 14 shown in FIG. 9 instead of the reference control circuit 24 shown in FIG. 11, or the active filter 2b shown in FIGS. , 2c may be provided as a reference control circuit.
  • the active filters 2b and 2c receive the oscillation signals OSCa and OSCb as the signal voltages VS21 and VS23, respectively, receive the reference voltage Vref as the signal voltage VS22, and supply the output voltage Vout of the active filters 2b and 2c as the comparison voltage VR. May be.
  • the reference frequency generation circuit 200 may include the reference voltage generation circuit 13 shown in FIG. 9 instead of the reference voltage generation circuit 23 shown in FIG.
  • FIG. 12 shows a second modification of the reference frequency generation circuit.
  • the reference frequency generation circuit 300 includes an oscillation circuit 31, an oscillation control circuit 32, a reference voltage generation circuit 13, and a reference control circuit (active filter 2).
  • the reference clock CK has a frequency corresponding to the time constant of the oscillation circuit 31.
  • the oscillation circuit 31 increases or decreases the signal level of the oscillation signal OSCa in response to the transition of the signal level of the reference clock CK.
  • the oscillation circuit 31 includes a capacitor Ca, a constant current source CS111a, and switches SW1a and SW2a.
  • the oscillation control circuit 32 detects that the signal level of the oscillation signal OSCa is higher than the comparison voltage VR, the oscillation control circuit 32 changes the reference clock CK from the low level to the high level, and sets the reference clock CK to the high level after a predetermined time has elapsed. Transition from low to low.
  • the oscillation control circuit 32 includes a comparator CMPa and a delay circuit 311.
  • the reference control circuit compares the reference voltage Vref so that the difference between the signal level of the intermediate signal proportional to the amplitude of the oscillation signal OSCa (here, the cumulative average voltage of the oscillation signal OSCa) and the reference voltage Vref is small. Increase or decrease VR.
  • the reference control unit is composed of an active filter 2, and the active filter 2 receives the oscillation signal OSCa as the signal voltage VS21 and the reference voltage Vref as the signal voltage VS22.
  • the output voltage Vout of the active filter 2 is , And supplied as a comparison voltage VR.
  • the reference frequency generation circuit 300 may include the active filter 2a illustrated in FIG. 6 instead of the active filter 2 illustrated in FIG.
  • the polarities of the chopper amplifier 1, the active filters 2, 2a, 2b, and 2c, and the reference frequency generation circuits 100, 200, and 300 may be reversed.
  • the load transistors 1031, 1032, the input transistors Tin1, Tin2, and the control transistor TC are configured by nMOS transistors
  • the current mirrors CM1, CM2 are configured by pMOS transistors
  • the power supply node The reference node to which the power supply voltage VDD is applied and the ground node (node to which the ground voltage GND is applied) may be interchanged.
  • the above-described chopper amplifier can reduce the offset voltage included in the output voltage without being affected by the response speed of the chopper mechanism and can suppress an increase in noise in the output voltage. Useful as.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

Dans un premier mode opératoire de l'invention, une unité de commutation d'entrée (101) fournit des tensions d'entrée (Vin1, Vin2) aux nœuds d'entrée (Nin1, Nin2) respectivement, une unité de commutation de connexion (104) relie un nœud commun (Nc) à un nœud intermédiaire (N1), et une unité de commutation de sortie (105) fournit des tensions intermédiaires (V1, V2) à un nœud intermédiaire (N105) et à un nœud de sortie (Nout) respectivement. Dans un deuxième mode opératoire de l'invention, l'unité de commutation d'entrée (101) fournit les tensions d'entrée (Vin1, Vin2) aux nœuds d'entrée (Nin1, Nin2) respectivement, et l'unité de commutation de connexion (104) relie le nœud commun (Nc) au nœud intermédiaire (N1), et l'unité de commutation de sortie (105) fournit les tensions intermédiaires (V1, V2) au nœud de sortie (Nout) et au nœud intermédiaire (N105) respectivement. Une unité de commande de tension (106) gère une tension de commande (Vout) de manière que la tension appliquée au nœud intermédiaire (N105) soit proche de celle appliquée au nœud de sortie (Nout).
PCT/JP2011/003475 2010-10-19 2011-06-17 Amplificateur à hacheur, filtre actif et circuit générateur de fréquence de référence WO2012053133A1 (fr)

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JP2010234846 2010-10-19

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2015037532A1 (ja) * 2013-09-13 2017-03-02 アルプス電気株式会社 増幅回路
US11323083B2 (en) 2018-04-27 2022-05-03 Panasonic Intellectual Property Management Co., Ltd. Amplifier circuit
WO2022254995A1 (fr) * 2021-05-31 2022-12-08 ローム株式会社 Circuit d'amplification, circuit d'alimentation à découpage et dispositif d'alimentation à découpage

Citations (5)

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Publication number Priority date Publication date Assignee Title
JP2002530916A (ja) * 1998-11-12 2002-09-17 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 増幅器により発生するｄｃオフセット及びノイズを減少させる手段を有する回路
JP2003218698A (ja) * 2002-01-25 2003-07-31 Sony Corp 並列型ａｄ変換器
JP2007074670A (ja) * 2005-09-09 2007-03-22 Nec Electronics Corp 差動増幅回路および半導体装置
JP2008067050A (ja) * 2006-09-07 2008-03-21 Handotai Rikougaku Kenkyu Center:Kk 帰還型増幅回路
WO2009035665A1 (fr) * 2007-09-14 2009-03-19 Analog Devices, Inc. Système d'amplificateur basse puissance et à faible bruit amélioré

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002530916A (ja) * 1998-11-12 2002-09-17 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 増幅器により発生するｄｃオフセット及びノイズを減少させる手段を有する回路
JP2003218698A (ja) * 2002-01-25 2003-07-31 Sony Corp 並列型ａｄ変換器
JP2007074670A (ja) * 2005-09-09 2007-03-22 Nec Electronics Corp 差動増幅回路および半導体装置
JP2008067050A (ja) * 2006-09-07 2008-03-21 Handotai Rikougaku Kenkyu Center:Kk 帰還型増幅回路
WO2009035665A1 (fr) * 2007-09-14 2009-03-19 Analog Devices, Inc. Système d'amplificateur basse puissance et à faible bruit amélioré

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2015037532A1 (ja) * 2013-09-13 2017-03-02 アルプス電気株式会社 増幅回路
US11323083B2 (en) 2018-04-27 2022-05-03 Panasonic Intellectual Property Management Co., Ltd. Amplifier circuit
WO2022254995A1 (fr) * 2021-05-31 2022-12-08 ローム株式会社 Circuit d'amplification, circuit d'alimentation à découpage et dispositif d'alimentation à découpage

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