WO2012029661A1 - Procédé de fabrication d'un dispositif à semi-conducteurs et dispositif de traitement de substrat - Google Patents

Procédé de fabrication d'un dispositif à semi-conducteurs et dispositif de traitement de substrat Download PDF

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Publication number
WO2012029661A1
WO2012029661A1 PCT/JP2011/069319 JP2011069319W WO2012029661A1 WO 2012029661 A1 WO2012029661 A1 WO 2012029661A1 JP 2011069319 W JP2011069319 W JP 2011069319W WO 2012029661 A1 WO2012029661 A1 WO 2012029661A1
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Prior art keywords
silicon
containing gas
gas
substrate
growth
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PCT/JP2011/069319
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English (en)
Japanese (ja)
Inventor
保信 越
圭吾 西田
前田　喜世彦
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株式会社日立国際電気
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Priority to JP2012531844A priority Critical patent/JP5393895B2/ja
Publication of WO2012029661A1 publication Critical patent/WO2012029661A1/fr
Priority to US14/597,372 priority patent/US9666430B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02592—Microstructure amorphous
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/02—Pretreatment of the material to be coated
    • C23C16/0227—Pretreatment of the material to be coated by cleaning or etching
    • C23C16/0236—Pretreatment of the material to be coated by cleaning or etching by etching with a reactive gas
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/24—Deposition of silicon only
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523—Pulsed gas flow or change of composition over time
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523—Pulsed gas flow or change of composition over time
    • C23C16/45525—Atomic layer deposition [ALD]
    • C23C16/45544—Atomic layer deposition [ALD] characterized by the apparatus
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/52—Controlling or regulating the coating process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD

Definitions

  • the present invention relates to a semiconductor device manufacturing method and a substrate processing apparatus including a step of processing a substrate, and more particularly to a semiconductor device manufacturing method and a substrate processing apparatus characterized by forming a silicon film.
  • TCAT Transmissionbit Cell Array Transistor
  • BICS Bit-Cost Scalable
  • the surface roughness (surface roughness, Rms) of the silicon film becomes a problem, and it may be difficult to maintain high carrier mobility.
  • Rms surface roughness
  • Patent Document 1 after a silicon film is formed, the surface of the silicon film is polished using an abrasive to form a silicon film having a flat surface.
  • the nucleation growth suppressing step and the nucleation step are defined as one cycle, and a silicon film is formed by repeating two or more cycles,
  • a method for manufacturing a semiconductor device is provided in which the time required for the nucleus growth suppressing step is equal to or shorter than the time required for the nucleus forming step.
  • a processing chamber for processing the substrate A chlorine-containing gas supply system for supplying at least a chlorine-containing gas into the processing chamber; A silicon-containing gas supply system for supplying at least a silicon-containing gas into the processing chamber; A nuclear growth suppression step in which the silicon-containing gas supply system supplies at least the silicon-containing gas into the processing chamber, and the chlorine-containing gas supply system supplies the chlorine-containing gas into the processing chamber to suppress the growth of the nuclei; A nucleation step of forming nuclei on the substrate.
  • the nucleation growth suppression step and the nucleation step are defined as one cycle, and this cycle is repeated two or more cycles.
  • a controller that is controlled to form a silicon film that is set below the time required for the formation process; A substrate processing apparatus is provided.
  • the present invention it is possible to suppress deterioration of the quality of the substrate and the performance of the semiconductor device.
  • 1 is a perspective view of a semiconductor manufacturing apparatus 10 to which a first embodiment of the present invention is applied.
  • 1 is a side sectional view of a processing furnace 202 of a semiconductor manufacturing apparatus 10 to which a first embodiment of the present invention is applied, and a control configuration of each part.
  • 1 is a schematic diagram of a processing furnace 202 and its peripheral structure of a semiconductor manufacturing apparatus 10 to which a first embodiment of the present invention is applied. It is a schematic diagram which shows the state of the board
  • FIG. 1 is a perspective view showing an example of a semiconductor manufacturing apparatus 10 as a substrate processing apparatus according to a first embodiment of the present invention.
  • This semiconductor manufacturing apparatus 10 is a batch type vertical heat treatment apparatus, and has a casing 12 in which a main part is arranged.
  • the semiconductor manufacturing apparatus 10 includes a hoop (hereinafter referred to as a pod) 16 as a substrate container that stores a wafer 200 as a substrate made of, for example, Si (silicon, silicon) or SiC (silicon carbide, silicon carbide). Used as a wafer carrier.
  • a pod stage 18 is disposed on the front side of the housing 12, and the pod 16 is conveyed to the pod stage 18. For example, 25 wafers 200 are stored in the pod 16 and placed on the pod stage 18 with the lid closed.
  • a pod transfer device 20 is arranged at a position facing the pod stage 18 on the front side in the housing 12. Further, a pod shelf 22, a pod opener 24, and a substrate number detector 26 are disposed in the vicinity of the pod transfer device 20.
  • the pod shelf 22 is disposed above the pod opener 24 and configured to hold a plurality of pods 16 mounted thereon.
  • the substrate number detector 26 is disposed adjacent to the pod opener 24.
  • the pod carrying device 20 carries the pod 16 among the pod stage 18, the pod shelf 22, and the pod opener 24.
  • the pod opener 24 opens the lid of the pod 16, and the substrate number detector 26 detects the number of wafers 200 in the pod 16 with the lid opened.
  • the substrate transfer machine 28 has an arm (tweezer) 32 and has a structure that can be rotated up and down by a driving means (not shown).
  • the arm 32 can take out, for example, five wafers 200, and the wafers 200 are transferred between the pod 16 and the boat 217 placed at the position of the pod opener 24 by moving the arm 32.
  • FIG. 2 is a schematic configuration diagram of the processing furnace 202 of the substrate processing apparatus preferably used in the embodiment of the present invention, and is shown as a longitudinal sectional view.
  • the processing furnace 202 has a heater 206 as a heating mechanism.
  • the heater 206 has a cylindrical shape, for example, a cylindrical shape, and is vertically installed by being supported by a heater base as a holding plate (not shown).
  • a process tube 203 as a reaction tube is disposed inside the heater 206 concentrically with the heater 206.
  • the process tube 203 is composed of an inner tube 204 as an internal reaction tube and an outer tube 205 as an external reaction tube provided on the outside thereof.
  • the inner tube 204 is made of a heat-resistant material such as quartz (SiO 2 ) or silicon carbide (SiC), and is formed in a cylindrical shape with an upper end and a lower end opened.
  • a processing chamber 201 is formed in a cylindrical hollow portion of the inner tube 204, and is configured to be able to accommodate wafers 200 as substrates in a state where they are arranged in multiple stages in a horizontal posture and in a vertical direction by a boat 217 described later.
  • the outer tube 205 is made of a heat-resistant material such as quartz or silicon carbide, has an inner diameter larger than the outer diameter of the inner tube 204, is formed in a cylindrical shape with the upper end closed and the lower end opened. It is provided concentrically with the tube 204.
  • a manifold 209 is disposed concentrically with the outer tube 205.
  • the manifold 209 is made of, for example, stainless steel and is formed in a cylindrical shape with an upper end and a lower end opened.
  • the manifold 209 is engaged with the inner tube 204 and the outer tube 205, and is provided so as to support them.
  • An O-ring 220a as a seal member is provided between the manifold 209 and the outer tube 205. Since the manifold 209 is supported by a heater base (not shown), the process tube 203 is installed vertically.
  • a reaction vessel is mainly formed by the process tube 203 and the manifold 209.
  • Nozzles 230a, 230b, and 230c as gas introduction portions are connected to the manifold 209 so as to communicate with the inside of the processing chamber 201, and gas supply pipes 232a, 232b, and 232c are connected to the nozzles 230a, 230b, and 230c, respectively. ing.
  • MFCs mass flow controllers, Mass Flow Controllers
  • a silicon-containing gas source 300a, a chlorine-containing gas source 300b, and an inert gas source 300c are connected through valves 310a, 310b, and 310c as opening / closing devices.
  • a gas flow rate control unit 235 is electrically connected to the MFCs 241a, 241b, and 241c, and is configured to control at a desired timing so that the flow rate of the supplied gas becomes a desired amount.
  • the nozzle 230 a that supplies, for example, disilane (Si 2 H 6 ) gas as the silicon-containing gas is made of, for example, quartz, and is provided in the manifold 209 so as to penetrate the manifold 209. At least one nozzle 230 a is provided, and is provided in a region below the region facing the heater 206 and facing the manifold 209, and configured to supply the silicon-containing gas into the processing chamber 201.
  • the nozzle 230a is connected to the gas supply pipe 232a.
  • This gas supply pipe 232a is connected to a silicon-containing gas source 300a that supplies, for example, disilane (Si 2 H 6 ) gas as a silicon-containing gas via a mass flow controller 241a as a flow rate controller (flow rate control means) and a valve 310a.
  • a silicon-containing gas source 300a that supplies, for example, disilane (Si 2 H 6 ) gas as a silicon-containing gas via a mass flow controller 241a as a flow rate controller (flow rate control means) and a valve 310a.
  • a silicon-containing gas supply system as a gas supply system is mainly configured by the silicon-containing gas source 300a, the valve 310a, the mass flow controller 241a, the gas supply pipe 232a, and the nozzle 230a.
  • the nozzle 230 b that supplies, for example, dichlorosilane (SiH 2 Cl 2 ) gas as the chlorine-containing gas is made of, for example, quartz, and is provided in the manifold 209 so as to penetrate the manifold 209. At least one nozzle 230b is provided, is provided in a region below the region facing the heater 206 and facing the manifold 209, and is configured to supply a chlorine-containing gas into the processing chamber 201.
  • the nozzle 230b is connected to the gas supply pipe 232b.
  • the gas supply pipe 232b is connected to a chlorine-containing gas source 300b that supplies, for example, dichlorosilane gas as a chlorine-containing gas via a mass flow controller 241b as a flow rate controller (flow rate control means) and a valve 310b.
  • a chlorine-containing gas supply system as a gas supply system is mainly configured by the chlorine-containing gas source 300b, the valve 310b, the mass flow controller 241b, the gas supply pipe 232b, and the nozzle 230b.
  • the nozzle 230 c that supplies, for example, nitrogen (N 2 ) gas as an inert gas is made of, for example, quartz, and is provided in the manifold 209 so as to penetrate the manifold 209. At least one nozzle 230 c is provided, is provided in a region below the region facing the heater 206 and facing the manifold 209, and is configured to supply an inert gas into the processing chamber 201.
  • the nozzle 230c is connected to the gas supply pipe 232d.
  • the gas supply pipe 232c is connected to an inert gas source 300c that supplies, for example, nitrogen gas as an inert gas via a mass flow controller 241c as a flow rate controller (flow rate control means) and a valve 310c.
  • An inert gas supply system as a gas supply system is mainly configured by the inert gas source 300c, the valve 310c, the mass flow controller 241c, the gas supply pipe 232c, and the nozzle 230c.
  • a gas supply amount control unit 235 is electrically connected to the valves 310a, 310b, 310c and the mass flow controllers 241a, 241b, 241c, so that a gas supply amount, a gas supply start, a gas supply stop, etc. can be performed at a desired timing. Configured to control.
  • the nozzles 230a, 230b, and 230c are provided in the region facing the manifold 209.
  • the present invention is not limited to this.
  • at least a part of the nozzles 230a, 230b, and 230c is provided in the region facing the heater 206.
  • a chlorine-containing gas or an inert gas may be supplied in the wafer processing region.
  • the gas supply position may be extended to the wafer processing region, so that the gas can be supplied near the wafer from one or more positions.
  • nozzles may be provided in either the area facing the manifold 209 or the area facing the heater 206.
  • the disilane gas is exemplified as the silicon-containing gas.
  • the present invention is not limited to this.
  • a higher order silane gas such as silane (SiH 4 ) gas or trisilane (Si 3 H 8 ) gas may be used.
  • SiH 4 silane
  • Si 3 H 8 trisilane
  • dichlorosilane (SiH 2 Cl 2) gas as the chlorine-containing gas is not limited thereto, for example, trichlorosilane (SiHCl 3) gas and tetrachlorosilane (SiCl 4) chlorosilane such as a gas
  • trichlorosilane (SiHCl 3) gas and tetrachlorosilane (SiCl 4) chlorosilane such as a gas
  • chlorine (Cl 2 ) gas, hydrogen chloride (HCl) gas, or the like may be used, or a combination thereof may be used.
  • nitrogen (N 2 ) gas is exemplified as the inert gas.
  • the present invention is not limited thereto, and examples thereof include rare gases such as helium (He) gas, neon (Ne) gas, and argon (Ar) gas.
  • nitrogen gas and these rare gases may be used in combination.
  • the manifold 209 is provided with an exhaust pipe 231 for exhausting the atmosphere in the processing chamber 201.
  • the exhaust pipe 231 is disposed at the lower end portion of the cylindrical space 250 formed by the gap between the inner tube 204 and the outer tube 205 and communicates with the cylindrical space 250.
  • a vacuum exhaust device 246 such as a vacuum pump is connected to the downstream side of the exhaust pipe 231 opposite to the connection side with the manifold 209 via a pressure sensor 245 as a pressure detector and a pressure adjusting device 242.
  • the processing chamber 201 can be evacuated so that the pressure in the processing chamber 201 becomes a predetermined pressure (degree of vacuum).
  • a pressure control unit 236 is electrically connected to the pressure adjusting device 242 and the pressure sensor 245.
  • the pressure control unit 236 is configured to control the pressure adjusting device 242 at a desired timing so that the pressure in the processing chamber 201 becomes a desired pressure based on the pressure detected by the pressure sensor 245. .
  • a seal cap 219 is provided as a furnace opening lid capable of airtightly closing the lower end opening of the manifold 209.
  • the seal cap 219 is brought into contact with the lower end of the manifold 209 from the lower side in the vertical direction.
  • the seal cap 219 is made of, for example, a metal such as stainless steel and is formed in a disk shape.
  • an O-ring 220b is provided as a seal member that comes into contact with the lower end of the manifold 209.
  • a rotation mechanism 254 that rotates the boat 217 is installed on the side of the seal cap 219 opposite to the processing chamber 201.
  • a rotation shaft 255 of the rotation mechanism 254 passes through the seal cap 219 and is connected to a boat 217 described later, and is configured to rotate the wafer 200 by rotating the boat 217.
  • the seal cap 219 is configured to be lifted vertically by a boat elevator 115 as a lifting mechanism vertically installed outside the process tube 203, and thereby the boat 217 is carried into and out of the processing chamber 201. It is possible to do.
  • a drive control unit 237 is electrically connected to the rotation mechanism 254 and the boat elevator 115, and is configured to control at a desired timing so as to perform a desired operation.
  • the boat 217 as a substrate holder is made of a heat-resistant material such as quartz or silicon carbide, and holds a plurality of wafers 200 in a horizontal posture and aligned in a state where the centers are aligned with each other in multiple stages. It is configured.
  • a plurality of heat insulating plates 216 made of a heat-resistant material such as quartz or silicon carbide and having a disk shape are arranged in a multi-stage in a horizontal posture at the lower portion of the boat 217. The heat from 206 is difficult to be transmitted to the manifold 209 side.
  • a temperature sensor 263 is installed as a temperature detector.
  • a temperature controller 238 is electrically connected to the heater 206 and the temperature sensor 263, and by adjusting the power supply to the heater 206 based on the temperature information detected by the temperature sensor 263, Control is performed at a desired timing so that the temperature has a desired temperature distribution.
  • the gas flow rate control unit 235, the pressure control unit 236, the drive control unit 237, and the temperature control unit 238 also constitute an operation unit and an input / output unit, and are electrically connected to a main control unit 239 that controls the entire substrate processing apparatus. ing. These gas flow rate control unit 235, pressure control unit 236, drive control unit 237, temperature control unit 238, and main control unit 239 are configured as a controller 240.
  • the boat 217 holding the plurality of wafers 200 is lifted by the boat elevator 115 and processed in the processing chamber 201. It is carried in (boat loading). In this state, the seal cap 219 seals the lower end of the manifold 209 via the O-ring 220b.
  • the processing chamber 201 is evacuated by the evacuation device 246 so as to have a desired pressure (degree of vacuum). At this time, the pressure in the processing chamber 201 is measured by the pressure sensor 245, and feedback control is performed by the pressure regulator 242 based on the measured pressure. In addition, the heater 206 is heated so that the inside of the processing chamber 201 has a desired temperature. At this time, the power supply to the heater 206 is feedback-controlled based on the temperature information detected by the temperature sensor 263 so that the inside of the processing chamber 201 has a desired temperature distribution. Subsequently, the wafer 200 is rotated by rotating the boat 217 by the rotation mechanism 254.
  • a silicon-containing gas is supplied as a processing gas from a silicon-containing gas supply source 300a.
  • the silicon-containing gas controlled to have a desired flow rate by the MFC 241a is introduced into the processing chamber 201 from the nozzle 230a through the gas supply pipe 232a.
  • the introduced silicon-containing gas rises in the processing chamber 201, flows out from the upper end opening of the inner tube 204 into the cylindrical space 250, and is exhausted from the exhaust pipe 231.
  • the silicon-containing gas contacts the surface of the wafer 200 when passing through the processing chamber 201, and at this time, a film, for example, a silicon film is deposited on the wafer 200 by a thermal CVD reaction.
  • the inert gas is supplied from the inert gas supply source 300c so as to have a desired flow rate by the MFC 241c, and the inside of the processing chamber 201 is replaced with the inert gas.
  • the pressure in the processing chamber 201 is restored to normal pressure.
  • the seal cap 219 is lowered by the boat elevator 115, the lower end of the manifold 209 is opened, and the processed wafer 200 is carried out from the lower end of the manifold 209 to the outside of the process tube 203 while being held by the boat 217 ( Boat unloading). Thereafter, the processed wafer 200 is taken out from the boat 217 (wafer discharge).
  • a target film is formed on the substrate in the following procedure as one step of the manufacturing process of the semiconductor device.
  • FIG. 4 is a schematic diagram showing the state of the substrate in each step in the first embodiment.
  • a silicon film having a predetermined film thickness is formed on a wafer 200 serving as a substrate by supplying a chlorine-containing gas and a silicon-containing gas.
  • a silicon film having a predetermined thickness can be formed while controlling the in-plane distribution of the silicon film formed on the wafer surface. Details will be described below.
  • This step is a step of suppressing local silicon growth by removing a part of nuclei (impurities existing on the initial substrate, formed silicon nuclei, etc.) and suppressing growth.
  • a chlorine-containing gas is supplied for a predetermined time, and as shown in FIG. 4B, the silicon nucleus formed in FIG. The growth is suppressed, and some silicon nuclei are detached from the wafer 200 to control the growth of silicon nuclei.
  • chlorine-containing gas is exemplified dichlorosilane (SiH 2 Cl 2) gas, not limited to this, for example, trichlorosilane (SiHCl 3) gas and tetrachlorosilane (SiCl 4) may be used gas and Further, chlorine (Cl 2 ) gas, hydrogen chloride (HCl) gas, or the like may be used, or a combination thereof may be used.
  • dichlorosilane (SiH 2 Cl 2) gas not limited to this, for example, trichlorosilane (SiHCl 3) gas and tetrachlorosilane (SiCl 4) may be used gas and Further, chlorine (Cl 2 ) gas, hydrogen chloride (HCl) gas, or the like may be used, or a combination thereof may be used.
  • the processing conditions when processing the wafer 200 in the processing chamber 201 of the present embodiment that is, the processing conditions when controlling the silicon nucleus growth by dichlorosilane gas on the wafer 200 are as follows: Processing temperature: 300 ° C. or more and 500 ° C. or less, Processing pressure: 10 Pa or more and 1330 Pa or less, Dichlorosilane gas supply flow rate: 10 sccm or more and 5000 sccm or less, By maintaining each processing condition constant at a certain value within each range, the growth of silicon nuclei on the wafer 200 can be suppressed.
  • This step is a step of forming silicon nuclei on the substrate.
  • the nucleus can be formed so as to spread the silicon nucleus on the substrate.
  • a film forming process for forming, for example, an amorphous silicon (amorphous silicon) film on a wafer 200 as a substrate composed of silicon or the like will be described.
  • at least a silicon-containing gas is supplied into the processing chamber 201 for a predetermined time to form silicon nuclei on the wafer 200.
  • silicon-containing gas examples include silane gas (SiH 4 gas), disilane gas (Si 2 H 6 gas), and the like, and a combination thereof may be used.
  • the processing conditions when processing the wafer 200 in the processing chamber 201 of the present embodiment are as follows: Processing temperature: 300 ° C. or more and 500 ° C. or less, Processing pressure: 10 Pa or more and 1330 Pa or less, Disilane gas supply flow rate: 10 sccm or more and 5000 sccm or less, A silicon nucleus is formed on the wafer 200 by maintaining each processing condition constant at a certain value within each range.
  • nucleation step which is a step of forming silicon nuclei on the substrate
  • new silicon nuclei are formed as shown in FIG.
  • the nucleation growth suppressing step (FIG. 4B) and the nucleation step (FIG. 4C) are set as one cycle, and this cycle is repeated two or more cycles, whereby as shown in FIG. Silicon nuclei are uniformly formed thereon, and the formed silicon nuclei are grown, whereby a silicon film is formed on the wafer 200.
  • the silicon nucleus formed on the wafer 200 is further coarsened by supplying a silicon-containing gas and grows into a silicon film. However, when the silicon nuclei grow coarse and grow into a silicon film, the silicon nuclei that were formed first start growing faster, while other parts where no silicon nuclei are formed are delayed. Since nuclei are formed, there is a difference in the size of silicon nuclei formed on the wafer 200. When a difference occurs in the size of the silicon nucleus, a difference occurs in the in-plane distribution of the film thickness of the silicon film formed on the wafer 200.
  • the first silicon-containing gas is first supplied for a predetermined time, and then the chlorine-containing gas is supplied, whereby the first silicon-containing gas is supplied on the wafer 200.
  • the coarsening of the silicon nuclei formed in is delayed.
  • silicon nuclei are formed at predetermined locations on the wafer 200 where silicon nuclei were not formed at the first time by supplying the silicon-containing gas from the second time on for a predetermined time.
  • the silicon nuclei can be uniformly formed on the wafer 200, and the uniformly formed silicon nuclei are controlled and grown.
  • the formed silicon film can be formed with good in-plane film thickness uniformity.
  • a silicon oxide film is preferably formed on the wafer 200, and the amorphous silicon film 710 is preferably formed on the silicon oxide film formed on the wafer 200 by the above-described method.
  • the adhesion between the formed amorphous silicon film 710 and the silicon oxide film is increased, it is possible to reduce deterioration of the performance of the semiconductor device to be formed and to suppress a decrease in throughput. .
  • pretreatment is performed before the nucleation step.
  • pretreatment is performed before the nucleation step.
  • a step of vacuum replacement or nitrogen gas replacement of the inside of the reaction furnace may be provided between the nucleation growth suppressing step and the nucleation step. Thereby, the gas supplied by each process can be made to react efficiently.
  • the film formation by the CVD method has been described.
  • the present invention is not limited thereto, and for example, an ALD (Atomic Layer Deposition) method may be used.
  • the supply of the processing gas is stopped, the inert gas is supplied from the inert gas supply source, the inside of the processing chamber 201 is replaced with the inert gas, and the pressure in the processing chamber 201 is normal pressure. Returned to
  • the seal cap 219 is lowered by the elevating motor 122 so that the lower end of the manifold 209 is opened, and the boat 217 holding the processed wafer 200 is unloaded from the lower end of the manifold 209 to the outside of the processing chamber 201 (boat unloading).
  • the boat 217 waits at a predetermined position until all the wafers 200 supported by the boat 217 are cooled.
  • the wafer 200 of the waiting boat 217 is cooled to a predetermined temperature
  • the wafer 200 is taken out from the boat 217 by the substrate (wafer) transfer device 28 and transferred to the empty pod 16 set in the pod opener 24. And accommodate.
  • the pod 16 containing the wafer 200 is transferred to the pod shelf 22 or the pod stage 18 by the pod transfer device 20. In this way, a series of operations of the semiconductor manufacturing apparatus 10 is completed.
  • FIG. 5 shows a film formation result of the silicon film formed by the above method.
  • the displayed sample data are the results when the time required for the nucleation process is X [sec.] And the time required for the nucleation suppression process is 0.4X, X, 2X [sec.]. It is.
  • the vertical axis in FIG. 5 indicates the film thickness value [ ⁇ ] of the silicon film formed under each condition on the right side, and the in-plane deviation value [ ⁇ ] indicating the in-plane distribution of the wafer on the left side. Indicates the ratio [ ⁇ ] divided by “time required for the nucleation process” divided by “time required for the nucleation process”.
  • the in-plane deviation value indicates the difference between the measured maximum film thickness value and the minimum film thickness value on the wafer. A small in-plane deviation value indicates that the formed film is uniformly formed on the wafer.
  • the time required for the nucleus growth suppression process is relatively longer than “the time required for the nucleus formation process”, that is, the film deposition rate gradually decreases as the left side in FIG. I understand.
  • the in-plane deviation value gradually increases as the “time required for the nucleation suppression step” becomes longer than the “time required for the nucleation step” (when the time ratio in the figure exceeds 1.0).
  • a silicon film having a small in-plane deviation value can be formed when the ratio between the “time required for the nucleus growth suppression process” and the “time required for the nucleus formation process” is 0.4 or more and 1 or less.
  • a silicon film having a good in-plane distribution of film thickness can be formed.
  • an insulating film made of silicon can be formed uniformly.
  • the time required for the nucleus growth suppressing step is 0.4 times or more and 1 time or less with respect to the time required for the nucleation step.
  • good step coverage can be obtained.
  • a semiconductor device having good performance can be stably manufactured, and throughput can be improved.
  • the second embodiment is a modification of the first embodiment, and is a film forming method in which the nucleus growth step is performed after one cycle of the nucleus growth suppression step and the nucleus formation step, and this cycle is repeated two or more cycles. . Details will be described below.
  • chlorine-containing gas is exemplified dichlorosilane (SiH 2 Cl 2) gas, not limited to this, for example, trichlorosilane (SiHCl 3) gas and tetrachlorosilane (SiCl 4) may be used gas and Further, chlorine (Cl 2 ) gas, hydrogen chloride (HCl) gas, or the like may be used, or a combination thereof may be used.
  • dichlorosilane (SiH 2 Cl 2) gas not limited to this, for example, trichlorosilane (SiHCl 3) gas and tetrachlorosilane (SiCl 4) may be used gas and Further, chlorine (Cl 2 ) gas, hydrogen chloride (HCl) gas, or the like may be used, or a combination thereof may be used.
  • the processing conditions when processing the wafer 200 in the processing chamber 201 of the present embodiment that is, the processing conditions when controlling the silicon nucleus growth by dichlorosilane gas on the wafer 200 are as follows: Processing temperature: 300 ° C. or more and 500 ° C. or less, Processing pressure: 10 Pa or more and 1330 Pa or less, Dichlorosilane gas supply flow rate: 10 sccm or more and 5000 sccm or less, In this case, the growth of silicon nuclei formed on the wafer 200 can be suppressed by maintaining each processing condition constant at a certain value within each range.
  • a film forming process for forming, for example, an amorphous silicon (amorphous silicon) film 710 on a wafer 200 as a substrate composed of silicon or the like will be described.
  • at least a silicon-containing gas is supplied into the processing chamber 201 for a predetermined time to form silicon nuclei on the wafer 200.
  • silicon-containing gas examples include silane gas (SiH 4 gas), disilane gas (Si 2 H 6 gas), and the like, and a combination thereof may be used.
  • the processing conditions when processing the wafer 200 in the processing chamber 201 of the present embodiment are as follows: Processing temperature: 300 ° C. or more and 500 ° C. or less, Processing pressure: 10 Pa or more and 1330 Pa or less, Disilane gas supply flow rate: 10 sccm or more and 5000 sccm or less, In this case, silicon nuclei are formed on the wafer 200 by keeping the respective processing conditions constant at a certain value within the respective ranges.
  • the nucleus growth process is a process in which a nucleus growth suppression process and a nucleus formation process are defined as one cycle, and after performing this cycle two or more cycles, silicon nuclei spread on the substrate are grown.
  • a silicon-containing gas is supplied for a predetermined time, and the formed silicon nuclei are grown to form a silicon film.
  • silicon-containing gas examples include silane gas (SiH 4 gas), disilane gas (Si 2 H 6 gas), and the like, and a combination thereof may be used.
  • the processing conditions when processing the wafer 200 in the processing chamber 201 of the present embodiment are as follows: Processing temperature: 300 ° C. or more and 500 ° C. or less, Processing pressure: 10 Pa or more and 1330 Pa or less, Silane gas supply flow rate: 10 sccm or more and 5000 sccm or less, The silicon nuclei formed on the wafer 200 grow by maintaining each processing condition constant at a certain value within each range, and a silicon film is formed.
  • silicon nuclei uniformly formed on the wafer 200 can be efficiently grown, and a silicon film can be formed.
  • At least one of the following effects can be obtained.
  • a silicon film can be formed by efficiently growing silicon nuclei. it can.
  • consumption of the source gas can be suppressed.
  • the present invention can be applied not only to batch type apparatuses but also to single wafer type apparatuses.

Abstract

La présente invention concerne un procédé de fabrication d'un dispositif à semi-conducteurs comprenant une étape de formation des noyaux destinée à former les noyaux sur un substrat et une étape d'interruption de la croissance des noyaux destinée à interrompre la croissance des noyaux. L'étape de formation des noyaux et l'étape d'interruption de la croissance des noyaux sont définies comme un cycle. Un film est formé en répétant une pluralité de cycles. La durée de l'étape d'interruption de la croissance des noyaux est inférieure ou égale à celle de l'étape de formation des noyaux. En variante, l'étape de formation des noyaux est répétée après une pluralité de cycles.
PCT/JP2011/069319 2010-09-01 2011-08-26 Procédé de fabrication d'un dispositif à semi-conducteurs et dispositif de traitement de substrat WO2012029661A1 (fr)

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Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013524516A (ja) * 2010-03-31 2013-06-17 東京エレクトロン株式会社 シリコン及びシリコン含有膜の原子層堆積
JP2014067796A (ja) * 2012-09-25 2014-04-17 Hitachi Kokusai Electric Inc 半導体装置の製造方法及び基板処理装置
JP2016001760A (ja) * 2015-09-24 2016-01-07 株式会社日立国際電気 半導体装置の製造方法、基板処理方法、基板処理装置およびガス供給系
JP2016105457A (ja) * 2014-11-19 2016-06-09 株式会社日立国際電気 三次元フラッシュメモリ、ダイナミックランダムアクセスメモリ、半導体装置、半導体装置の製造方法、基板処理装置、ガス供給システムおよびプログラム
JP2016122699A (ja) * 2014-12-24 2016-07-07 東京エレクトロン株式会社 シリコン膜の成膜方法および成膜装置
US9540728B2 (en) 2014-11-19 2017-01-10 Hitachi Kokusai Electric Inc. Substrate processing apparatus, apparatus for manufacturing semiconductor device, and gas supply system
JP2017135344A (ja) * 2016-01-29 2017-08-03 株式会社日立国際電気 半導体装置の製造方法、基板処理装置、ガス供給システムおよびプログラム
JP2017162974A (ja) * 2016-03-09 2017-09-14 株式会社日立国際電気 半導体装置の製造方法、基板処理装置、ガス供給系およびプログラム
JP2017188598A (ja) * 2016-04-07 2017-10-12 株式会社日立国際電気 半導体装置の製造方法、基板処理装置、およびプログラム
US10134584B2 (en) 2015-12-25 2018-11-20 Hitachi Kokusai Electric Inc. Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium
US10199219B2 (en) 2016-06-15 2019-02-05 Hitachi Kokusai Electric, Inc. Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium
KR20190080788A (ko) 2017-12-28 2019-07-08 가부시키가이샤 코쿠사이 엘렉트릭 반도체 장치의 제조 방법, 기판 처리 장치 및 프로그램
KR20200030451A (ko) 2018-09-12 2020-03-20 가부시키가이샤 코쿠사이 엘렉트릭 반도체 장치의 제조 방법, 기판 처리 장치 및 프로그램
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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180102161A1 (en) * 2016-10-07 2018-04-12 Kilopass Technology, Inc. Vertical Thyristor Memory Array and Memory Array Tile Therefor
US10861727B2 (en) 2018-03-13 2020-12-08 Samsung Electronics Co., Ltd. Segmented vertical wafer boat
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05267166A (ja) * 1992-03-04 1993-10-15 Nec Corp シリコンエピタキシャル膜の選択成長方法及び成長装置
JP2005183514A (ja) * 2003-12-17 2005-07-07 Hitachi Kokusai Electric Inc 半導体装置の製造方法
WO2007013464A1 (fr) * 2005-07-29 2007-02-01 Hitachi Kokusai Electric Inc. Procédé de fabrication d’un dispositif semi-conducteur

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2889810B2 (ja) 1994-03-14 1999-05-10 三菱マテリアル株式会社 ポリシリコン膜の研磨方法およびポリシリコン膜用研磨剤
KR100373853B1 (ko) * 2000-08-11 2003-02-26 삼성전자주식회사 반도체소자의 선택적 에피택시얼 성장 방법
JP3952735B2 (ja) * 2001-10-25 2007-08-01 ソニー株式会社 半導体装置の製造方法
US7560352B2 (en) * 2004-12-01 2009-07-14 Applied Materials, Inc. Selective deposition
US7438760B2 (en) * 2005-02-04 2008-10-21 Asm America, Inc. Methods of making substitutionally carbon-doped crystalline Si-containing materials by chemical vapor deposition
JP2007329200A (ja) * 2006-06-06 2007-12-20 Toshiba Corp 半導体装置の製造方法
JP2008177419A (ja) * 2007-01-19 2008-07-31 Nissin Electric Co Ltd シリコン薄膜形成方法
US8012885B2 (en) * 2007-04-02 2011-09-06 Hitachi Kokusai Electric Inc. Manufacturing method of semiconductor device
KR101028416B1 (ko) * 2007-08-20 2011-04-13 재단법인서울대학교산학협력재단 박막 제조 방법 및 박막 제조 장치
JP5436101B2 (ja) * 2008-09-05 2014-03-05 株式会社半導体エネルギー研究所 半導体装置の作製方法
KR20110021654A (ko) * 2009-08-25 2011-03-04 가부시키가이샤 한도오따이 에네루기 켄큐쇼 미결정 반도체막의 제조방법, 및 반도체장치의 제조방법
JP5514162B2 (ja) * 2011-07-22 2014-06-04 東京エレクトロン株式会社 アモルファスシリコン膜の成膜方法および成膜装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05267166A (ja) * 1992-03-04 1993-10-15 Nec Corp シリコンエピタキシャル膜の選択成長方法及び成長装置
JP2005183514A (ja) * 2003-12-17 2005-07-07 Hitachi Kokusai Electric Inc 半導体装置の製造方法
WO2007013464A1 (fr) * 2005-07-29 2007-02-01 Hitachi Kokusai Electric Inc. Procédé de fabrication d’un dispositif semi-conducteur

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JP2014067796A (ja) * 2012-09-25 2014-04-17 Hitachi Kokusai Electric Inc 半導体装置の製造方法及び基板処理装置
US9941119B2 (en) 2014-11-19 2018-04-10 Hitachi Kokusai Electric Inc. Method of forming silicon layer in manufacturing semiconductor device and recording medium
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US9691609B2 (en) 2014-11-19 2017-06-27 Hitachi Kokusai Electric Inc. Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium
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US10134584B2 (en) 2015-12-25 2018-11-20 Hitachi Kokusai Electric Inc. Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium
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