WO2012029450A1 - シリコンエッチング液及びそれを用いたトランジスタの製造方法 - Google Patents
シリコンエッチング液及びそれを用いたトランジスタの製造方法 Download PDFInfo
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- WO2012029450A1 WO2012029450A1 PCT/JP2011/066997 JP2011066997W WO2012029450A1 WO 2012029450 A1 WO2012029450 A1 WO 2012029450A1 JP 2011066997 W JP2011066997 W JP 2011066997W WO 2012029450 A1 WO2012029450 A1 WO 2012029450A1
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- Prior art keywords
- silicon
- etching
- dummy gate
- transistor
- dielectric material
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
Definitions
- the present invention relates to a method for manufacturing a transistor, characterized in that a structure having a dummy gate stacked body in which at least a high dielectric material film and a dummy gate made of silicon are stacked is used, and the dummy gate is replaced with an aluminum metal gate.
- the present invention relates to an etching solution that is used for etching a dummy gate made of silicon and selectively etches the dummy gate made of silicon, and a transistor manufacturing method using the same.
- semiconductors have improved performance, cost, and power consumption by so-called miniaturization that reduces the gate length and gate thickness of transistors.
- the gate thickness becomes too thin in the conventional gate insulating film using silicon oxide, the leakage current due to the tunnel current increases, and the power consumption increases.
- devices that use semiconductor elements have been increasingly carried around, such as mobile phones, notebook computers, and portable music players. In this case, since electric power is often supplied from a rechargeable battery, low power consumption is required for the semiconductor element aiming at long-term use.
- FIG. 1 is a schematic cross-sectional view of a part of a transistor before removing polycrystalline silicon in a semiconductor element using a high dielectric material.
- this polycrystalline silicon is etched, aluminum, an interlayer insulating film, a sidewall, and a high dielectric material film are present around the polycrystalline silicon, and these should not be etched. Therefore, a technique for etching polycrystalline silicon without etching aluminum, interlayer insulating films, sidewalls, and high dielectric materials is required.
- Dry etching is known as a method for etching polycrystalline silicon (Patent Document 1).
- a protective film such as a photoresist
- Providing the protective film complicates the manufacturing process and may lead to a decrease in yield and an increase in manufacturing cost.
- the ashing treatment performed to remove the photoresist damages the aluminum and the interlayer insulating film, so there is a concern that the performance of the transistor may be deteriorated.
- overetching is performed in which etching is performed for a time longer than the etching processing time calculated from the etching amount per unit time of silicon (hereinafter referred to as an etch rate).
- an etch rate the etching processing time calculated from the etching amount per unit time of silicon
- Non-patent Document 2 Various alkaline cleaning liquids are known as cleaning liquids for etching silicon by a wet etching method (Non-patent Document 2). However, these cleaning solutions etch not only polycrystalline silicon but also aluminum (see Comparative Example 1).
- Patent Document 2 As a technique for etching silicon without etching aluminum, an anisotropic silicon etchant in which silicon is dissolved in tetramethylammonium hydroxide has been proposed (Patent Document 2).
- Patent Document 2 an anisotropic silicon etchant in which silicon is dissolved in tetramethylammonium hydroxide has been proposed.
- Patent Document 2 Since this technology is premised on the use at high temperature, in recent years, when using a single wafer cleaning device for cleaning silicon wafers one by one, which is usually used in semiconductor manufacturing, to suppress particles in wet etching , Can not provide stable etching ability.
- the etching rate of silicon is too small, and therefore cannot be used for silicon etching in a transistor forming process including a high dielectric material and a metal gate.
- Patent Document 3 As an etchant composition capable of selectively anisotropically etching only silicon without etching aluminum or an aluminum alloy, an alkaline etchant composition in which a reducing compound and an anticorrosive agent are added to an alkaline aqueous solution has been proposed.
- Patent Document 3 This technique cannot be used for silicon etching in a transistor formation process including a high dielectric material and a metal gate because the etch rate of aluminum is too large (see Comparative Example 3).
- Patent Document 4 An aqueous solution containing quaternary ammonium hydroxide, sugar or sugar alcohol has been proposed as a technique for suppressing etching of aluminum and removing chlorine (Patent Document 4).
- Patent Document 4 prevents aluminum from the viewpoint of removing chlorine, and does not mention the etching ability of silicon of the alkaline stripping solution. That is, Patent Document 4 is a technical idea different from the present invention that aims to etch silicon without etching an aluminum film. Furthermore, since the etch rate of silicon in an aqueous solution disclosed in Patent Document 4 is too small, it cannot be used for silicon etching in a transistor formation process including a high dielectric material and a metal gate, which is an object of the present invention (Comparative Example 4). See).
- Patent Document 5 proposes an alkaline stripping solution that prevents the etching of aluminum from the viewpoint of not hindering the ability to weaken the adhesive strength of the adhesive film, and does not mention the etching ability of silicon of the alkaline stripping solution. Therefore, Patent Document 5 is a technique different from the present invention aimed at etching silicon without etching an aluminum film. Furthermore, the stripping solution that can be used in Patent Document 5 is not particularly limited as long as it is an alkaline solution. However, the alkaline compounds that can be used for etching silicon are limited. That is, it is not easy to analogize a compound suitable for the present invention based on Patent Document 5 (see Comparative Example 5).
- An aqueous solution containing a quaternary ammonium hydroxide, trialkylamine, alcohol or alkyl ether has been proposed as a technique for suppressing etching of aluminum and removing the polyimide alignment film (Patent Document 6).
- this cleaning solution has a small silicon etching capability and cannot be used for this purpose (see Comparative Example 6).
- the dummy gate made of silicon and replacing it with an aluminum metal gate, the dummy gate is selectively removed in a method of manufacturing a transistor having a laminate composed of at least a high dielectric material film and an aluminum metal gate. There is a strong demand for an etching solution.
- the present invention relates to a dummy gate made of silicon in a method of manufacturing a transistor having a laminate composed of at least a high dielectric material film and an aluminum metal gate by removing the dummy gate made of silicon and replacing it with an aluminum metal gate. It is an object of the present invention to provide an etching solution for selectively etching a dummy gate made of silicon and a method for manufacturing a transistor using the same.
- the present inventors have found that the object can be achieved by using a specific silicon etchant for etching a dummy gate made of silicon. .
- the present invention has been completed based on such findings. That is, the gist of the present invention is as follows.
- a dummy gate laminated body formed by laminating at least a high dielectric material film and a silicon dummy gate on a substrate, a sidewall provided to cover the side surface of the laminated body, and a sidewall provided to cover the sidewall
- the dummy gate made of silicon is used for etching, ammonia, diamine, and a general formula ( 0.1 to 40% by weight of at least one alkali compound selected from the polyamines represented by 1) and 5 to 50% by weight of at least one selected from polyhydric alcohols represented by the general formula (2)
- a silicon etching solution containing 40 to 94.9% by weight of water.
- a dummy gate laminated body formed by laminating at least a high dielectric material film and a silicon dummy gate on a substrate, a sidewall provided to cover the side surface of the laminated body, and a sidewall provided to cover the sidewall A method for manufacturing a transistor, comprising: using a structure having an interlayer insulating film; having the following step (I); and replacing the dummy gate with an aluminum metal gate.
- Step (I) The silicon is represented by 0.1 to 40% by weight of an alkali compound that is at least one selected from ammonia, diamine, and polyamine represented by the general formula (1), represented by the general formula (2) Etching with an etching solution containing 5 to 50% by weight of at least one selected from polyhydric alcohols and 40 to 94.9% by weight of water H 2 N— (CH 2 CH 2 NH) m —H ... (1) (M is an integer of 2 to 5.) H— (CH (OH)) n —H (2) (N is an integer of 3 to 6.) 6). 6.
- the diamine and the polyamine represented by the general formula (1) are at least one selected from ethylenediamine, 1,2-propanediamine, 1,3-propanediamine, diethylenetriamine, and triethylenetetramine. Manufacturing method. 8).
- the polyhydric alcohol represented by the general formula (2) is at least one selected from glycerin, meso-erythritol, xylitol, and sorbitol.
- silicon is selectively used in a method of manufacturing a transistor having a laminate composed of at least a high dielectric material film and an aluminum metal gate by removing a dummy gate made of silicon and replacing it with an aluminum metal gate.
- a high-precision and high-quality transistor can be manufactured with high yield.
- the silicon etchant of the present invention comprises a dummy gate laminate in which at least a high dielectric material film and a dummy gate made of silicon are laminated on a substrate, a sidewall provided so as to cover a side surface of the laminate, and the What is used for etching a dummy gate made of silicon in a method of manufacturing a transistor using a structure having an interlayer insulating film provided so as to cover a sidewall and replacing the dummy gate with an aluminum metal gate 0.1 to 40% by weight of at least one alkali compound selected from ammonia, diamine, and polyamine represented by the general formula (1), from a polyhydric alcohol represented by the general formula (2) Contains 5 to 50% by weight of at least one selected, and 40 to 94.9% by weight of water It is.
- M is an integer of 2 to 5.
- N is an integer of
- the alkali compound used in the present invention is for etching silicon, and is at least one compound selected from ammonia, diamine, and polyamine represented by the general formula (1).
- Preferred examples of the diamine contained in the silicon etching solution of the present invention include ethylenediamine, 1,2-propanediamine, 1,3-propanediamine, and the like, and examples of the polyamine represented by the general formula (1) include diethylenetriamine and triethylene. Preferred examples include ethylene tetramine.
- the concentration of the alkali compound in the etching solution is usually 0.1 to 40% by weight, preferably 0.2 to 40% by weight, more preferably 0.3 to 30% by weight.
- the polyhydric alcohol in the silicon etching solution of the present invention is one or more selected from compounds represented by the general formula (2).
- Preferable specific examples of the polyhydric alcohol represented by the general formula (2) are glycerin, meso-erythritol, xylitol, and sorbitol.
- the concentration of the polyhydric alcohol in the etching solution is usually 5 to 50% by weight, preferably 6 to 40% by weight, and more preferably 7 to 30% by weight. If the concentration of the polyhydric alcohol is 5% by weight or more, a sufficient aluminum corrosion prevention effect can be obtained. On the other hand, if the concentration of the polyhydric alcohol is 50% by weight or less, the silicon etching ability is sufficient.
- the silicon etching solution of the present invention may be blended with additives such as surfactants and anticorrosive agents conventionally used in etching solutions as long as they do not impair the purpose of the present invention.
- the silicon etching solution of the present invention covers a dummy gate stack including a high dielectric material film and a dummy gate made of silicon, a sidewall provided to cover a side surface of the stack, and the sidewall on the substrate.
- the structure having the interlayer insulating film thus provided is used for etching a dummy gate made of silicon.
- FIG. 1 shows a cross-sectional view of a structure having a dummy gate etched with the etching solution of the present invention. The structure shown in FIG.
- a dummy gate laminated body in which a high dielectric material film 2 and a dummy gate 1 made of silicon are laminated on a substrate 7, and a sidewall provided so as to cover the side surface of the laminated body. 3 and an interlayer insulating film 4 provided so as to cover the sidewall 3.
- the structure may already have a place where the dummy gate 1 is replaced with an aluminum metal gate.
- the aluminum metal gate is a metal gate containing aluminum metal, and the metal gate may not be formed of 100% aluminum. From the viewpoint of effectively obtaining the effects of the present invention, aluminum metal gate is used. The content of is preferably 50% or more. Further, all the dummy gates may be replaced with aluminum metal gates, or a part thereof may be replaced. In the present invention, if aluminum is used in a part of the transistor, the effect of the present invention can be obtained by selectively etching the silicon forming the dummy gate without etching the part. is there.
- FIG. 1 shows the source / drain 6 and the isolation 5 that can be formed by a method such as ion implantation.
- the high dielectric material film 2 is a substrate so as to cover the space between the source / drain 6. 7 on the surface.
- the substrate material used for the substrate 7 preferably includes silicon, amorphous silicon, polysilicon, glass, and the like, and the wiring material used for the metal gate and the like is as follows. At least aluminum is used, and materials other than aluminum, for example, wiring materials such as copper, tungsten, titanium-tungsten, aluminum, aluminum alloy, chromium, and chromium alloy may be used.
- a silicon oxide film (HDP), tetraethoxysilane (TEOS), Boron Phosphorate Silicate Glass (BPSG) or the like by a high density plasma chemical vapor deposition method is preferably used.
- high dielectric materials include HfO 2 , Al 2 O 3 , or silicon atoms and / or nitrogen atoms and / or La, Ti, A material containing a metal such as Zr is preferably used.
- the materials used for the interlayer insulating film 4, the sidewall 3, and the high dielectric material film 2 are not limited to these.
- the silicon etchant of the present invention first comprises an aluminum metal gate (not shown), an interlayer insulating film 4 and sidewalls of the structure. 3 will be touched. Further, when the dummy gate 1 is etched, the high dielectric material film 2 is exposed from the bottom of the dummy gate 1, so that the high dielectric material film 2 is touched. Under such circumstances, the silicon etching solution of the present invention does not etch the aluminum metal gate (not shown), the interlayer insulating film 4, the sidewalls 3 and the high dielectric material film 2, and the dummy gate 1 made of silicon. Since it has a characteristic of selectively etching, damage to each part of the transistor can be prevented, and a high-precision and high-quality transistor can be manufactured with high yield.
- the use temperature of the silicon etching solution of the present invention that is, the temperature at the time of etching the dummy gate is usually in the range of about 20 to 80 ° C., preferably 20 to 70 ° C., more preferably 20 to 60 ° C. What is necessary is just to select suitably by these conditions and the board
- the processing time with the silicon etching solution of the present invention is usually in the range of about 0.1 to 10 minutes, preferably 0.2 to 8 minutes, more preferably 0.3 to 5 minutes. Therefore, it may be selected as appropriate depending on the etching conditions and the substrate material used.
- the method of manufacturing a transistor of the present invention includes a dummy gate stacked body in which at least a high dielectric material film and a dummy gate made of silicon are stacked on a substrate, a sidewall provided so as to cover a side surface of the stacked body, and A structure having an interlayer insulating film provided so as to cover the sidewall is used, and an alkali compound that is at least one selected from ammonia, diamine, and polyamine represented by the general formula (1) is used in an amount of 0.0.
- the structure and the etching solution are as described above.
- the use temperature and processing time when using the etching solution of the present invention are also as described above.
- ultrasonic waves can be used together as necessary.
- an organic solvent such as alcohol as the rinsing liquid after removing the etching residue on the substrate by the production method of the present invention, and it is sufficient to rinse with water.
- the method for producing a transistor of the present invention is not particularly limited as long as it has an etching process using the above-described etching solution of the present invention, and one embodiment of a preferred method for producing a transistor of the present invention is the step (A).
- a step of forming a high dielectric material film on the substrate, step (B), a step of forming a dummy gate made of silicon on the high dielectric material film, and forming a laminate including the high dielectric material film and the dummy gate C) a step of forming a sidewall so as to cover the side surface of the laminate, a step (D) a step of forming an interlayer insulating film so as to cover the sidewall, a step (E) a step of etching a silicon natural oxide film, a step (1) Etching step of dummy gate using the above-described etching solution of the present invention, and step (F): forming an aluminum metal gate on the high dielectric material film, and forming the high dielectric material film Manufacturing method having a step of laminating body comprises fine aluminum metal gate in order and the like.
- the steps (A) to (F) are not particularly limited, and may be in accordance with a method generally employed in each step in the transistor manufacturing method.
- the dummy gate 1 is made of a silicon material such as polycrystalline silicon. Since the silicon material comes into contact with air in the process of manufacturing a transistor, the surface of the dummy gate 1 is naturally oxidized, and the silicon natural oxide film is formed. May form. Therefore, in the manufacturing method of the present invention, it is preferable that the silicon natural oxide film 6 be etched in advance before the dummy gate 1 using the etching solution of the present invention is etched (step (1)). By having such a process, the etching process of the dummy gate using the etching solution of the present invention can be efficiently performed, so that a high-precision and high-quality transistor can be manufactured with a high yield. Become.
- etching solution for etching the silicon natural oxide film, a conventionally used etching solution containing a fluorine compound such as hydrofluoric acid can be used. Further, in this step (E), the aluminum metal gate (not shown), the interlayer insulating film 4 and the sidewall 3 of the structure are touched so that these portions are not damaged, that is, a silicon natural oxide film is selected. It is preferable to use an etching solution having a performance of etching. As such an etching solution, it is preferable to use an etching solution containing 0.01 to 8% by weight of a fluorine compound, 20 to 90% by weight of a water-soluble organic solvent, and water.
- fluorine compound Preferable specific examples of the fluorine compound are hydrofluoric acid, ammonium fluoride, and acidic ammonium fluoride. More preferred are ammonium fluoride and acidic ammonium fluoride. In this invention, these fluorine compounds can be mix
- the water-soluble organic solvent is preferably an alcohol such as ethanol, 2-propanol, ethylene glycol or diethylene glycol; a glycol ether such as diethylene glycol monomethyl ether, diethylene glycol monobutyl ether, dipropylene glycol monomethyl ether or dipropylene glycol monopropyl ether; Preferred examples include amides such as N, N-dimethylformamide, N, N-dimethylacetamide and N-methyl-2-pyrrolidone; dimethyl sulfoxide and the like. These water-soluble organic solvents may be used alone or in combination of two or more.
- the etching solution used in this step (E) includes inorganic acids such as hydrochloric acid, nitric acid, sulfuric acid, and phosphoric acid; organic acids such as acetic acid, propionic acid, oxalic acid, and methanesulfonic acid. You may add in the range. These acids may be used alone or in combination of two or more.
- the transistor obtained by the manufacturing method of the present invention is provided on a substrate 7 so as to cover at least a high dielectric material film 2 and an aluminum metal gate (not shown), and a side surface of the laminated body.
- the dummy gate 1 Is replaced with an aluminum metal gate.
- the transistor obtained by the manufacturing method of the present invention has a source / drain 6 and an isolation 5, and the high dielectric material film 2 is interposed between the source / drain 6. Is provided on the surface of the substrate 7.
- the substrate material used for the substrate 7, the material used for the interlayer insulating film 4, and the material used for the sidewall 3 are the substrates used for the substrate 7 in the above structure. It is the same as the material, the material used for the interlayer insulating film 4, and the material used for the sidewall 3.
- the transistor obtained by the manufacturing method of the present invention may have a portion that the transistor normally has, for example, a barrier layer or an insulating film.
- the barrier material for forming the barrier layer preferable examples of the barrier material include titanium, titanium nitride, tantalum, and tantalum nitride.
- the insulating material for forming the insulating film silicon oxide, silicon nitride, silicon carbide, and the like. Preferred are the derivatives of In a laminate formed by laminating a high dielectric material film 2 and an aluminum metal gate (not shown), a metal gate made of a metal material other than the metal forming the aluminum metal gate is further laminated, for example, a characteristic control film Layers having such functions may be laminated.
- the semiconductor material a compound semiconductor such as gallium-arsenic, gallium-phosphorus, indium-phosphorus, or an oxide semiconductor such as chromium oxide is preferable.
- the transistor obtained by the manufacturing method of the present invention is a high-precision and high-quality transistor.
- Examples 1-48 In order to investigate the anticorrosion ability of the etching solution against aluminum, the following method was used. An aluminum film 1000 ⁇ was deposited by PVD on a silicon wafer serving as a substrate. This aluminum film was immersed in the etching solution shown in Table 2 at 25 ° C. for 30 minutes, the film thickness before and after the immersion was measured with a fluorescent X-ray analyzer, and the etching amount of the aluminum film by the etching solution was calculated. The etch rate was calculated from the calculated etching amount and immersion time, and when the etch rate of aluminum was less than 1 nm / min, it was determined that the corrosion resistance of the etching solution to aluminum was obtained.
- a silicon wafer was employed as the substrate, and a structure having a cross-sectional view as shown in FIG. 1 having a transistor structure on the silicon wafer and having the transistor structure of 1A to 1I shown in Table 1 was prepared.
- 0.05 wt% hydrofluoric acid etching solution was used.
- the high dielectric material film 2 is covered with a dummy gate 1 made of silicon. Therefore, when the dummy gate 1 made of silicon is removed by the etching solution, the etching solution comes into contact with the high dielectric material film 2, and the state of the high dielectric material film 2 is observed, whereby the high dielectric material by the etching solution is used. Damage to the material film can be determined. Therefore, only when the dummy gate 1 made of silicon is etched, the high-dielectric material film 2 is obtained by thinning the transistor after etching to a thickness of 200 nm or less using an FIB and observing with a STEM. Judged the state of.
- Tables 3 and 5 show the evaluation results of the state of the dummy gate 1 made of silicon and the etch rate of aluminum.
- Comparative Example 2 After the hydrofluoric acid treatment shown in Example 1 was performed using the structure having the transistor structure 1B, 0.5% by weight of tetramethylammonium hydroxide described in Patent Document 2 was used instead of the etching solution 2G. As a result of etching using an aqueous solution containing 0.1% by weight of silicon (Table 4, etching solution 4B), the etch rate of aluminum was less than 1 nm / min as shown in Table 5. The etching capability of the dummy gate 1 made of silicon was insufficient. From this, it can be seen that the etching solution described in Patent Document 2 cannot be used for silicon etching in a transistor forming process including a high dielectric material and a metal gate, which is the subject of the present invention.
- Comparative Example 3 After the hydrofluoric acid treatment shown in Example 1 was performed using the structure having the transistor structure 1C, 10% by weight of tetramethylammonium hydroxide described in Patent Document 3 and hydroxylamine instead of the etching solution 2G As a result of etching using an aqueous solution of 10% by weight and 5% by weight of sorbitol (Table 4, etching solution 4C), the dummy gate 1 made of silicon was etched as shown in Table 5. The etch rate of aluminum was 1 nm / min or more. From this, it can be seen that the aqueous solution described in Patent Document 3 cannot be used for silicon etching in a transistor forming process including a high dielectric material and a metal gate, which is an object of the present invention.
- Comparative Example 4 After the hydrofluoric acid treatment shown in Example 1 was performed using the structure having the transistor structure 1G, 2.4% by weight of tetramethylammonium hydroxide described in Patent Document 4 was used instead of the etching solution 2G. As a result of etching using an aqueous solution of sorbitol 5% by weight (Table 4, etching solution 4D), as shown in Table 5, the etching capability of the dummy gate 1 made of silicon is insufficient. The etch rate was 1 nm / min or more. From this, it can be seen that the aqueous solution described in Patent Document 4 cannot be used for silicon etching in a transistor forming process including a high dielectric material and a metal gate, which is the subject of the present invention.
- Comparative Example 7 After the hydrofluoric acid treatment described in Example 1 was performed using the structure having the transistor structure 1F, an aqueous solution of 0.5% by weight of 1,3-propanediamine (Table 4, As a result of etching using the etching solution 4G), as shown in Table 5, the etching capability of the dummy gate 1 made of silicon was insufficient, and the etching rate of aluminum was 1 nm / min or more. . From this, it can be seen that the aqueous alkali compound solution cannot be used for silicon etching in a transistor forming process including a high dielectric material and a metal gate, which is the subject of the present invention.
- Comparative Example 8 After the hydrofluoric acid treatment shown in Example 1 was performed using the structure having the transistor structure 1H, an aqueous solution of sorbitol 10% by weight (Table 4, etching solution 4H) was used instead of the etching solution 2G. As a result of performing the etching process, as shown in Table 5, the etching rate of aluminum was less than 1 nm / min, but the etching capability of the dummy gate 1 made of silicon was insufficient. This shows that the polyhydric alcohol aqueous solution cannot be used for silicon etching in a transistor forming process including a high dielectric material and a metal gate, which is the subject of the present invention.
- Comparative Example 9 After the hydrofluoric acid treatment shown in Example 1 was performed using the structure having the transistor structure 1A, an aqueous solution (first solution of 5% by weight of 1,3-propanediamine and 10% by weight of inositol was used instead of the etching solution 2G. As shown in Table 5, the dummy gate 1 made of silicon was etched but the aluminum etch rate was 1 nm / min or more as a result of etching using Table 4 and Etching Solution 4I). It was.
- Comparative Example 10 After the hydrofluoric acid treatment shown in Example 1 was performed using the structure having the transistor structure 1A, an aqueous solution (first solution of 5% by weight of 1,3-propanediamine and 10% by weight of sucrose was used instead of the etching solution 2G. As shown in Table 5, the dummy gate 1 made of silicon was etched but the aluminum etch rate was 1 nm / min or more as a result of etching using Table 4, Etching Solution 4J). It was. From this, it can be seen that an aqueous solution of an alkali compound and a non-reducing sugar cannot be used for silicon etching in a transistor formation process including a high dielectric material and a metal gate, which is the subject of the present invention.
- a high-dielectric material film and aluminum can be selectively etched by etching a dummy gate made of silicon without etching an aluminum metal gate, an interlayer insulating film, a sidewall, and a high-dielectric material film. It can be used in a transistor forming process including a metal gate contained therein, and is industrially useful.
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Abstract
Description
2:高誘電材料膜
3:サイドウォール
4:層間絶縁膜
5:アイソレーション
6:ソース/ドレイン
7:基板
H2N-(CH2CH2NH)m-H ・・・(1)
(mは2~5の整数である。)
H-(CH(OH))n-H ・・・(2)
(nは3~6の整数である。)
2.ジアミン及び一般式(1)で表されるポリアミンが、エチレンジアミン、1,2-プロパンジアミン、1,3-プロパンジアミン、ジエチレントリアミン、及びトリエチレンテトラミンから選ばれる少なくとも1種である上記1に記載のシリコンエッチング液。
3.一般式(2)で表される多価アルコールが、グリセリン、meso-エリトリトール、キシリトール、及びソルビトールから選ばれる少なくとも1種である上記1に記載のシリコンエッチング液。
4.高誘電材料膜を形成する高誘電材料が、HfO2、HfSiO、HfSiON、HfLaO、HfLaON、HfTiSiON、HfAlSiON、HfZrO、又はAl2O3である上記1に記載のシリコンエッチング液。
5.基板上に、少なくとも高誘電材料膜とシリコンからなるダミーゲートとが積層してなるダミーゲート積層体、該積層体の側面を覆うように設けられるサイドウォール、及び該サイドウォールを覆うように設けられる層間絶縁膜を有する構造体を用い、以下の工程(I)を有し、かつ該ダミーゲートをアルミニウム金属ゲートに入れ替えることを特徴とするトランジスタの製造方法。
工程(I)シリコンを、アンモニア、ジアミン、及び一般式(1)で表されるポリアミンから選ばれる少なくとも1種であるアルカリ化合物を0.1~40重量%、一般式(2)で表される多価アルコールから選ばれる少なくとも1種を5~50重量%、ならびに水40~94.9重量%を含有するエッチング液を用いてエッチングする工程
H2N-(CH2CH2NH)m-H ・・・(1)
(mは2~5の整数である。)
H-(CH(OH))n-H ・・・(2)
(nは3~6の整数である。)
6.高誘電材料膜を形成する高誘電材料が、HfO2、HfSiO、HfSiON、HfLaO、HfLaON、HfTiSiON、HfAlSiON、HfZrO、又はAl2O3である上記5に記載のトランジスタの製造方法。
7.ジアミン及び一般式(1)で表されるポリアミンが、エチレンジアミン、1,2-プロパンジアミン、1,3-プロパンジアミン、ジエチレントリアミン、及びトリエチレンテトラミンから選ばれる少なくとも1種である上記5に記載のトランジスタの製造方法。
8.一般式(2)で表される多価アルコールが、グリセリン、meso-エリトリトール、キシリトール、及びソルビトールから選ばれる少なくとも1種である上記5に記載のトランジスタの製造方法。
本発明のシリコンエッチング液は、基板上に、少なくとも高誘電材料膜とシリコンからなるダミーゲートとが積層してなるダミーゲート積層体、該積層体の側面を覆うように設けられるサイドウォール、及び該サイドウォールを覆うように設けられる層間絶縁膜を有する構造体を用い、該ダミーゲートをアルミニウム金属ゲートに入れ替えることを特徴とするトランジスタの製造方法における、該シリコンからなるダミーゲートのエッチングに用いられるものであり、アンモニア、ジアミン、及び一般式(1)で表されるポリアミンから選ばれる少なくとも1種であるアルカリ化合物を0.1~40重量%、一般式(2)で表される多価アルコールから選ばれる少なくとも1種を5~50重量%、ならびに水40~94.9重量%を含有する液である。
H2N-(CH2CH2NH)m-H ・・・(1)
(mは2~5の整数である。)
H-(CH(OH))n-H ・・・(2)
(nは3~6の整数である。)
エッチング液中のアルカリ化合物の濃度は、通常0.1~40重量%であり、好ましくは0.2~40重量%で、より好ましくは0.3~30重量%である。
エッチング液中の多価アルコールの濃度は、通常5~50重量%であり、好ましくは6~40重量%であり、より好ましくは7~30重量%である。多価アルコールの濃度が5重量%以上であれば、十分なアルミニウムの腐食防止効果が得られる。一方、多価アルコールの濃度が50重量%以下であれば、シリコンエッチング能力は十分なものとなる。
本発明のシリコンエッチング液は、基板上に、高誘電材料膜、及びシリコンからなるダミーゲートを含むダミーゲート積層体、該積層体の側面を覆うように設けられるサイドウォール、及び該サイドウォールを覆うように設けられる層間絶縁膜を有する構造体の、シリコンからなるダミーゲートのエッチングに用いられる。ここで、図1に、本発明のエッチング液によりエッチングするダミーゲートを有する構造体の断面図を示す。図1に示される構造体は、基板7上に、高誘電材料膜2とシリコンからなるダミーゲート1とが積層してなるダミーゲート積層体、該積層体の側面を覆うように設けられるサイドウォール3、及び該サイドウォール3を覆うように設けられる層間絶縁膜4を有する構造体である。
また、図1にはイオン注入などの方法により形成しうるソース/ドレイン6、アイソレーション5が示されているが、通常高誘電材料膜2は、ソース/ドレイン6の間を覆うように、基板7の表面上に設けられる。
また、層間絶縁膜4に用いられる材料としては、高密度プラズマ化学気相法による酸化シリコン膜(HDP)、テトラエトキシシラン(TEOS)、Boron Phosphor Silicate Glass(BPSG)などが好ましく使用され、サイドウォール3に用いられる材料としては、窒化シリコン(SiN)などが好ましく使用され、高誘電材料としては、HfO2、Al2O3、あるいはこれらにケイ素原子及び/又は窒素原子及び/又はLa、Ti、Zrなどの金属を含む材料が好ましく使用される。層間絶縁膜4、サイドウォール3、高誘電材料膜2に使用される材料は、これらに限定されるものではない。
本発明のシリコンエッチング液の使用温度、すなわちダミーゲートのエッチングの際の温度は、通常20~80℃程度の範囲であり、好ましくは20~70℃で、より好ましくは20~60℃で、エッチングの条件や使用される基板材料により適宜選択すればよい。
本発明のトランジスタの製造方法は、基板上に、少なくとも高誘電材料膜とシリコンからなるダミーゲートとが積層してなるダミーゲート積層体、該積層体の側面を覆うように設けられるサイドウォール、及び該サイドウォールを覆うように設けられる層間絶縁膜を有する構造体を用い、シリコンを、アンモニア、ジアミン、及び一般式(1)で表されるポリアミンから選ばれる少なくとも1種であるアルカリ化合物を0.1~40重量%、一般式(2)で表される多価アルコールから選ばれる少なくとも1種を5~50重量%、ならびに水40~94.9重量%を含有するエッチング液、すなわち本発明のエッチング液を用いてエッチングする工程を有し、かつ該ダミーゲートをアルミニウム金属ゲートに入れ替えることを特徴とするものである。
H2N-(CH2CH2NH)m-H ・・・(1)
(mは2~5の整数である。)
H-(CH(OH))n-H ・・・(2)
(nは3~6の整数である。)
本発明のエッチング液を用いたエッチング工程においては、必要に応じて超音波を併用することができる。また、本発明の製造方法により、基板上のエッチング残渣を除去した後のリンス液としては、アルコールのような有機溶剤を使用する必要はなく、水でリンスするだけで十分である。
本発明のトランジスタの製造方法は、上記した本発明のエッチング液を用いたエッチング工程を有していれば特に制限はなく、本発明の好ましいトランジスタの製造方法の一態様としては、工程(A)基板上に高誘電材料膜を形成する工程、工程(B)該高誘電材料膜上にシリコンからなるダミーゲートを形成し、高誘電材料膜及びダミーゲートを含む積層体を形成する工程、工程(C)該積層体の側面を覆うようにサイドウォールを形成する工程、工程(D)該サイドウォールを覆うように層間絶縁膜を形成する工程、工程(E)シリコン自然酸化膜のエッチング工程、工程(1)上記した本発明のエッチング液を用いたダミーゲートのエッチング工程、及び工程(F)該高誘電材料膜上にアルミニウム金属ゲートを形成し、高誘電材料膜及びアルミニウム金属ゲートを含む積層体する工程を順に有する製造方法が挙げられる。上記の工程(A)~(F)については、特に制限はなく、トランジスタの製造方法における各工程で一般的に採用される方法に準じればよい。
図1に示されるように、ダミーゲート1は多結晶シリコンなどのシリコン材料からなるが、該シリコン材料はトランジスタの製造過程において空気と接触するため、その表面が自然酸化し、シリコン自然酸化膜が形成する場合がある。そこで、本発明の製造方法においては、本発明のエッチング液を用いたダミーゲート1をエッチング工程(工程(1))の前に、シリコン自然酸化膜6を予めエッチングすることが好ましい。このような工程を有することで、本発明のエッチング液を用いたダミーゲートのエッチング工程が効率的に行うことが可能となるので、高精度、高品質のトランジスタを歩留まりよく製造することが可能となる。
水溶性有機溶媒としては、好ましくはエタノール、2-プロパノール、エチレングリコール、ジエチレングリコールなどのアルコール類;ジエチレングリコールモノメチルエーテル、ジエチレングリコールモノブチルエーテル、ジプロピレングリコールモノメチルエーテル、ジプロピレングリコールモノプロピルエーテルなどのグリコールエーテル類;N,N-ジメチルホルムアミド、N,N-ジメチルアセトアミド、N-メチル-2-ピロリドンなどのアミド類;ジメチルスルホキシドなどが好ましく挙げられる。これらの水溶性有機溶媒は、単独でも2種類以上組み合わせて用いてもよい。
また、本工程(E)に用いられるエッチング液には、塩酸、硝酸、硫酸、リン酸などの無機酸;酢酸、プロピオン酸、シュウ酸、メタンスルホン酸などの有機酸を、5重量%以下程度の範囲で加えてもよい。これらの酸は、単独でも2種類以上組み合わせて用いてもよい。
本発明の製造方法により得られるトランジスタは、基板7上に、少なくとも高誘電材料膜2とアルミニウム金属ゲート(図示せず)とが積層してなる積層体、該積層体の側面を覆うように設けられるサイドウォール3、該サイドウォール3を覆うように設けられる層間絶縁膜4を有するもの、すなわち、本発明のエッチング液によりエッチングする工程に供される図1に示される構造体において、ダミーゲート1をアルミニウム金属ゲートに入れ替えたものである。また、図1に示されるように、本発明の製造方法により得られるトランジスタは、ソース/ドレイン6、及びアイソレーション5を有しており、高誘電材料膜2は、該ソース/ドレイン6の間を覆うように、基板7の表面上に設けられている。
高誘電材料膜2とアルミニウム金属ゲート(図示せず)とが積層してなる積層体において、該アルミニウム金属ゲートを形成する金属以外の金属材料からなる金属ゲートがさらに積層したり、例えば特性制御膜といった機能を有する層が積層されていてもよい。また、半導体材料としては、ガリウム-砒素、ガリウム-リン、インジウム-リンなどの化合物半導体や、クロム酸化物などの酸化物半導体などが好ましく挙げられる。
本発明の製造方法により得られるトランジスタは、高精度、高品質のトランジスタである。
測定機器;
蛍光X線分析:エスアイアイ・ナノテクノロジー株式会社製、SEA1200VXを用いて測定した。
SEM観察:株式会社日立ハイテクノロジーズ社製、超高分解能電界放出形走査電子顕微鏡S-5500を用いて観察した。
FIB加工:株式会社日立ハイテクノロジーズ社製、集束イオンビーム加工装置FB-2100を用いて加工した。
STEM観察:株式会社日立ハイテクノロジーズ社製、走査透過電子顕微鏡HD-2300を用いて観察した。
判定;
(シリコンからなるダミーゲート1のエッチング状態)
○:ダミーゲート1が完全にエッチングされた。
×:ダミーゲート1のエッチングが不十分であった。
(アルミニウムの防食能力の評価)
○:アルミニウムのエッチレートが1nm/min未満であった。
×:アルミニウムのエッチレートが1nm/min以上であった。
エッチング液のアルミニウムに対する防食能力を調べるために、以下に説明する手法を用いた。基板となるシリコンウェハ上にPVDによりアルミニウム膜1000Åを堆積させた。このアルミニウム膜を第2表に示したエッチング液に25℃、30分間浸漬し、浸漬前後の膜厚を蛍光X線分析計で測定し、エッチング液によるアルミニウム膜のエッチング量を算出した。算出されたエッチング量と浸漬時間からエッチレートを計算し、アルミニウムのエッチレートが1nm/min未満の場合エッチング液のアルミニウムに対する防食能力があると判断した。
エッチング後のトランジスタ断面をSEMで観察することにより、シリコンからなるダミーゲート1、サイドウォール3、及び層間絶縁膜4の状態を判断した。
トランジスタ構造1Dを有する構造体を用い、実施例1で示したフッ化水素酸処理を行った後、エッチング液2Gのかわりに非特許文献2に記された水酸化テトラメチルアンモニウムの2重量%水溶液(第4表、エッチング液4A)を用いてエッチング処理を行った結果、第5表に示されるように、シリコンからなるダミーゲート1のエッチング能力が不足しており、アルミニウムのエッチレートが1nm/min以上であった。このことより、非特許文献2記載のエッチング液は、本発明の対象である高誘電材料とアルミニウムを含有する金属ゲートを含んだトランジスタ形成工程におけるシリコンエッチングには使用できないことがわかる。
トランジスタ構造1Bを有する構造体を用い、実施例1で示したフッ化水素酸処理を行った後、エッチング液2Gのかわりに特許文献2に記された水酸化テトラメチルアンモニウム0.5重量%とシリコン0.1重量%を含む水溶液(第4表、エッチング液4B)を用いてエッチング処理を行った結果、第5表に示されるように、アルミニウムのエッチレートは1nm/min未満であったが、シリコンからなるダミーゲート1のエッチング能力が不足していた。このことより、特許文献2記載のエッチング液は、本発明の対象である高誘電材料と金属ゲートを含んだトランジスタ形成工程におけるシリコンエッチングには使用できないことがわかる。
トランジスタ構造1Cを有する構造体を用い、実施例1で示したフッ化水素酸処理を行った後、エッチング液2Gのかわりに特許文献3に記された水酸化テトラメチルアンモニウム10重量%とヒドロキシルアミン10重量%とソルビトール5重量%の水溶液(第4表、エッチング液4C)を用いてエッチング処理を行った結果、第5表に示されるように、シリコンからなるダミーゲート1はエッチングされていたが、アルミニウムのエッチレートが1nm/min以上であった。このことより、特許文献3記載の水溶液は、本発明の対象である高誘電材料と金属ゲートを含んだトランジスタ形成工程におけるシリコンエッチングには使用できないことがわかる。
トランジスタ構造1Gを有する構造体を用い、実施例1で示したフッ化水素酸処理を行った後、エッチング液2Gのかわりに特許文献4に記された水酸化テトラメチルアンモニウム2.4重量%とソルビトール5重量%の水溶液(第4表、エッチング液4D)を用いてエッチング処理を行った結果、第5表に示されるように、シリコンからなるダミーゲート1のエッチング能力が不足しており、アルミニウムのエッチレートが1nm/min以上であった。このことより、特許文献4記載の水溶液は、本発明の対象である高誘電材料と金属ゲートを含んだトランジスタ形成工程におけるシリコンエッチングには使用できないことがわかる。
トランジスタ構造1Eを有する構造体を用い、実施例1で示したフッ化水素酸処理を行った後、エッチング液2Gのかわりに特許文献5に記されたヘキサメチレンジアミン(1,6-ヘキサンジアミン)5重量%とソルビトール30重量%の水溶液(第4表、エッチング液4E)を用いてエッチング処理を行った結果、第5表に示されるように、アルミニウムのエッチレートは1nm/min未満であったが、シリコンからなるダミーゲート1のエッチング能力が不足していた。このことより、特許文献5記載の剥離液は、本発明の対象である高誘電材料と金属ゲートを含んだトランジスタ形成工程におけるシリコンエッチングには使用できないことがわかる。
トランジスタ構造1Iを有する構造体を用い、実施例1で示したフッ化水素酸処理を行った後、エッチング液2Gのかわりに特許文献6に記された水酸化テトラメチルアンモニウム4重量%とトリメチルアミン0.01重量%とプロピレングリコール80重量%とグリセリン4重量%の水溶液(第4表、エッチング液4F)を用いてエッチング処理を行った結果、第5表に示されるように、アルミニウムのエッチレートは1nm/min未満であったが、シリコンからなるダミーゲート1のエッチング能力が不足していた。このことより、特許文献6記載の水溶液は、本発明の対象である高誘電材料と金属ゲートを含んだトランジスタ形成工程におけるシリコンエッチングには使用できないことがわかる。
トランジスタ構造1Fを有する構造体を用い、実施例1で示したフッ化水素酸処理を行った後、エッチング液2Gのかわりに1,3-プロパンジアミン0.5重量%の水溶液(第4表、エッチング液4G)を用いてエッチング処理を行った結果、第5表に示されるように、シリコンからなるダミーゲート1のエッチング能力が不足しており、アルミニウムのエッチレートが1nm/min以上であった。このことより、アルカリ化合物水溶液は、本発明の対象である高誘電材料と金属ゲートを含んだトランジスタ形成工程におけるシリコンエッチングには使用できないことがわかる。
トランジスタ構造1Hを有する構造体を用い、実施例1で示したフッ化水素酸処理を行った後、エッチング液2Gのかわりにソルビトール10重量%の水溶液(第4表、エッチング液4H)を用いてエッチング処理を行った結果、第5表に示されるように、アルミニウムのエッチレートは1nm/min未満であったが、シリコンからなるダミーゲート1のエッチング能力が不足していた。このことより、多価アルコール水溶液は、本発明の対象である高誘電材料と金属ゲートを含んだトランジスタ形成工程におけるシリコンエッチングには使用できないことがわかる。
トランジスタ構造1Aを有する構造体を用い、実施例1で示したフッ化水素酸処理を行った後、エッチング液2Gのかわりに1,3-プロパンジアミン5重量%とイノシトール10重量%の水溶液(第4表、エッチング液4I)を用いてエッチング処理を行った結果、第5表に示されるように、シリコンからなるダミーゲート1はエッチングされていたが、アルミニウムのエッチレートが1nm/min以上であった。このことより、アルカリ化合物と環状多価アルコールの水溶液は、本発明の対象である高誘電材料と金属ゲートを含んだトランジスタ形成工程におけるシリコンエッチングには使用できないことがわかる。
トランジスタ構造1Aを有する構造体を用い、実施例1で示したフッ化水素酸処理を行った後、エッチング液2Gのかわりに1,3-プロパンジアミン5重量%とスクロース10重量%の水溶液(第4表、エッチング液4J)を用いてエッチング処理を行った結果、第5表に示されるように、シリコンからなるダミーゲート1はエッチングされていたが、アルミニウムのエッチレートが1nm/min以上であった。このことより、アルカリ化合物と非還元糖の水溶液は、本発明の対象である高誘電材料と金属ゲートを含んだトランジスタ形成工程におけるシリコンエッチングには使用できないことがわかる。
Claims (8)
- 基板上に、少なくとも高誘電材料膜とシリコンからなるダミーゲートとが積層してなるダミーゲート積層体、該積層体の側面を覆うように設けられるサイドウォール、及び該サイドウォールを覆うように設けられる層間絶縁膜を有する構造体を用い、該ダミーゲートをアルミニウム金属ゲートに入れ替えることを特徴とするトランジスタの製造方法における、該シリコンからなるダミーゲートのエッチングに用いられ、アンモニア、ジアミン、及び一般式(1)で表されるポリアミンから選ばれる少なくとも1種であるアルカリ化合物を0.1~40重量%、一般式(2)で表される多価アルコールから選ばれる少なくとも1種を5~50重量%、ならびに水40~94.9重量%を含有するシリコンエッチング液。
H2N-(CH2CH2NH)m-H ・・・(1)
(mは2~5の整数である。)
H-(CH(OH))n-H ・・・(2)
(nは3~6の整数である。) - ジアミン及び一般式(1)で表されるポリアミンが、エチレンジアミン、1,2-プロパンジアミン、1,3-プロパンジアミン、ジエチレントリアミン、及びトリエチレンテトラミンから選ばれる少なくとも1種である請求項1に記載のシリコンエッチング液。
- 一般式(2)で表される多価アルコールが、グリセリン、meso-エリトリトール、キシリトール、及びソルビトールから選ばれる少なくとも1種である請求項1に記載のシリコンエッチング液。
- 高誘電材料膜を形成する高誘電材料が、HfO2、HfSiO、HfSiON、HfLaO、HfLaON、HfTiSiON、HfAlSiON、HfZrO、又はAl2O3である請求項1に記載のシリコンエッチング液。
- 基板上に、少なくとも高誘電材料膜とシリコンからなるダミーゲートとが積層してなるダミーゲート積層体、該積層体の側面を覆うように設けられるサイドウォール、及び該サイドウォールを覆うように設けられる層間絶縁膜を有する構造体を用い、以下の工程(I)を有し、かつ該ダミーゲートをアルミニウム金属ゲートに入れ替えることを特徴とするトランジスタの製造方法。
工程(I)シリコンを、アンモニア、ジアミン、及び一般式(1)で表されるポリアミンから選ばれる少なくとも1種であるアルカリ化合物を0.1~40重量%、一般式(2)で表される多価アルコールから選ばれる少なくとも1種を5~50重量%、ならびに水40~94.9重量%を含有するエッチング液を用いてエッチングする工程
H2N-(CH2CH2NH)m-H ・・・(1)
(mは2~5の整数である。)
H-(CH(OH))n-H ・・・(2)
(nは3~6の整数である。) - 高誘電材料膜を形成する高誘電材料が、HfO2、HfSiO、HfSiON、HfLaO、HfLaON、HfTiSiON、HfAlSiON、HfZrO、又はAl2O3である請求項5に記載のトランジスタの製造方法。
- ジアミン及び一般式(1)で表されるポリアミンが、エチレンジアミン、1,2-プロパンジアミン、1,3-プロパンジアミン、ジエチレントリアミン、及びトリエチレンテトラミンから選ばれる少なくとも1種である請求項5に記載のトランジスタの製造方法。
- 一般式(2)で表される多価アルコールが、グリセリン、meso-エリトリトール、キシリトール、及びソルビトールから選ばれる少なくとも1種である請求項5に記載のトランジスタの製造方法。
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EP11821468.3A EP2613345A4 (en) | 2010-08-31 | 2011-07-26 | SILICON ETCHING AGENT AND PROCESS FOR PRODUCING TRANSISTORS USING THE SAME |
JP2012531752A JPWO2012029450A1 (ja) | 2010-08-31 | 2011-07-26 | シリコンエッチング液及びそれを用いたトランジスタの製造方法 |
CN2011800417067A CN103081075A (zh) | 2010-08-31 | 2011-07-26 | 硅蚀刻液以及使用其的晶体管的制造方法 |
US13/819,107 US20130203263A1 (en) | 2010-08-31 | 2011-07-26 | Silicon etchant and method for producing transistor by using same |
KR1020137004129A KR20130114083A (ko) | 2010-08-31 | 2011-07-26 | 실리콘 에칭액 및 이를 이용한 트랜지스터의 제조 방법 |
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EP (1) | EP2613345A4 (ja) |
JP (1) | JPWO2012029450A1 (ja) |
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WO2020044789A1 (ja) * | 2018-08-31 | 2020-03-05 | 株式会社Screenホールディングス | 基板処理方法および基板処理装置 |
JP2020038956A (ja) * | 2018-08-31 | 2020-03-12 | 株式会社Screenホールディングス | 基板処理方法および基板処理装置 |
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WO2012023387A1 (ja) * | 2010-08-20 | 2012-02-23 | 三菱瓦斯化学株式会社 | トランジスタの製造方法 |
US20150203753A1 (en) * | 2014-01-17 | 2015-07-23 | Nanya Technology Corporation | Liquid etchant composition, and etching process in capacitor process of dram using the same |
KR102468776B1 (ko) * | 2015-09-21 | 2022-11-22 | 삼성전자주식회사 | 폴리실리콘 습식 식각용 조성물 및 이를 이용한 반도체 소자의 제조 방법 |
JP6769760B2 (ja) | 2016-07-08 | 2020-10-14 | 関東化学株式会社 | エッチング液組成物およびエッチング方法 |
US11037792B2 (en) | 2018-10-25 | 2021-06-15 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure etching solution and method for fabricating a semiconductor structure using the same etching solution |
CN112410036B (zh) * | 2020-10-29 | 2021-09-07 | 湖北兴福电子材料有限公司 | 一种低选择性的bpsg和peteos薄膜的蚀刻液 |
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CN103081075A (zh) | 2013-05-01 |
JPWO2012029450A1 (ja) | 2013-10-28 |
US20130203263A1 (en) | 2013-08-08 |
EP2613345A4 (en) | 2015-03-18 |
KR20130114083A (ko) | 2013-10-16 |
EP2613345A1 (en) | 2013-07-10 |
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