WO2012024891A1 - 一种硅基液晶显示器件的场缓存像素电路 - Google Patents

一种硅基液晶显示器件的场缓存像素电路 Download PDF

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Publication number
WO2012024891A1
WO2012024891A1 PCT/CN2011/001366 CN2011001366W WO2012024891A1 WO 2012024891 A1 WO2012024891 A1 WO 2012024891A1 CN 2011001366 W CN2011001366 W CN 2011001366W WO 2012024891 A1 WO2012024891 A1 WO 2012024891A1
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Prior art keywords
transistor
circuit
voltage
liquid crystal
display device
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PCT/CN2011/001366
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English (en)
French (fr)
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赵博华
黄苒
杜寰
罗家俊
林斌
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中国科学院微电子研究所
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Priority to US13/701,009 priority Critical patent/US20130069966A1/en
Publication of WO2012024891A1 publication Critical patent/WO2012024891A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/001—Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/18—Use of a frame buffer in a display terminal, inclusive of the display panel

Definitions

  • the present invention relates to the field of liquid crystal on silicon (LCoS) technology, and more particularly to a field buffer pixel circuit of a silicon-based liquid crystal display device.
  • LCD liquid crystal on silicon
  • LCoS is a new display technology that combines CMOS integrated circuit technology with liquid crystal display technology. Compared with transmissive LCD and DLP, LCoS has the characteristics of high light utilization efficiency, small size, high aperture ratio and low manufacturing cost. The biggest advantage of LCoS is that the resolution can be made very high. In the application of portable projection equipment, this advantage is unmatched by other technologies.
  • the LC 0 S color display mainly has a sequential color method and a spatial color mixing method.
  • the spatial color mixing method affects the aperture ratio and the alignment of the color filter film and the bonding process are high. Therefore, the design of the LCoS pixel circuit mainly adopts timing color. Methods. Since the time-series color method shortens the illumination time of the light source, the mainstream solution adopts the field buffer pixel circuit, which is characterized in that the display data of the next frame is first stored on the capacitor, and the stored data is read in by the read signal at one time. Display on the pixel capacitor.
  • the basic principle is to hide the reading time of the next frame of data into the liquid crystal response time and illumination time of the previous frame, thereby prolonging the illumination time and improving the display contrast.
  • the data voltage is transmitted from the gate to the source through the MOS transistor.
  • the voltage obtained by the source has a threshold loss, and the threshold voltage of the loss is also different due to the difference of the data voltage. Therefore, the output pixel voltage has a nonlinear relationship with the input data voltage, which affects the consistency of the pixel output voltage, thereby affecting the final display effect.
  • a main purpose of the present invention is to provide a field buffer pixel circuit to reduce threshold loss and improve the disadvantage that the existing circuit data voltage has a threshold voltage loss from the gate of the MOS transistor to the source, thereby affecting the consistency of the pixel output voltage.
  • the stability and consistency of the pixel output voltage which in turn improves the display.
  • the present invention provides a field buffer pixel circuit of a silicon-based liquid crystal display device, the circuit comprising a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a storage capacitor C1 and a pixel capacitor C2, wherein the first transistor M1 constitutes a precharge circuit, and the second transistor M2 and the third transistor M3 form a threshold voltage generation circuit, the storage The capacitor C1 constitutes a sample-and-hold circuit, and the fourth transistor M4, the fifth transistor M5 and the pixel capacitor C2 constitute an input data voltage read-in circuit, and the sixth transistor M6 constitutes a discharge circuit.
  • the drain of the first transistor M1 is connected to the gate and the drain of the second transistor M2, and is connected to one end of the storage capacitor C1 and the gate of the fourth transistor M4.
  • the source of the first transistor M1 is externally connected to the power supply voltage
  • the gate of the first transistor M1 is externally connected to the charging control signal
  • one end of the storage capacitor C1 is precharged to the power supply voltage through the first transistor M1;
  • the other end of the storage capacitor C1 is grounded.
  • the source of the second transistor M2 is connected to the drain of the third transistor M3.
  • the source of the third transistor M3 is connected to the input data voltage, and the gate is externally connected to the write signal to control the writing of data.
  • the drain terminal of the fourth transistor M4 is connected to the power supply voltage, and the source is connected to the drain of the fifth transistor M5.
  • the gate of the fifth transistor M5 is externally connected with a read control signal, the source is connected to the pixel capacitor C2 terminal, and the drain of the sixth transistor M6; the other end of the pixel capacitor C2 is grounded. .
  • the source of the sixth transistor M6 is grounded, and the gate is externally connected with a discharge control signal to discharge the voltage on the pixel capacitor C2 through the sixth transistor M6.
  • the first transistor M1 is a PMOS transistor
  • the second transistor M2 the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are all NMOS transistors.
  • the storage capacitor C1 is charged to the power supply voltage during the pre-charging phase; when the third transistor M3 is turned on, the input data voltage rfato is written, and the storage capacitor C1 is discharged to v data + v TH2 , r//2 is the threshold voltage of the second transistor; in the data reading phase, the fifth ⁇ .
  • the transistor 5 When the transistor 5 is turned on, the voltage of the storage capacitor C1 is to + ra2 , and the pixel capacitor C2 is charged to y data.
  • the present invention has the following beneficial effects:
  • the field buffer pixel circuit of the liquid crystal display device of the present invention wherein data writing is performed by discharging a storage capacitor precharged to a power supply voltage, since the storage capacitor is discharged to the input data voltage through the second transistor.
  • the second transistor is turned off when summing with the threshold voltage (which varies as the input data voltage changes), so the value stored on the storage capacitor during the data write phase is the sum of the input data voltage and the threshold voltage.
  • the voltage that is finally transmitted to the pixel capacitor is the voltage on the storage capacitor due to the loss of the threshold when the voltage is transmitted through the gate of the fourth transistor.
  • the difference between the threshold voltages is also the input data voltage.
  • Previous pixel circuits have a threshold voltage loss due to voltage transfer across the transistor, resulting in an inconsistency in the final output voltage.
  • the present invention utilizes the method of first adding a threshold voltage when storing the input data voltage, thereby canceling the threshold loss existing when the voltage is transferred, thereby improving the stability and consistency of the output voltage and improving the display effect.
  • 1 is a structural diagram of a field buffer pixel circuit
  • FIG. 2 is a structural diagram of a field buffer pixel circuit of a silicon-based liquid crystal display device provided by the present invention
  • Figure 3 is a signal timing diagram of a field buffer pixel circuit of a liquid crystal on silicon display device provided by the present invention. detailed description
  • FIG. 2 is a structural diagram of a field buffer pixel circuit of a silicon-based liquid crystal display device provided by the present invention, the circuit including a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, Fifth transistor M5, sixth transistor M6, storage a capacitor CI and a pixel capacitor C2, wherein the first transistor M1 has a path, the second transistor M2 and the third transistor M3 form a threshold voltage generating circuit, and the storage capacitor C1 constitutes a sample and hold
  • the fourth transistor M4, the fifth transistor M5 and the pixel capacitor C2 form an input data voltage read-in circuit, and the sixth transistor M6 constitutes a discharge circuit.
  • the drain of the first transistor M 1 is connected to the gate and the drain of the second transistor M 2 , and is connected to one end of the storage capacitor C1 and the gate of the fourth transistor M4.
  • a source of a transistor M1 is externally connected to a power supply voltage
  • a gate of the first transistor M1 is externally connected with a charging control signal
  • one end of the storage capacitor C1 is precharged to a power supply voltage through the first transistor M1; the storage capacitor The other end of C1 is grounded.
  • the source of the second transistor M2 is connected to the drain of the third transistor M3.
  • the source of the third transistor M3 is connected to the input data voltage, and the gate is externally connected to the write signal to control the writing of data.
  • the drain terminal of the fourth transistor M4 is connected to the power supply voltage, and the source is connected to the drain of the fifth transistor M5.
  • the gate of the fifth transistor M5 is externally connected to the read control signal, and the source is connected to the pixel capacitor C2 terminal and the drain of the sixth transistor M6; the other end of the pixel capacitor C2 is grounded.
  • the source of the sixth transistor M6 is grounded, and the gate is externally connected to the discharge control signal to discharge the voltage on the pixel capacitor C2 through the sixth transistor M6.
  • the first transistor M1 adopts a PMOS transistor
  • the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 each adopt an NMOS transistor.
  • the storage capacitor Cl and the pixel capacitor C2 are determined by the pixel voltage error tolerance.
  • the storage capacitor C1 is charged to the power supply voltage during the pre-charging phase; when the third transistor M3 is turned on, the input data voltage ⁇ w is written, and at this time, the storage capacitor C1 is discharged to ⁇ + ⁇ 2 , ) 3 ⁇ 4 2 is the second The threshold voltage of the transistor; during the data read-in phase, the fifth transistor M5 is turned on, and the voltage of the storage capacitor C1 is at this time. + 2 , pixel capacitor C2 is charged to ⁇
  • FIG. 3 is a signal timing diagram of a field buffer pixel circuit of a silicon-based liquid crystal display device provided by the present invention.
  • Data signal 1, precharge signal 2, write signal 3, read signal 4, and discharge signal 5 are as shown in Figs.
  • the data signal 1 is connected to the source of the third transistor M3, the precharge signal 2 is connected to the gate of the first transistor M1, the write signal 3 is connected to the gate of the third transistor M3, and the read signal 4 is connected to the fifth transistor M5.
  • the gate, the discharge signal 5 is connected to the gate of the sixth transistor M6.
  • the gate read signal 4 of the fifth transistor M5 includes the gate discharge signal 5 of the sixth transistor M6 in time series.
  • one frame time is divided into three sub-scores: data writing time, liquid crystal material response time, and light source illumination time, and the data writing time and the light source illumination time partially coincide.
  • the precharge signal 2 is first changed to a low level, and the power supply voltage charges the storage capacitor C1 to the power supply voltage through the first transistor M1; then the write signal 3 becomes a high level, and the data signal 1 passes through the third transistor M3.
  • the second transistor M2 is turned off.
  • the voltage stored on the storage capacitor C1 is the sum of the data signal voltage and the threshold voltage of the second transistor M2; when all the data voltages of the row are written into the storage capacitors C1 of the respective pixels, the read signal 4 becomes High level, the fifth transistor M5 is turned on, the discharge signal 5 is also high level, and the sixth transistor M6 is also turned on.
  • the voltage on the pixel capacitor C2 is discharged to the low level through the sixth transistor M6, and then the discharge signal 5 Turning to a low level, the read signal 4 is still at a high level, and the voltage stored on the storage capacitor C1 is -charged to the pixel capacitor C2 through the fourth transistor M4 and the fifth transistor M5, when the pixel is electrically charged
  • the fourth transistor M4 since the gate voltage of the fourth transistor M4 is the sum of the data signal voltage and the threshold voltage of the M2 tube, the fourth transistor M4 is turned off, and the voltage stored on the pixel capacitor C2 is the data signal voltage.
  • the pixel capacitance enters the pixel voltage retention period.

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  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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Description

一种硅基液晶显示器件的场緩存像素电路 技术领域
本发明涉及硅基液晶微显示器件（ Liquid Crystal on Silicon, LCoS ) 技术领域， 特别是涉及一种硅基液晶显示器件的场緩存像素电路。 背景技术
LCoS是一种将 CMOS 集成电路技术和液晶显示技术相结合的新 型显示技术。 与穿透式 LCD和 DLP相比， LCoS具有光利用效率高、 体积小、 开口率高、 制造成本低等特点。 LCoS最大的优点是解析度可 以做得很高， 在便携型投影设备的应用上， 此优点是其他技术无法比 拟的。
目前实现 L C 0 S彩色显示主要有时序彩色法和空间混色法，其中空 间混色法影响开口率以及对滤色膜的对准以及粘贴工艺要求较高， 因 此 LCoS像素电路的设计主要是采用时序彩色的方法。而由于时序彩色 法缩短了光源的照明时间， 主流的解决方法采用场緩存像素电路， 其 特点是先将下一帧的显示数据存储在电容上， 再通过读信号一次性将 存储的数据读入到像素电容上进行显示。 其基本原理是将下一帧数据 的读入时间隐藏到上一帧的液晶响应时间和光照时间中， 从而延长光 照时间， 提高显示对比度。 现有技术（如图 1 )中， 数据电压通过 MOS 管从栅极传到源极， 此时源极得到的电压存在阈值损失， 并且由于数 据电压的不同， 损失的阈值电压也是不相同的， 因而输出的像素电压 与输入的数据电压存在非线性的关系， 影响了像素输出电压的一致性， 进而影响最终的显示效果。 发明内容
(一）要解决的技术问题
针对现有电路数据电压从 MOS管栅极传到源极存在阈值电压损失 进而影响像素输出电压一致性的缺点， 本发明的主要目的是提供一种 场緩存像素电路， 以减小阈值损失， 提高像素输出电压的稳定性和一 致性， 进而提高显示效果。 (二） 技术方案
为达到上述目的， 本发明提供了一种硅基液晶显示器件的场緩存 像素电路， 该电路包括第一晶体管 Ml、 第二晶体管 M2、 第三晶体管 M3、 第四晶体管 M4、 第五晶体管 M5、 第六晶体管 M6、 存储电容 C1 和像素电容 C2, 其中， 所述第一晶体管 Ml构成一预充电电路， 所述 第二晶体管 M2和所述第三晶体管 M3构成一阈值电压产生电路，所述 存储电容 C1构成一采样保持电路， 所述第四晶体管 M4、 第五晶体管 M5和像素电容 C2构成一输入数据电压读入电路，所述第六晶体管 M6 构成一放电电路。
上述方案中，所述第一晶体管 Ml的漏极与所述第二晶体管 M2栅 极和漏极相连接， 同时与所述存储电容 C1 一端以及所述第四晶体管 M4的栅极相连接， 所述第一晶体管 Ml的源极外接电源电压， 所述第 一晶体管 Ml的栅极外接充电控制信号，并通过所述第一晶体管 Ml将 所述存储电容 C1的一端预先充电至电源电压； 所述存储电容 C1的另 一端接地。
上述方案中，所述第二晶体管 M2的源极与所述第三晶体管 M3的 漏极相连接。
上述方案中， 所述第三晶体管 M3的源极与输入数据电压相接，栅 极外接写信号， 控制数据的写入。
上述方案中， 所述第四晶体管 M4的漏端与电源电压相接， 源极与 所述第五晶体管 M5的漏极相连。
上述方案中， 所述第五晶体管 M5的栅极外接读入控制信号， 源极 与所述像素电容 C2—端、 所述第六晶体管 M6的漏极相连； 所述像素 电容 C2的另一端接地。
上述方案中， 所述第六晶体管 M6的源极接地，栅极外接放电控制 信号， 使所述像素电容 C2上的电压通过所述第六晶体管 M6放电。
上述方案中， 所述第一晶体管 Ml 采用 PMOS晶体管， 所述第二 晶体管 M2、 第三晶体管 M3、 第四晶体管 M4、 第五晶体管 M5、 第六 晶体管 M6均采用 NMOS晶体管。
上述方案中， 存储电容 C1在预充电阶段充电至电源电压； 在第三 晶体管 M3 导通时写入输入数据电压 rfato， 此时存储电容 C1 放电至 vdata + vTH2 , r//2为第二晶体管的阔值电压； 在数据读入阶段， 第五 Β。曰俸 管 Μ5导通， 此时存储电容 C1的电压为 to + ra2 , 像素电容 C2充电 至 y data。
(三）有益效果
从上述技术方案可以看出， 本发明具有以下有益效果：
1、 本发明提供的硅基液晶显示器件的场緩存像素电路， 其数据写 入是通过将预充到电源电压的存储电容放电实现的， 由于在将存储电 容通过第二晶体管放电至输入数据电压和阔值电压 （其随着输入数据 电压变化而变化）之和时， 第二晶体管关断， 因此在数据写入阶段存 储到存储电容上的值为输入数据电压和阈值电压之和。 在再将存储电 容上的电压通过第四晶体管转移到像素电容上时， 由于通过第四晶体 管栅极传输电压时存在阔值损失， 因此最终传输到像素电容上的电压 为存储电容上的电压与阈值电压之差， 也即为输入数据电压。
2、 以前像素电路由于在通过晶体管转移电压时存在阈值电压损 失， 从而造成最终输出电压的不一致性。 而本发明利用在存储输入数 据电压时先加上一个阈值电压的做法， 抵消了转移电压时存在的阈值 损失， 从而提高了输出电压的稳定性和一致性， 改善了显示效果。 附图说明
图 1是背景技术场緩存像素电路结构图；
图 2是本发明提供的硅基液晶显示器件的场緩存像素电路的结构 图；
图 3 是本发明提供的硅基液晶显示器件的场緩存像素电路的信号 时序图。 具体实施方式
为使本发明的目的、 技术方案和优点更加清楚明白， 以下结合具 体实施例， 并参照附图， 对本发明进一步详细说明。
如图 2所示， 图 2是本发明提供的硅基液晶显示器件的场緩存像 素电路的结构图， 该电路包括第一晶体管 Ml、 第二晶体管 M2、 第三 晶体管 M3、 第四晶体管 M4、 第五晶体管 M5、 第六晶体管 M6、 存储 电容 CI和像素电容 C2， 其中， 所述第一晶体管 Ml构底一 无 路，所述第二晶体管 M2和所述第三晶体管 M3构成一阈值电压产生电 路， 所述存储电容 C1构成一采样保持电路， 所述第四晶体管 M4、 第 五晶体管 M5和像素电容 C2构成一输入数据电压读入电路， 所述第六 晶体管 M6构成一放电电路。
所述第一晶体管 M 1的漏极与所述第二晶体管 M 2栅极和漏极相连 接， 同时与所述存储电容 C1一端以及所述第四晶体管 M4的栅极相连 接， 所述第一晶体管 Ml的源极外接电源电压， 所述第一晶体管 Ml的 栅极外接充电控制信号， 并通过所述第一晶体管 Ml 将所述存储电容 C1 的一端预先充电至电源电压； 所述存储电容 C1 的另一端接地。 所 述第二晶体管 M2的源极与所述第三晶体管 M3的漏极相连接。所述第 三晶体管 M3的源极与输入数据电压相接，栅极外接写信号，控制数据 的写入。所述第四晶体管 M4的漏端与电源电压相接， 源极与所述第五 晶体管 M5的漏极相连。所述第五晶体管 M5的栅极外接读入控制信号， 源极与所述像素电容 C2—端、 所述第六晶体管 M6的漏极相连； 所^ 像素电容 C2的另一端接地。 所述第六晶体管 M6的源极接地， 栅极外 接放电控制信号， 使所述像素电容 C2 上的电压通过所述第六晶体管 M6放电。 所述第一晶体管 Ml 采用 PMOS 晶体管， 所述第二晶体管 M2、 第三晶体管 M3、 第四晶体管 M4、 第五晶体管 M5、 第六晶体管 M6均采用 NMOS晶体管。 所述存储电容 Cl、 像素电容 C2由像素电 压误差容许值决定。
其中， 存储电容 C1在预充电阶段充电至电源电压； 在第三晶体管 M3导通时写入输入数据电压^ w， 此时存储电容 C1放电至^ ^ +^^2， )¾2为第二晶体管的阄值电压；在数据读入阶段，第五晶体管 M5导通， 此时存储电容 C1的电压为 。+ 2， 像素电容 C2充电至^^
如图 3所示， 图 3是本发明提供的硅基液晶显示器件的场緩存像 素电路的信号时序图。 数据信号 1， 预充电信号 2， 写信号 3， 读信号 4， 放电信号 5如图 2、 3所示。 数据信号 1连接在第三晶体管 M3的源 极，预充电信号 2连接在第一晶体管 Ml的栅极， 写信号 3连接在第三 晶体管 M3的栅极， 读信号 4连接在第五晶体管 M5的栅极， 放电信号 5连接在第六晶体管 M6的栅极。 第五晶体管 M5的栅极读信号 4在时 序上包含第六晶体管 M6的栅极放电信号 5。 在本发明提供的这种场緩存像素电路中， 一帧时间分为三邵分： 数据写入时间、 液晶材料响应时间和光源照明时间， 数据写入时间和 光源照明时间部分重合。 数据写入阶段首先预充电信号 2变为低电平， 电源电压通过第一晶体管 Ml对存储电容 C1充电至电源电压； 接着写 信号 3变为高电平， 数据信号 1通过第三晶体管 M3传到第二晶体管 M2的漏极和存储电容 C1上， 当存储电容 C1上电压通过第二晶体管 M2和第三晶体管 M3放电至数据信号电压与第二晶体管 M2的阈值电 压之和时， 第二晶体管 M2关断， 此时保存到存储电容 C1上的电压为 数据信号电压与第二晶体管 M2的阈值电压之和；当所有行的数据电压 全部写入各像素存储电容 C1 后， 读信号 4 变为高电平， 第五晶体管 M5导通， 放电信号 5也为高电平， 第六晶体管 M6也导通， 首先像素 电容 C2上的电压通过第六晶体管 M6放电至低电平， 然后放电信号 5 变为低电平， 读信号 4仍为高电平， 保存在存储电容 C1上的电压通过 第四晶体管 M4、 第五晶体管 M5对像素电容 C2进行-充电， 当像素电 容 C2充电至数据信号电压时， 由于第四晶体管 M4栅极电压为数据信 号电压与 M2管的阈值电压之和， 因此第四晶体管 M4关断， 保存到像 素电容 C2上的电压为数据信号电压， 像素电容进入像素电压保持期。
以上所述的具体实施例， 对本发明的目的、 技术方案和有益效果 进行了进一步详细说明， 所应理解的是， 以上所述仅为本发明的具体 实施例而已， 并不用于限制本发明， 凡在本发明的精神和原则之内， 所做的任何修改、 等同替换、 改进等， 均应包含在本^明的保护范围 之内。

Claims

权 利 要 求
1. 一种硅基液晶显示器件的场緩存像素电路， 其特征在于， 该电 路包括第一晶体管 （Ml) 、 第二晶体管 （M2) 、 第三晶体管 （M3) 、 第四晶体管 （M4) 、 第五晶体管 （M5) 、 第六晶体管 （M6) 、 存储 电容（C1)和像素电容（C2) ， 其中， 所述第一晶体管 （Ml)构成一 预充电电路， 所述第二晶体管 （M2)和所述第三晶体管 （M3)构成一 阈值电压产生电路， 所述存储电容（C1 )构成一采样保持电路， 所述 第四晶体管 （M4) 、 第五晶体管（M5)和像素电容（C2)构成一输入 数据电压读入电路， 所述第六晶体管 （M6)构成一放电电路。
2. 根据权利要求 1所述的硅基液晶显示器件的场緩存像素电路， 其特征在于， 所述第一晶体管 （Ml) 的漏极与所述第二晶体管 （M2) 栅极和漏极相连接， 同时与所述存储电容（C1) 一端以及所述第四晶 体管（M4)的栅极相连接， 所述第一晶体管（Ml)的源极外接电源电 压， 所述第一晶体管 （Ml) 的栅极外接充电控制信号， 并通过所述第 一晶体管 （Ml)将所述存储电容（C1) 的一端预先充电至电源电压； 所述存储电容（C1) 的另一端接地。
3. 根据权利要求 2所述的硅基液晶显示器件的场緩存像素电路， 其特征在于， 所述第二晶体管 （M2) 的源极与所述第三晶体管 （M3) 的漏极相连接。
4. 根据权利要求 3所述的硅基液晶显示器件的场緩存像素电路， 其特征在于， 所述第三晶体管 （M3) 的源极与输入数据电压相接， 栅 极外接写信号， 控制数据的写入。
5. 根据权利要求 4所述的硅基液晶显示器件的场緩存像素电路， 其特征在于， 所述第四晶体管 （M4) 的漏端与电源电压相接， 源极与 所述第五晶体管 （M5) 的漏极相连。
6. 根据权利要求 5所述的硅基液晶显示器件的场緩存像素电路， 其特征在于， 所述第五晶体管 （M5) 的栅极外接读入控制信号， 源极 与所述像素电容（C2) —端、 所述第六晶体管 （M6) 的漏极相连； 所 述像素电容（C2) 的另一端接地。
7. 根据权利要求 6所述的硅基液晶显示器件的场緩存像素电路， 其特征在于， 所述第六晶体管 （M6) 的源极接地， 栅极外接放电控制 信号， 使所述像素电容（C2)上的电压通过所迷第六日¾俸官 （M6〗 电。
8. 根据权利要求 1所述的硅基液晶显示器件的场緩存像素电路， 其特征在于， 所述第一晶体管 （Ml)采用 PMOS晶体管， 所述第二晶 体管 （M2) 、 第三晶体管 （M3) 、 第四晶体管 （M4) 、 第五晶体管
(M5) 、 第六晶体管 （M6) 均采用 NMOS晶体管。
9. 根据权利要求 1所述的硅基液晶显示器件的场緩存像素电路， 其特征在于， 存储电容（C1 )在预充电阶段充电至电源电压； 在第三 晶体管 （M3) 导通时写入输入数据电压^ ,。， 此时存储电容（C1 )放 电至^ «a + ^/2， TO2为第二晶体管的阈值电压； 在数据读入阶段， 第五 晶体管 （M5)导通， 此时存储电容（C1 ) 的电压为 fl + m2， 像素电 容（C2) 充电至^ α。
PCT/CN2011/001366 2010-08-25 2011-08-17 一种硅基液晶显示器件的场缓存像素电路 WO2012024891A1 (zh)

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Families Citing this family (9)

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Publication number Priority date Publication date Assignee Title
CN102324226B (zh) * 2011-10-19 2012-12-05 中国科学院微电子研究所 硅基液晶显示器件的场缓存像素电路
TWI534789B (zh) * 2013-09-13 2016-05-21 國立交通大學 一種主動矩陣顯示器裝置的畫素電路及其驅動方法
CN104537997B (zh) * 2015-01-04 2017-09-22 京东方科技集团股份有限公司 一种像素电路及其驱动方法和显示装置
TWI584264B (zh) * 2016-10-18 2017-05-21 友達光電股份有限公司 顯示控制電路及其操作方法
CN107403611B (zh) * 2017-09-25 2020-12-04 京东方科技集团股份有限公司 像素记忆电路、液晶显示器和可穿戴设备
CN108806606B (zh) 2018-06-15 2019-09-27 中国科学院微电子研究所 像素补偿电路
CN109523951A (zh) * 2018-12-29 2019-03-26 云谷（固安）科技有限公司 一种像素电路和显示装置
CN113168809B (zh) * 2019-09-05 2022-11-04 京东方科技集团股份有限公司 像素驱动电路、像素驱动方法、显示装置及其控制方法
JP2021135465A (ja) * 2020-02-28 2021-09-13 深▲セン▼通鋭微電子技術有限公司 駆動回路および表示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1510652A (zh) * 2002-09-25 2004-07-07 三星电子株式会社 有机发光显示装置及其制造方法
KR20050049686A (ko) * 2003-11-22 2005-05-27 삼성에스디아이 주식회사 유기전계발광표시장치의 픽셀구동회로
US20060232521A1 (en) * 2005-04-11 2006-10-19 Jin Jang Circuit and method for driving organic light-emitting diode
CN1851546A (zh) * 2005-04-22 2006-10-25 中国科学院长春光学精密机械与物理研究所 新型硅基液晶微显示器件帧存储像素电路
US20080106504A1 (en) * 2006-11-02 2008-05-08 Chunghwa Picture Tubes, Ltd. Organic light emitting diode driving device
CN101276555A (zh) * 2007-03-28 2008-10-01 中国科学院微电子研究所 一种用于硅基液晶显示器件的帧存储像素电路

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100370286B1 (ko) * 2000-12-29 2003-01-29 삼성에스디아이 주식회사 전압구동 유기발광소자의 픽셀회로
US6911964B2 (en) * 2002-11-07 2005-06-28 Duke University Frame buffer pixel circuit for liquid crystal display
KR100515299B1 (ko) * 2003-04-30 2005-09-15 삼성에스디아이 주식회사 화상 표시 장치와 그 표시 패널 및 구동 방법

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1510652A (zh) * 2002-09-25 2004-07-07 三星电子株式会社 有机发光显示装置及其制造方法
KR20050049686A (ko) * 2003-11-22 2005-05-27 삼성에스디아이 주식회사 유기전계발광표시장치의 픽셀구동회로
US20060232521A1 (en) * 2005-04-11 2006-10-19 Jin Jang Circuit and method for driving organic light-emitting diode
CN1851546A (zh) * 2005-04-22 2006-10-25 中国科学院长春光学精密机械与物理研究所 新型硅基液晶微显示器件帧存储像素电路
US20080106504A1 (en) * 2006-11-02 2008-05-08 Chunghwa Picture Tubes, Ltd. Organic light emitting diode driving device
CN101276555A (zh) * 2007-03-28 2008-10-01 中国科学院微电子研究所 一种用于硅基液晶显示器件的帧存储像素电路

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