WO2012014448A1 - 半導体素子と半導体素子の製造方法 - Google Patents
半導体素子と半導体素子の製造方法 Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y20/00—Nanooptics, e.g. quantum optics or photonic crystals
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/0206—Substrates, e.g. growth, shape, material, removal or bonding
- H01S5/0215—Bonding to the substrate
- H01S5/0216—Bonding to the substrate using an intermediate compound, e.g. a glue or solder
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/0206—Substrates, e.g. growth, shape, material, removal or bonding
- H01S5/0217—Removal of the substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/30—Structure or shape of the active region; Materials used for the active region
- H01S5/34—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
- H01S5/343—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
- H01S5/34333—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser with a well layer based on Ga(In)N or Ga(In)P, e.g. blue laser
Definitions
- the present invention relates to a semiconductor element and a method for manufacturing the semiconductor element, and more particularly to a semiconductor element having a configuration in which a compound semiconductor layer is formed on a support substrate and a method for manufacturing the semiconductor element.
- Group III nitride semiconductors which are compound semiconductors, are widely used as materials for light-emitting elements such as blue and green LEDs (light-emitting diodes) and LD (laser diodes) because of their wide band gaps.
- a p-type semiconductor layer (p-type layer) and an n-type semiconductor layer (n-type layer) are laminated by epitaxial growth.
- this structure In order to manufacture this structure with good quality and low cost, it is generally performed by epitaxially growing a p-type layer and an n-type layer on a growth substrate made of a material other than a group III nitride semiconductor. .
- the growth substrate materials that can be used are limited.
- gallium nitride (GaN) which is representative of a group III nitride semiconductor, is grown on a growth substrate made of SiC, sapphire, or the like by MOCVD (metal organic chemical vapor deposition) or HVPE (hydride vapor deposition). be able to.
- sapphire is an insulator, it is necessary to provide two electrical contact portions on the upper surface of the semiconductor layer stacked on the sapphire, reducing the effective light emitting area on the same substrate area as compared with the conductor substrate, and the same. Since both electrodes are provided on the surface, there is a problem that the current density is locally increased and the element is deteriorated due to heat generation.
- a method for manufacturing a light-emitting element using lift-off technology is disclosed (for example, see Patent Document 1).
- a conductive substrate is newly bonded to the p-side electrode side as a support substrate.
- the lift-off technology when the sapphire is peeled off from the growth substrate, it is necessary to etch the lift-off layer from the periphery with an etching solution or the like. Therefore, there is a problem that the compound semiconductor layer may be cracked due to internal stress generated by the difference in thermal expansion coefficient between the growth substrate and the compound semiconductor layer during growth.
- an object of the present invention is to provide a semiconductor element and a method for manufacturing the semiconductor element, in which the compound semiconductor layer is not cracked by internal stress of the compound semiconductor layer at the time of lift-off.
- the semiconductor element and the semiconductor element manufacturing method according to the present invention are configured as follows.
- a first method for manufacturing a semiconductor element is a method for manufacturing a semiconductor element having a configuration in which a semiconductor layer is bonded to a support substrate, and an element region including a semiconductor layer is formed on a growth substrate via a lift-off layer.
- a lift-off step for separating the lower surface of the layer from the growth substrate and not separating the columnar material and the growth substrate; and a step of separating the columnar material and the support substrate.
- the columnar object forming step includes a sacrificial layer forming step of forming a sacrificial layer on a part of the columnar object, and separating the columnar object and the support substrate. In this step, the sacrificial layer is removed.
- the third method for producing a semiconductor element is preferably characterized in that, in the above method, the columnar body includes a core portion made of the same material as the semiconductor layer.
- the material constituting the semiconductor layer is formed on the growth substrate via the lift-off layer, and then etching is performed.
- the fifth method for manufacturing a semiconductor device preferably includes the step of removing the lift-off layer in the region where the columnar object is to be formed, in the step of forming the lift-off layer on the growth substrate. Is formed on the growth substrate via the lift-off layer and partially without the lift-off layer, and then etched to simultaneously form the element region and the core that is not lifted off in the lift-off process. It is characterized by.
- the lift-off layer is formed in the device region and in the region that is to be the region where the columnar object is to be formed. And selectively forming the material constituting the semiconductor layer on the growth substrate via the lift-off layer and partially forming the material without the lift-off layer, and then performing etching to lift off the element region and the lift-off layer. A core portion that is not lifted off in the process is formed at the same time.
- a seventh method for manufacturing a semiconductor element is a method for manufacturing a semiconductor element having a configuration in which a semiconductor layer is bonded to a support substrate, and an element region formed of a semiconductor layer is formed on a growth substrate via a lift-off layer.
- An element region forming process to be formed, a columnar object forming process for forming a columnar object on the support substrate, a semiconductor layer bonded to the support substrate, a bonding process for bonding the columnar object to the growth substrate, and the lift-off layer are removed.
- the method includes a lift-off process that separates the lower surface of the semiconductor layer from the growth substrate and that does not separate the columnar material and the growth substrate, and a step of separating the columnar material and the support substrate.
- the columnar body forming step includes a sacrificial layer forming step of forming a sacrificial layer on the support substrate, and the step of separating the columnar body and the support substrate. Then, the sacrificial layer is removed.
- the ninth method for manufacturing a semiconductor device is the above method, wherein the semiconductor layer preferably includes an n-type layer on the growth substrate side and a p-type layer formed on the n-type layer. .
- the tenth method for manufacturing a semiconductor element is characterized in that, in the above method, preferably, before the bonding step, conductive materials are respectively formed on the surface of the semiconductor layer and the surface of the support substrate in the element region.
- an n-type electrode bonded to the n-type layer is formed, a p-type electrode bonded to the p-type layer is formed, and the n-type electrode and the p-type electrode are formed.
- the leakage current is 10 ⁇ A or less when a reverse voltage of 10 volts is applied between
- the first semiconductor element is manufactured by the manufacturing method of the first to tenth semiconductor elements.
- the present invention it is possible to provide a semiconductor element and a method for manufacturing the semiconductor element in which the compound semiconductor layer is not cracked due to internal stress of the compound semiconductor layer during lift-off.
- n-type and p-type semiconductor layers used in this semiconductor element are obtained by epitaxial growth on a growth substrate.
- this growth substrate is removed, and a support substrate different from the growth substrate is connected to the side opposite to the side where the growth substrate was present.
- FIG. 1 is a flowchart showing a process of manufacturing a semiconductor device by the method of manufacturing a semiconductor device according to the first embodiment of the present invention.
- FIG. 2 is a cross-sectional view of the substrate at each step of the method of manufacturing a semiconductor device according to the first embodiment of the present invention.
- LED light emitting diode
- This LED uses light emission in a laminate of a nitride semiconductor n-type layer and a p-type layer.
- FIG. 2 the configuration of only one LED element is shown, but in practice, a plurality of LEDs can be formed on a single support substrate, and a plurality of elements are formed on the substrate. These can be used later by separating them into individual elements or by connecting them in series or in parallel.
- the semiconductor element manufacturing method includes a compound semiconductor layer forming process (step S11), an element region forming process (step S12), a columnar object forming process (step S13), and a sacrificial layer forming process (step).
- step S14 p-side electrode forming step (step S15), bonding layer forming step (step S16), support substrate bonding pre-step (step S17), bonding step (step S18), and peeling step (step S19).
- an n-side electrode forming process step S20
- a wire bonding process step S21.
- the peeling process (step S19) is performed from the lift-off process (step S191) and the sacrificial layer etching process (step S192).
- step S191 of the peeling process step S19
- the columnar objects are joined. It is equity. That is, in the lift-off process (step S191), the bottom surface of the semiconductor layer and the growth substrate are separated by removing the lift-off layer, and the columnar object and the growth substrate are not separated.
- a lift-off layer (metal buffer layer) and a compound semiconductor layer on the lift-off layer are formed on the growth substrate.
- the metal buffer layer 12 is formed on the growth substrate 11.
- a sapphire single crystal ((0001) substrate) is particularly preferably used.
- scandium (Sc) having a thickness of about 100 mm can be used.
- the metal buffer layer 12 can be formed by sputtering, vacuum deposition, or the like.
- a nitriding treatment for example, a step of raising the temperature to 1040 ° C. or higher in an ammonia atmosphere is performed.
- the surface of the metal buffer layer (metal layer: Sc layer) 12 is nitrided to become a scandium nitride layer (metal nitride layer: ScN layer) 12s.
- the thickness of the ScN layer 12s can be set by adjusting the processing time, temperature, and the like.
- an n-type nitride semiconductor layer (n-type semiconductor layer: n-type layer) 13 and a p-type nitride semiconductor layer (p-type semiconductor layer: p-type layer) are formed on the Sc metal buffer layer 12 having the ScN layer 12s. 14 are sequentially formed (epitaxial growth step). This film formation is performed, for example, by metal organic chemical vapor deposition (MOCVD), and the n-type layer 13 is doped with an impurity serving as a donor, and the p-type layer 14 is doped with an impurity serving as an acceptor.
- MOCVD metal organic chemical vapor deposition
- a stacked body 15 including an n-type layer 13 and a p-type layer 14 is formed, and a pn junction of a nitride semiconductor is formed therein, which becomes a light emitting layer 16.
- the n-type layer 13 and the p-type layer 14 with few crystal defects can be grown. Therefore, the quality of the nitride semiconductor in the stacked body 15 can be improved, and the emission intensity can be increased.
- the element region forming step (step S12) at least a part of the compound semiconductor layer (laminated body) 15 is removed by etching to simultaneously form the element region 15a, the core 21a, and the separation groove 20 (FIG. 2B). ).
- the core portion 21a for joining the growth substrate 11 and the support substrate is formed around the element region.
- the core portion 21 a is formed from the compound semiconductor layer (laminated body) 15.
- the separation groove 20 has a depth that reaches the surface of the growth substrate 11 from the upper side (p-type layer 14 side) in FIG. Thereby, the stacked body 15 is divided on the substrate 11.
- FIG. 2B a cross section in one direction is shown, but the separation groove 20 is also formed in a different direction, and a plurality of element regions 15a surrounded by the separation groove 20 are formed.
- the separation groove 20 is formed as follows, for example.
- a SiO 2 film is formed on the compound semiconductor layer (laminated body) 15 by CVD, patterned using a resist, and etched with BHF to form a SiO 2 mask. Thereafter, dry etching of the compound semiconductor layer is performed using SiO 2 as a mask until the sapphire substrate is exposed. Thereafter, the SiO 2 mask is removed using BHF.
- the protective film 22 is formed so as to cover the core 21a and the metal buffer layer, and the columnar material 21 is formed. This is to prevent the core 21a from being lifted off in the lift-off process.
- the protective film 22 is formed, for example, by depositing SiO 2 (1 ⁇ m) or the like (FIG. 2C). In FIG. 2C, the protective film 22 is also coated on the upper portion of the core portion 21a. However, a protective layer that is not removed in the lift-off process may be formed only on the side surface of the core portion.
- the protective layer is a material that does not dissolve or peel off in the lift-off process
- a material such as metal or resin may be used, and a sacrificial layer or a bonding layer is formed so as to cover the core and the metal buffer layer.
- the sacrificial layer and the bonding layer may also serve as a protective layer.
- step S14 for example, Cr (250 mm) is formed as the sacrificial layer 23 on the columnar object 21, and Pt / Au (2000 mm / 1 ⁇ m) is formed as the bonding layer 24 (FIG. 2D). ).
- a material capable of being in ohmic contact with the p-type layer 14 is formed as the p-side electrode 25 on the entire surface of the p-type layer 14 existing on the uppermost surface.
- Ni / Au 50/200 is formed and annealed.
- step S16 for example, Pt / Au (2000 mm / 2 ⁇ m) is formed as the bonding layer 26 (FIG. 2D).
- the conductive bonding layer 31 is formed on one main surface of the support substrate 30 prepared separately from the above structure (FIG. 2 (e)).
- any substrate having sufficient mechanical strength and high thermal conductivity can be used, and its electrical conductivity is also arbitrary.
- a single crystal silicon (Si) substrate which is a kind of semiconductor substrate can be used.
- the conductive bonding layer 31 is formed of a conductive material that can be bonded to the bonding layer 24 and the bonding layer 26 by thermocompression bonding.
- Ti / Pt / Au / Sn / Au 100 mm / 2000 mm / 1000 mm / as the bonding layer). (2000 mm / 1 ⁇ m) is formed.
- step S18 the compound semiconductor layer 15, the columnar object 21, and the support substrate 30 are joined (FIG. 2 (f)).
- the structure of FIG. 2 (d) and the structure of FIG. 2 (e) are heated so that the conductive bonding layer 31 and the bonding layers 24 and 26 are in direct contact with each other.
- Pressure bonding For example, the bonding condition is that a load of 12 kN is applied and thermocompression bonding is performed in a vacuum atmosphere at 300 ° C. for 60 minutes.
- the stacked body 15 a and the columnar object 21 are bonded to the support substrate 30 through the p-side electrode 25 and the bonding layer 26, the sacrificial layer 23 and the bonding layer 24, and the conductive bonding layer 31.
- step S19 the lift-off layer (metal buffer layer) 12 is removed and the growth substrate 11 is peeled off.
- This peeling process includes a lift-off process (step S191) and a sacrificial layer etching process (step S192).
- step S191 the joining of the columnar objects 21 is maintained (FIG. 2 (g)).
- the lift-off layer (metal buffer layer) 12 is dissolved by, for example, immersing the bonded substrate 40 in hydrochloric acid and performing chemical etching (FIG. 2G).
- the sacrificial layer etching step (step S192) for example, the sacrificial layer 23 is dissolved by performing chemical etching using a Cr selective etching solution (cerium ammonium nitrate), and the sapphire substrate 11 is peeled off.
- step S191 of the peeling process since the joining of the columnar objects 21 is maintained, the stress applied to the compound semiconductor layer 15a is relaxed and cracks are not generated, so that the compound semiconductor layer is separated from the sapphire substrate 11. (Element region) 15a can be peeled off.
- a high-quality LED semiconductor element having no cracks can be finally manufactured through an n-side electrode forming step (step S20) and a wire bonding step.
- FIG. 3 is a flowchart showing a process of manufacturing a semiconductor device by the method of manufacturing a semiconductor device according to the second embodiment of the present invention.
- FIG. 4 is a cross-sectional view of the substrate in each step of the method for manufacturing a semiconductor device according to the second embodiment of the present invention.
- the columnar material is formed by not providing a lift-off layer on the growth substrate.
- a columnar thing is formed with a metal or resin.
- the columnar body is formed of a metal or a resin that is not chemically etched in the lift-off process.
- the semiconductor device manufacturing method includes a compound semiconductor layer forming step (step S31), an element region forming step (step S32), a columnar material forming step (step S33), and a sacrificial layer forming step (step).
- step S34 includes p-side electrode forming step (step S35), bonding layer forming step (step S36), support substrate pre-bonding step (step S37), bonding step (step S38), and peeling step (step S39).
- the peeling step (step S39) is performed from the lift-off step (step S391) and the sacrificial layer etching step (step S392).
- step S391 of the peeling process step S39
- the columnar objects are joined. It is equity. That is, in the lift-off process (step S391), the bottom surface of the semiconductor layer and the growth substrate are separated by removing the lift-off layer, and the columnar object and the growth substrate are not separated.
- step S31 a lift-off layer (metal buffer layer) and a compound semiconductor layer on the lift-off layer are formed on the growth substrate (FIG. 4A). Since this process is the same as step S11 in the first embodiment, a description thereof will be omitted.
- step S32 At least a part of the compound semiconductor layer (laminated body) 15 is removed by etching to form the element region and the isolation groove 50 (FIG. 4B). Since this step is the same as step S12 of the first embodiment except that no core is formed around the element region, description thereof will be omitted.
- a columnar object 51 having substantially the same height as the element region is formed around a part of the element region of the separation groove region 50.
- a seed layer 52 is formed in a part of the region of the separation groove, and a support 53 is formed by Ni plating or the like.
- a columnar object 51 is formed by the seed layer 52 and the column 53 (FIG. 4C).
- pillar 53 can also be formed using the resist which is not etched by the metal etching liquid used at a next process instead of Ni plating.
- step S34 Cr / Pt / Au (250 mm / 2000 mm / 1 ⁇ m) is formed as the sacrificial layer 23 and the bonding layer 24 on the columnar body 51 (FIG. 4D). This process is the same as step S14 of the first embodiment.
- the p-side electrode forming step (step S35) is the same step as step S15 of the first embodiment, and the p-type layer 14 is formed on the entire surface of the p-type layer 14 existing on the uppermost surface with the p-type layer 14 and ohmic.
- a material capable of having sexual contact is formed. For example, Ni / Au (50/200) is formed and annealed.
- step S36 Pt / Au (2000 mm / 2 ⁇ m) is formed as the bonding layer 26 as in step S16 of the first embodiment (FIG. 4E).
- the conductive bonding layer 31 is formed on one main surface of the support substrate 30 prepared separately from the above structure. Note that, after this step, operations similar to those in steps S17 to S21 in the first embodiment are performed, and thus a cross-sectional view and a specific description are omitted.
- step S38 the compound semiconductor layer 15, the columnar object 51, and the support substrate 30 are joined.
- step S39 the lift-off layer (metal buffer layer) 12 is removed and the growth substrate 11 is peeled off.
- This peeling process includes a lift-off process (step S391) and a sacrificial layer etching process (step S392). In the lift-off process (step S391), the joining of the columnar objects 51 is maintained.
- step S391 the lift-off layer (metal buffer layer) 12 is dissolved by immersing the bonded substrate 40 in hydrochloric acid and performing chemical etching.
- step S392 the sacrificial layer etching step (step S392), for example, the sacrificial layer 23 is dissolved by performing chemical etching using a Cr selective etching solution (cerium ammonium nitrate), and the sapphire substrate 11 is peeled off.
- a Cr selective etching solution cerium ammonium nitrate
- step S391 of the peeling process since the joining of the columnar objects 51 is maintained, the stress applied to the compound semiconductor layer 15a is relaxed and cracks are not generated, so that the compound semiconductor layer is separated from the sapphire substrate 11. (Element region) 15a can be peeled off.
- FIG. 5 is a flowchart showing a process of manufacturing a semiconductor device by the method of manufacturing a semiconductor device according to the third embodiment of the present invention.
- FIG. 6 is a cross-sectional view of the substrate in each step of the method for manufacturing a semiconductor device according to the third embodiment of the present invention.
- a step of forming the metal buffer layer and a step of removing the metal buffer layer in the region where the columnar object (core part) is provided are provided, and then the compound semiconductor layer is formed. It has the process.
- the semiconductor device manufacturing method includes a compound semiconductor layer forming step (Step S51), an element region forming step (Step S52), a sacrificial layer forming step (Step S53), and a p-side electrode forming step (Step S51).
- Step S54 bonding layer forming step (Step S55), supporting substrate bonding step (Step S56), bonding step (Step S57), peeling step (Step S58), n-side electrode forming step (Step S59) ) And a wire bonding process (step S60), and the peeling process (step S58) includes a lift-off process (step S581) and a sacrificial layer etching process (step S582), and lift-off of the peeling process (step S58). In the process (step S581), the joining of the columnar objects is maintained.
- step S191 the bottom surface of the semiconductor layer and the growth substrate are separated by removing the lift-off layer, and the columnar object and the growth substrate are not separated.
- step S51 the metal buffer layer forming step (step S511), the step of removing the metal buffer layer in the region where the columnar body (core part) is formed (step S512), the compound semiconductor layer It has a deposition process (step S513).
- a selectively formed metal buffer layer is used.
- a step of forming a metal buffer layer (step S511) is performed.
- a lift-off layer (metal buffer layer) is formed on the growth substrate.
- the metal buffer layer 12 is formed on the growth substrate 11.
- a sapphire single crystal ((0001) substrate) is particularly preferably used.
- scandium (Sc) having a thickness of about 100 mm can be used.
- the metal buffer layer 12 can be formed by sputtering, vacuum deposition, or the like.
- step S512 of removing the metal buffer layer in the region for forming the next columnar body (core part) is executed.
- a region 12b where the metal buffer layer is deposited on the growth substrate 11 and a region 60 where the metal buffer layer is not deposited are provided.
- a lift-off method or an etching method using a resist or the like as a mask can be used.
- a nitriding treatment for example, a step of raising the temperature to 1040 ° C. or higher in an ammonia atmosphere is performed.
- the surface of the metal buffer layer (metal layer: Sc layer) 12 is nitrided to become a scandium nitride layer (metal nitride layer: ScN layer) 12s.
- the thickness of the ScN layer 12s can be set by adjusting the processing time, temperature, and the like.
- an n-type nitride semiconductor layer (n-type semiconductor layer: n-type layer) is formed on the region 12b where the Sc metal buffer layer 12 having the ScN layer 12s is deposited and the region 60 where it is not deposited. 13)
- a p-type nitride semiconductor layer (p-type semiconductor layer: p-type layer) 14 is sequentially formed (epitaxial growth step). This film formation is performed, for example, by metal organic chemical vapor deposition (MOCVD), and the n-type layer 13 is doped with an impurity serving as a donor, and the p-type layer 14 is doped with an impurity serving as an acceptor.
- MOCVD metal organic chemical vapor deposition
- a stacked body 15 including an n-type layer 13 and a p-type layer 14 is formed, and a pn junction of a nitride semiconductor is formed therein, which becomes a light emitting layer 16.
- the n-type layer 13 and the p-type layer 14 with few crystal defects can be grown. Therefore, the quality of the nitride semiconductor in the stacked body 15 can be improved, and the emission intensity can be increased.
- step S52 At least a part of the compound semiconductor layer (laminated body) 15 is removed by etching to form an element region and a separation groove 61 (FIG. 6B).
- the element region is formed, it is formed leaving the columnar body (core part) 62 for joining the growth substrate 11 and the support substrate.
- This columnar body (core part) 62 is formed from a compound semiconductor layer (laminated body) deposited in a region 60 where no metal buffer layer is deposited.
- the separation groove 61 is formed as follows. A SiO 2 film is formed on the compound semiconductor layer 15 by CVD, patterned using a resist, and etched with BHF to form a SiO 2 mask. Thereafter, dry etching of the compound semiconductor layer is performed using SiO 2 as a mask until the sapphire substrate is exposed. Thereafter, the SiO 2 mask is removed using BHF.
- step S53 Cr / Pt / Au (250 ⁇ / 2000 ⁇ / 1 ⁇ m) is formed as the sacrificial layer 23 and the bonding layer 24 on the columnar body (core portion) 62 (FIG. 6D). ). This process is the same as step S14 of the first embodiment.
- the p-side electrode forming step (step S54) is the same step as step S15 of the first embodiment, and the p-type layer 14 is formed on the entire surface of the p-type layer 14 existing on the uppermost surface as the p-side electrode 25.
- a material capable of having sexual contact is formed. For example, Ni / Au (50/200) is formed and annealed.
- step S55 Pt / Au (2000 mm / 2 ⁇ m) is formed as the bonding layer 26 as in step S16 of the first embodiment (FIG. 6E).
- the conductive bonding layer 31 is formed on one main surface of the support substrate 30 prepared separately from the above structure. Note that, after this step, operations similar to those in steps S17 to S21 in the first embodiment are performed, and thus a cross-sectional view and a specific description are omitted.
- step S57 the compound semiconductor layer 15, the columnar object 62, and the support substrate 30 are joined.
- step S58 the lift-off layer (metal buffer layer) 12 is removed and the growth substrate 11 is peeled off.
- This peeling process includes a lift-off process (step S581) and a sacrificial layer etching process (step S582).
- step S581 the joining of the columnar object (core part) 62 is maintained.
- the metal buffer layer 12 is dissolved by immersing the bonded substrate 40 in hydrochloric acid and performing chemical etching.
- the sacrificial layer etching step for example, the sacrificial layer 23 is dissolved by performing chemical etching using a Cr selective etching solution (cerium ammonium nitrate), and the sapphire substrate 11 is peeled off.
- step S581 of the peeling process since the bonding of the columnar body (core part) 62 is maintained, the stress applied to the compound semiconductor layer 15a is relieved and cracks are not generated, so that the sapphire substrate 11 The compound semiconductor layer (element region) 15a can be peeled off.
- FIG. 7 is a process cross-sectional view showing the manufacturing process in this case.
- FIGS. 7A to 7E correspond to FIGS. 6A to 6E, and only the positional relationship between the pattern of the Sc layer 12b and the columnar object 62 is different.
- step S512 instead of the step (step S512) of removing the metal buffer layer in the region where the columnar body (core portion) is to be formed in FIG.
- step Sc layer 12 The step of leaving the metal buffer layer (Sc layer 12) and removing the metal buffer layer in regions other than these is performed.
- the columnar object 62 is formed by etching.
- the Sc layer 12 (12 b) is not formed at the place where the columnar object 62 is formed, but here, the Sc layer 12 (12 b) is formed inside the columnar object 62. ) Is formed.
- the Sc layer 12 inside the columnar body 62 is set not to be exposed from the n-type layer 13. Setting the columnar body 62 and the Sc layer 12 in this way can be performed in the same manner as in FIG.
- the Sc layer 12 inside the columnar body 62 is not exposed from the n-type layer 13, the Sc layer 12 in the columnar body 62 is not etched even in the lift-off process, and the columnar body 62 and the growth substrate 11 are not etched. The connection between is maintained. For this reason, subsequent processes can be performed similarly to the manufacturing method of FIG. In this case, compared with the manufacturing method of FIG. 6, in the state of FIG. 7C, the height in the element region and the height of the columnar portion 62 are equal. For this reason, these height adjustments which are important in the joining process are particularly easy. Further, the Sc layer 12 inside the columnar object 62 can also be used as an alignment mark during lithography or bonding.
- FIG. 8 is a flowchart showing a process of manufacturing a semiconductor device by the method of manufacturing a semiconductor device according to the fourth embodiment of the present invention.
- FIG. 9 is a cross-sectional view of the substrate in each step of the method of manufacturing a semiconductor device according to the fourth embodiment of the present invention.
- a sacrificial layer is formed on a support substrate, and a columnar object is formed on the basis of the sacrificial layer. And preferably a columnar thing is formed with a metal. Further, preferably, the columnar body is formed of a metal that is not chemically etched.
- the method for manufacturing a semiconductor device includes a compound semiconductor layer forming step (step S71), an element region forming step (step S72), a p-side electrode forming step (step S73), and a bonding layer forming step ( Step S74), pre-support substrate bonding step (Step S75), bonding step (Step S76), peeling step (Step S77), n-side electrode forming step (Step S78), and wire bonding step (Step S79) And have.
- the supporting substrate bonding step (step S75) includes a sacrificial layer forming step (step S751), a columnar object forming step (step S752), and a bonding layer forming step (step S753).
- the peeling process (step S77) includes a lift-off process (step S771) and a sacrificial layer etching process (step S772).
- step S771 of the peeling process (step S77) the joining of the columnar objects is maintained. Is done. That is, in the lift-off process (step S771), the bottom surface of the semiconductor layer and the growth substrate are separated by removing the lift-off layer, and the columnar object and the growth substrate are not separated.
- step S71 a lift-off layer (metal buffer layer) and a compound semiconductor layer on the lift-off layer are formed on the growth substrate 11. Since this process is the same as step S11 in the first embodiment, a description thereof will be omitted.
- step S72 At least a part of the compound semiconductor layer (laminated body) 15 is removed by etching to form the element region and the separation groove 50. Since this step is the same as step S12 of the first embodiment except that no core is formed around the element region, description thereof will be omitted.
- the p-side electrode forming step (step S73) is the same step as step S15 of the first embodiment, and the p-type layer 14 is formed on the entire surface of the p-type layer 14 existing on the uppermost surface as the p-side electrode 25.
- a material capable of having sexual contact is formed. For example, Ni / Au (50/200) is formed and annealed.
- step S74 Pt / Au (2000 mm / 2 ⁇ m) is formed as the bonding layer 80 as in step S16 of the first embodiment (FIG. 9B).
- a sacrificial layer forming step (step S751) is executed.
- Cr 250 ⁇
- FIG. 9A the support substrate 30 is shown downward.
- a columnar object 82 having substantially the same height as the element region formed on the growth substrate 11 is formed on the basis of the sacrificial layer 81 formed on the support substrate 30.
- a seed layer 82a is formed on the basis of the sacrificial layer 81, and a support 82b is formed by Ni plating or the like.
- a columnar object 82 is formed by the seed layer 82a and the column 82b (FIG. 9A).
- pillar 82b can also be formed using the resist which is not etched by the etching liquid used at a next process instead of Ni plating.
- step S753 Pt / Au (2000 mm / 2 ⁇ m) is formed as the bonding layer 83 on the support substrate 30 and the columnar object 82 (FIG. 9A).
- step S76 the compound semiconductor layer 15 and the support substrate 30 are joined by joining the joining layer 80 shown in FIG. 9B and the joining layer 83 shown in FIG. 82 and the growth substrate 11 are joined (FIG. 9C).
- step S77 the lift-off layer (metal buffer layer) 12 is removed and the growth substrate 11 is peeled off.
- This peeling process includes a lift-off process (step S771) and a sacrificial layer etching process (step S772).
- step S771 the joining of the columnar objects 82 is maintained (FIG. 9 (d)).
- the metal buffer layer 12 is dissolved by immersing the bonded substrate 40 in hydrochloric acid and performing chemical etching.
- the sacrificial layer etching step for example, the sacrificial layer 81 is dissolved by performing chemical etching using a Cr selective etching solution (cerium ammonium nitrate), and the sapphire substrate 11 is peeled off.
- step S771 of the peeling process since the joining of the columnar objects 82 is maintained, the stress applied to the compound semiconductor layer (element region) 15a is relaxed so that cracks do not occur, and the sapphire substrate 11 The compound semiconductor layer (element region) 15a can be peeled off.
- sapphire is used as the growth substrate 11.
- a group III nitride such as high-quality GaN or AlGaN is provided via the buffer layer 12 or the like.
- Other materials such as an AlN template or SiC can be used as long as they can grow semiconductors (n-type layer 13 and p-type layer 14).
- the support substrate 30 any material other than silicon can be used.
- the support substrate 30 serves as a mechanical support substrate for the manufactured LED and at the same time serves as a heat dissipation substrate, it preferably has high mechanical strength and high thermal conductivity.
- the material of the support substrate 30 can be selected from a wide range of materials, and various insulating substrates, metal substrates, and semiconductor substrates can be used. A metal ceramic bonded substrate in which metal wiring is previously formed on an insulating ceramic substrate having high mechanical strength and thermal conductivity can also be used.
- the stacked body is composed of the n-type layer 13 and the p-type layer 14 both made of a nitride semiconductor.
- an LED or LD laser diode
- the n-type layer 13 is formed on the growth substrate 11, the active layer is formed thereon, and then the p-type layer 14 is formed.
- the columnar object in the above embodiment temporarily plays the role of a column between the floor and the ceiling, and is limited to a substantially cylindrical or polygonal column.
- various forms are possible for the shape, size, and arrangement relationship.
- the one that completely blocks the path through which the chemical etching solution can reach the lift-off layer such as a wall that surrounds four sides, is used. Should not. In order to disperse the stress evenly with respect to the shape of the part to be lifted off, it is a preferable form that the arrangement is regular.
- the columnar object in the above embodiment needs to be peeled off after lift-off.
- it is preferable to provide a sacrificial layer on a part of the columnar material but it is also preferable that the columnar material itself has the function of the sacrificial layer.
- the separation part of the columnar object is on the support substrate side in order to avoid an adverse effect when the elements are individually separated, but the separation part is on the growth substrate side.
- the location is arbitrary. For the purpose of reusing the substrate, both sides of the pillar may be peeled off.
- the sacrificial layer in the above embodiment is not peeled off when the lift-off layer is lifted off, but may be any layer that can be separated without adversely affecting the element and the bonding layer in the subsequent sacrificial layer etching step.
- different selective etching solutions may be used for the metal buffer layer and the sacrificial layer, which are lift-off layers.
- the metal buffer layer for example, Sc, Cr, Zr, Hf, etc. (and their nitrides) can be selected.
- the sacrificial layer is made of a material other than that selected in the metal buffer layer, and for example, a metal such as Cr, Ni, Ti, a resin, an adhesive, or the like can be selected.
- the method for separating the sacrificial layer is not limited to etching, and heat, light, a mechanical method, or the like may be used.
- the bonding layer may be made of a material other than those selected above.
- a noble metal such as Pt or Au can be used. There are various combinations of these depending on the type of the lift-off layer, the type of the selective etching solution, and the separation method.
- the first to fourth embodiments it is relatively preferable to have a core portion made of the same material as the semiconductor layer, like the first and third columnar objects.
- the second and fourth which use a columnar material made of a material different from that of the semiconductor layer, the quality control becomes easier with respect to the accuracy of matching the height with the semiconductor layer, which is necessary when joining the support substrate. is there.
- Example 1-1 Actually, the compound semiconductor layer was formed in the step exemplified in the first embodiment, and the sapphire substrate was peeled off. On the sapphire single crystal substrate (0001) surface, scandium (Sc) having a thickness of 100 mm was formed as a metal buffer layer by a sputtering method. Next, nitriding treatment was performed at 1200 ° C. for 10 minutes in an ammonia atmosphere, the metal buffer layer was nitrided, and a scandium nitride layer (ScN layer) was formed.
- Sc scandium nitride layer
- Non-doped AlGaN, Si-doped n-type AlGaN layer (1.5 ⁇ m), MQW active layer (0.1 ⁇ m), and Mg-doped p-type AlGaN layer (0.3 ⁇ m) are sequentially formed on the ScN layer by MOCVD.
- a film was formed.
- a SiO 2 film is formed on the p-type AlGaN layer by CVD, patterned using a resist, etched with BHF to form a SiO 2 mask, a compound semiconductor layer is dry etched, and the sapphire substrate is exposed.
- SiO 2 (1 ⁇ m) was formed by CVD so as to cover the entire core.
- Cr 250 mm
- Pt / Au 2000 mm / 1 ⁇ m
- Ni / Au 50/200 mm
- Pt / Au 2000 mm / 2 ⁇ m
- a p-type single crystal silicon (Si) substrate was used as the support substrate 30, and Ti / Pt / Au / Sn / Au (100 ⁇ / 2000 ⁇ / 1000 ⁇ / 2000 ⁇ / 1 ⁇ m) was formed as a bonding layer on the support substrate side.
- the bonding layer on the element region and the columnar object side and the bonding layer on the support substrate side were thermocompression bonded in a vacuum atmosphere at 300 ° C. for 60 minutes by applying a load of 12 kN.
- the bonded substrates were immersed in hydrochloric acid for 24 hours to dissolve Sc and ScN and perform chemical lift-off. Thereafter, the sacrificial layer was dissolved using a Cr selective etching solution (cerium ammonium nitrate), and the sapphire substrate was peeled off.
- a Cr selective etching solution cerium ammonium nitrate
- the quality of the compound semiconductor layer after sapphire substrate peeling was compared with the conventional manufacturing method by surface observation with an optical microscope.
- FIG. 10A is a view showing a support substrate and a compound semiconductor layer in which a core portion is not formed and a sapphire substrate is peeled off without providing a columnar object
- FIG. 10B is a columnar shape of Example 1. It is a figure which shows the support substrate and compound semiconductor layer which provided the thing, peeled the sapphire substrate, and isolate
- a columnar columnar column having a diameter of about 90 ⁇ m was arranged at the position of the apex of a square having a side of 850 ⁇ m so as to surround a circular semiconductor layer having a diameter of 850 ⁇ m, which is equal to the semiconductor layer of each element.
- Cross sections for one element viewed from the diagonal side of the quadrangle are illustrated in the cross-sectional views of the first to fourth embodiments.
- Reference numeral 70 in FIG. 10 indicates a support substrate
- reference numeral 71 indicates a compound semiconductor layer according to a conventional method
- reference numeral 72 indicates a compound semiconductor layer according to the present invention.
- symbol 73 of FIG.10 (b) shows the trace (surface by the side of the sacrificial layer 23 of the joining layer 24) which peeled the columnar thing.
- FIG. 10 (a) and an electron micrograph (FIG. 10 (c)) in the conventional manufacturing method, it is confirmed that a crack occurs in the central portion of the compound semiconductor layer after the sapphire substrate is peeled off. SEM was observed. In the minute region that is etched from the outer periphery of the compound semiconductor layer and remains in the center immediately before the sapphire substrate is peeled off, stress concentration occurs between the substrate, the compound semiconductor layer, and the support substrate. It is thought that cracks were observed. However, as can be seen from FIG.
- the compound semiconductor layer is not cracked in the manufacturing method of the present invention.
- no cracks such as those shown in FIG. Therefore, it was confirmed that no cracks were generated when the sapphire substrate was peeled off in the examples, and it was found that cracks at locations where stress is concentrated can be suppressed by the progress of etching of the compound semiconductor layer that is lifted off by etching the lift-off layer from the periphery. .
- Example 1-2 In the process illustrated in the first embodiment, when the sacrificial layer and the bonding layer also serve as a protective layer, the protective layer forming process is omitted, and Cr (250 mm) is formed as the sacrificial layer so as to cover the entire core portion.
- the same procedure as in Example 1 was performed except that Pt / Au (2000 ⁇ / 1 ⁇ m) was formed as the layer and the bonding layer in the element region was Pt / Au (2000 ⁇ / 1 um).
- the same results as in FIG. 10B were obtained, and no cracks occurred in the compound semiconductor layer.
- Example 2 As in the process exemplified in the second embodiment, the core is not formed, the seed layer is Pt / Au / Pt / Pd (500 mm / 7500 mm / 500 mm / 500 mm), and the columnar material is Ni-plated with a thickness of 3 ⁇ m. This was performed in the same manner as in Example 1 except that the columnar material and the element region bonding layer were made of Pt / Au (2000 mm / 1 ⁇ m). The same results as in FIG. 10B were obtained, and no cracks occurred in the compound semiconductor layer.
- Example 3 As in the process illustrated in the third embodiment, the metal buffer layer serving as the position of the core is removed by etching after forming a resist mask, and the bonding layer between the pillar and the element region is formed by Pt without forming a protective film. This was performed in the same manner as in Example 1 except that / Au (2000 mm / 1 ⁇ m) was used. The same results as in FIG. 10B were obtained, and no cracks occurred in the compound semiconductor layer.
- Example 4 Moreover, it carried out similarly to Example 2 except having formed the columnar object through the peeling layer on the support substrate side like the process illustrated in Embodiment 4th. The trace which peeled off the columnar thing like the code
- Example 1 the non-doped AlGaN layer of the separated compound semiconductor layer was removed by dry etching, Ti / Al was formed on the exposed n-type AlGaN layer, and IV Measurements were made.
- Vr reverse voltage
- the voltage of Example 1 was 10 V or higher, while that of Comparative Example 1 was as low as about 6 V. It is thought that the leakage current increased due to the occurrence of cracks. Therefore, it was found that an element with little leakage current can be obtained by the present invention.
- the semiconductor element and the method for manufacturing the semiconductor element according to the present invention are used for a semiconductor element such as an LED optical system element and a method for manufacturing the semiconductor element.
- Growth substrate 12 Lift-off layer (metal buffer layer) (metal layer: Sc layer) 13 n-type nitride semiconductor layer (n-type semiconductor layer: n-type layer) 14 p-type nitride semiconductor layer (p-type semiconductor layer: p-type layer) 15 Compound semiconductor layer (laminated body) 15a element region 16 light emitting layer 20 separation groove 21 columnar object 22 protective film 23 sacrificial layer 24 bonding layer 25 p-type electrode 26 bonding layer 30 support substrate 31 conductive bonding layer
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Abstract
Description
第2の半導体素子の製造方法は、上記の方法において、好ましくは、柱状物形成工程は、柱状物の一部に犠牲層を形成する犠牲層形成工程を備え、柱状物と支持基板とを分離する工程では、犠牲層を除去することを特徴とする。
第3の半導体素子の製造方法は、上記の方法において、好ましくは、柱状物は、半導体層と同じ材料から構成された核部を具備することを特徴とする。
第4の半導体素子の製造方法は、上記の方法において、好ましくは、素子領域形成工程において、半導体層を構成する材料をリフトオフ層を介して成長基板上に形成した後に、エッチングを施すことにより、素子領域と核部を形成し、柱状物形成工程において、リフトオフ工程において除去されない保護層を核部側面に形成することを特徴とする。
第5の半導体素子の製造方法は、上記の方法において、好ましくは、成長基板上にリフトオフ層を形成する工程において、柱状物を形成すべき領域におけるリフトオフ層を除去する工程を有し、半導体層を構成する材料をリフトオフ層を介して成長基板上に形成すると共に部分的にリフトオフ層を介さずに形成した後に、エッチングを施し、素子領域とリフトオフ工程においてリフトオフされない核部とを同時に形成することを特徴とする。
第6の半導体素子の製造方法は、上記の方法において、好ましくは、成長基板上にリフトオフ層を形成する工程において、素子領域と、柱状物を形成すべき領域の内部となる領域においてリフトオフ層を選択的に形成する工程を有し、半導体層を構成する材料をリフトオフ層を介して成長基板上に形成すると共に部分的にリフトオフ層を介さずに形成した後に、エッチングを施し、素子領域とリフトオフ工程においてリフトオフされない核部とを同時に形成することを特徴とする。
第7の半導体素子の製造方法は、支持基板上に半導体層が接合された構成を具備する半導体素子の製造方法であって、成長基板上にリフトオフ層を介して、半導体層からなる素子領域を形成する素子領域形成工程と、支持基板上に、柱状物を形成する柱状物形成工程と、支持基板に半導体層を接合し、成長基板に柱状物を接合する接合工程と、リフトオフ層を除去することにより半導体層の下面と成長基板とを分離し、かつ柱状物と成長基板とを分離しないリフトオフ工程と、柱状物と支持基板とを分離する工程と、を具備することを特徴とする。
第8の半導体素子の製造方法は、上記の方法において、好ましくは、柱状物形成工程は、支持基板上に犠牲層を形成する犠牲層形成工程を備え、柱状物と支持基板とを分離する工程では、犠牲層を除去することを特徴とする。
第9の半導体素子の製造方法は、上記の方法において、好ましくは、半導体層は、成長基板側にn型層、当該n型層上に形成されたp型層を具備することを特徴とする。
第10の半導体素子の製造方法は、上記の方法において、好ましくは接合工程前において、素子領域における半導体層の表面、及び支持基板の表面に、それぞれ導電性材料を形成することを特徴とする。
第11の半導体素子の製造方法は、上記の方法において、好ましくはn型層に接合するn型電極を形成し、p型層に接合するp型電極を形成し、n型電極とp型電極との間に10ボルトの逆方向電圧を印加したときのリーク電流が10μA以下であることを特徴とする。
第1の半導体素子は、上記第1~第10の半導体素子の製造方法によって製造されたことを特徴とする。
上記実施形態における犠牲層は、リフトオフ層をリフトオフする際に剥離されないが、その後の犠牲層エッチング工程で素子や接合層に悪影響を与えずに分離が可能な層であればよい。ケミカルリフトオフの場合、リフトオフ層である金属バッファ層と犠牲層に異なる選択エッチング液があればよい。金属バッファ層は、例えばSc、Cr、Zr、Hfなど(およびそれらの窒化物)を選択できる。犠牲層は、金属バッファ層で選択された以外の材料で、例えばCr、Ni、Tiなどの金属や樹脂、接着剤等を選択できる。なお、犠牲層を分離する方法は、エッチングに限らず、熱や光、機械的方法等を用いるものでも良い。接合層は、上記で選択された以外の材料でよく、例えばPt、Auなどの貴金属を使用できる。リフトオフ層の種類によって、および選択エッチング液の種類や分離方法によって、これらの組み合わせは多岐に亘る。
実際に、実施形態第1に例示した工程で化合物半導体層を形成し、サファイヤ基板剥離を行った。サファイア単結晶基板(0001)面上に金属バッファ層として100Åの膜厚のスカンジウム(Sc)をスパッタリング法により成膜した。
次に、アンモニア雰囲気で1200℃で10分間の窒化処理を行い、金属バッファ層は窒化され、窒化スカンジウム層(ScN層)が形成された。
次に、ScN層上に、ノンドープAlGaNを2um、Siドープn型AlGaN層(1.5μm)、MQW活性層(0.1μm)、Mgドープp型AlGaN層(0.3μm)を順次MOCVD法で成膜した。
p型AlGaN層上にCVDによりSiO2を成膜して、レジストを用いてパターニングを行い、BHFでエッチングすることでSiO2マスクを形成し、化合物半導体層のドライエッチングを行い、サファイア基板が露出するまで、エッチングを行った。その後、BHFを使用してSiO2マスクを除去し、直径850μmの円形の素子領域と、素子領域の周辺に、直径約90μmの核部を形成した。
核部全体を被覆するように保護膜としてSiO2(1μm)をCVDにより成膜した。核部の上部の保護膜上に犠牲層としてCr(250Å)を、接合層としてPt/Au(2000Å/1μm)を成膜した。
また、素子領域のp型層全面に、p側電極としてNi/Au(50Å/200Å)を成膜して550℃で15分のアニールを行った。その後、接合層として、Pt/Au(2000Å/2μm)を成膜した。
支持基板30としてp型単結晶シリコン(Si)基板を用い、支持基板側の接合層としてTi/Pt/Au/Sn/Au(100Å/2000Å/1000Å/2000Å/1μm)を成膜した。素子領域および柱状物側の接合層と、支持基板側の接合層とを、12kNの荷重を印加して、300℃で60分、真空雰囲気で熱圧着した。
接合した基板を塩酸に24時間浸漬してScおよびScNを溶解してケミカルリフトオフを行った。その後、Cr選択エッチング液(硝酸セリウムアンモニウム)を用いて犠牲層を溶解し、サファイア基板を剥離した。
サファイア基板剥離後の化合物半導体層の品質を、光学顕微鏡での表面観察により、従来の製造方法と比較した。
実施形態1に例示した工程において、犠牲層および接合層が保護層を兼ねる場合、保護層の形成工程を省き、核部全体を被覆するように犠牲層としてCr(250Å)を成膜し、接合層としてPt/Au(2000Å/1um)を成膜し、素子領域の接合層をPt/Au(2000Å/1um)とした以外は実施例1と同様に行った。図10(b)と同様の結果が得られ、化合物半導体層に割れは生じなかった。
実施形態第2に例示した工程のように、核部を形成せず、シード層としてPt/Au/Pt/Pd(500Å/7500Å/500Å/500Å)とし、柱状物を厚さ3μmのNiメッキにより形成し、柱状物と素子領域の接合層をPt/Au(2000Å/1μm)とした以外は、実施例1と同様に行った。図10(b)と同様の結果が得られ、化合物半導体層に割れは生じなかった。
実施形態第3に例示した工程のように、核部の位置となる金属バッファ層を、レジストマスクを形成しエッチングにより除去し、保護膜を形成せずに柱状物と素子領域の接合層をPt/Au(2000Å/1μm)とした以外は、実施例1と同様に行った。図10(b)と同様の結果が得られ、化合物半導体層に割れは生じなかった。
また、実施形態第4に例示する工程のように、支持基板側に剥離層を介して柱状物を形成した以外は実施例2と同様に行った。図10(b)の符号73のような柱状物を剥離した跡は見られず、化合物半導体層に割れは生じなかった。
12 リフトオフ層(金属バッファ層)(金属層:Sc層)
13 n型窒化物半導体層(n型半導体層:n型層)
14 p型窒化物半導体層(p型半導体層:p型層)
15 化合物半導体層(積層体)
15a 素子領域
16 発光層
20 分離溝
21 柱状物
22 保護膜
23 犠牲層
24 接合層
25 p型電極
26 接合層
30 支持基板
31 導電性接合層
Claims (12)
- 支持基板上に半導体層が接合された構成を具備する半導体素子の製造方法であって、
成長基板上にリフトオフ層を介して、前記半導体層からなる素子領域を形成する素子領域形成工程と、
前記成長基板上に、柱状物を形成する柱状物形成工程と、
支持基板に、前記半導体層及び前記柱状物の上部を接合する接合工程と、
前記リフトオフ層を除去することにより前記半導体層の下面と前記成長基板とを分離し、かつ前記柱状物と前記成長基板とを分離しないリフトオフ工程と、
前記柱状物と前記支持基板とを分離する工程と、
を具備することを特徴とする半導体素子の製造方法。 - 前記柱状物形成工程は、前記柱状物の一部に犠牲層を形成する犠牲層形成工程を備え、前記柱状物と前記支持基板とを分離する工程では、前記犠牲層を除去することを特徴とする請求項1記載の半導体素子の製造方法。
- 前記柱状物は、前記半導体層と同じ材料から構成された核部を具備することを特徴とする請求項1または2記載の半導体素子の製造方法。
- 前記素子領域形成工程において、前記半導体層を構成する材料を前記リフトオフ層を介して前記成長基板上に形成した後に、エッチングを施すことにより、前記素子領域と前記核部を形成し、
前記柱状物形成工程において、前記リフトオフ工程において除去されない保護層を前記核部側面に形成することを特徴とする請求項3記載の半導体素子の製造方法。 - 前記成長基板上に前記リフトオフ層を形成する工程において、前記柱状物を形成すべき領域における前記リフトオフ層を除去する工程を有し、前記半導体層を構成する材料を前記リフトオフ層を介して前記成長基板上に形成すると共に部分的にリフトオフ層を介さずに形成した後に、エッチングを施し、前記素子領域とリフトオフ工程においてリフトオフされない前記核部とを同時に形成することを特徴とする請求項3記載の半導体素子の製造方法。
- 前記成長基板上に前記リフトオフ層を形成する工程において、前記素子領域と、前記柱状物を形成すべき領域の内部となる領域において前記リフトオフ層を選択的に形成する工程を有し、前記半導体層を構成する材料を前記リフトオフ層を介して前記成長基板上に形成すると共に部分的にリフトオフ層を介さずに形成した後に、エッチングを施し、前記素子領域とリフトオフ工程においてリフトオフされない前記核部とを同時に形成することを特徴とする請求項3記載の半導体素子の製造方法。
- 支持基板上に半導体層が接合された構成を具備する半導体素子の製造方法であって、
成長基板上にリフトオフ層を介して、前記半導体層からなる素子領域を形成する素子領域形成工程と、
前記支持基板上に、柱状物を形成する柱状物形成工程と、
前記支持基板に前記半導体層を接合し、前記成長基板に前記柱状物を接合する接合工程と、
前記リフトオフ層を除去することにより前記半導体層の下面と前記成長基板とを分離し、かつ前記柱状物と前記成長基板とを分離しないリフトオフ工程と、
前記柱状物と前記支持基板とを分離する工程と、
を具備することを特徴とする半導体素子の製造方法。 - 前記柱状物形成工程は、前記支持基板上に犠牲層を形成する犠牲層形成工程を備え、前記柱状物と前記支持基板とを分離する工程では、前記犠牲層を除去することを特徴とする請求項7記載の半導体素子の製造方法。
- 前記半導体層は、前記成長基板側にn型層、当該n型層上に形成されたp型層を具備することを特徴とする請求項1~8のいずれか1項に記載の半導体素子の製造方法。
- 前記接合工程前において、
前記素子領域における前記半導体層の表面、及び前記支持基板の表面に、それぞれ導電性材料を形成することを特徴とする請求項1~9のいずれか1項に記載の半導体素子の製造方法。 - 前記n型層に接合するn型電極を形成し、前記p型層に接合するp型電極を形成し、前記n型電極と前記p型電極との間に10ボルトの逆方向電圧を印加したときのリーク電流が10μA以下であることを特徴とする請求項9記載の半導体素子の製造方法。
- 請求項1~請求項11のいずれか1項に記載の半導体素子の製造方法によって製造されたことを特徴とする半導体素子。
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