WO2012003659A1 - Procédé de fabrication d'un dispositif mos soi afin de réaliser un contact ohmique de la source et du corps - Google Patents

Procédé de fabrication d'un dispositif mos soi afin de réaliser un contact ohmique de la source et du corps Download PDF

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Publication number
WO2012003659A1
WO2012003659A1 PCT/CN2010/076683 CN2010076683W WO2012003659A1 WO 2012003659 A1 WO2012003659 A1 WO 2012003659A1 CN 2010076683 W CN2010076683 W CN 2010076683W WO 2012003659 A1 WO2012003659 A1 WO 2012003659A1
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WIPO (PCT)
Prior art keywords
region
type
source
doped
source region
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PCT/CN2010/076683
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English (en)
Chinese (zh)
Inventor
陈静
伍青青
罗杰馨
黄晓橹
王曦
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中国科学院上海微系统与信息技术研究所
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Priority to US13/131,126 priority Critical patent/US8354310B2/en
Publication of WO2012003659A1 publication Critical patent/WO2012003659A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78612—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/78654—Monocrystalline silicon transistors

Definitions

  • the present invention relates to a method of fabricating a MOS (Metal O Oxide Semi conduc tor ) structure, and more particularly to a method of fabricating an SOI MOS device for ohmic contact of a source by a silicide process, and belongs to the field of semiconductor manufacturing technology.
  • MOS Metal O Oxide Semi conduc tor
  • SOI Silicon-on-insulator technology
  • the device In the S0 I technology, the device is only fabricated in a thin silicon film. The device is separated from the substrate by a layer of buried oxide. This structure makes the SOI technology have advantages that are not comparable to bulk silicon. .
  • the small parasitic capacitance makes the S0I device high speed and low power consumption.
  • the all-media isolation of SOI CMOS devices completely eliminates the parasitic latch-up effect of bulk silicon CMOS devices.
  • S0I full-medium isolation makes S0I technology highly integrated and resistant to radiation.
  • S0I technology is widely used in radio frequency, high voltage, anti-irradiation and other fields. As device sizes continue to shrink, S0I technology is likely to replace bulk silicon as the first choice for S i technology.
  • the SOI M0S is divided into a partially depleted SO I MOS (PD SOI ) and a fully depleted SOI MOS ( FD SOI ) depending on whether the active body region is depleted.
  • PD SOI partially depleted SO I MOS
  • FD SOI fully depleted SOI MOS
  • the fully depleted SOI M0S threshold voltage is not easy to control. Therefore, it is still commonly used to partially deplete SO I M0S.
  • the active body region of the partially depleted SOI MOS is not completely depleted, so that the body region is in a floating state, and the charge generated by the impact ionization cannot be quickly removed, which results in a unique floating body effect of the SOI MOS.
  • the hole flows to the body region, and the SOI M0S floating body effect causes the holes to accumulate in the body region, thereby raising the body potential, making the SOI ⁇ OS
  • the threshold voltage is reduced and the leakage current is increased, resulting in a warpage of the output characteristic curve I d Vd of the device. This phenomenon is called the Kink effect.
  • the K ink effect has many adverse effects on device and circuit performance and reliability, and should be suppressed as much as possible during device design.
  • SOI PM0S due to the low ionization rate of holes, the electricity generated by impact ionization The sub-hole pair is much lower than the SOI MN, so the Kink effect in SOI PM0S is not obvious.
  • the body contact is usually connected to a fixed potential (source or ground) by means of a body contact, as shown in Figure la-lb, for a conventional T-gate structure contact,
  • the P + implant region formed at one end of the T-type gate is connected to the P-type body region under the gate.
  • the present invention proposes a novel fabrication process of the MOS structure, which is simple and easy to be compatible with the integrated circuit process.
  • the technical problem to be solved by the present invention is to provide a SOI MOS device manufacturing method for realizing ohmic contact of a source body, which effectively suppresses the S0I floating body effect by a silicide process.
  • a method for fabricating an SO I MOS device for achieving ohmic contact of a source body includes the following steps: Step 1: forming a shallow trench isolation structure on a Si material having an insulating buried layer, isolating an active region, and is in an active region Making a grid area;
  • Step 2 performing high-dose light doping of the source region and light doping of the drain region to form a high concentration lightly doped N-type source region and a lightly doped N-type drain region, the high-dose source region being lightly doped and
  • the light-doped implant dose of the drain region reaches the order of 1 e 15 /cm 2
  • the concentration of the high-concentration lightly doped N-type source region and the lightly doped N-type drain region reaches the order of le 9 /cm 3 ;
  • Step 3 preparing an insulating sidewall spacer structure around the gate region, and then performing ion implantation in the source region and the drain region to form an N-type S i material source region and an N-type drain region, and forming a body region therebetween;
  • Step 4 using a mask plate having an opening at a position of the source region of the N-type Si material, and performing a large-angle heavily doped P ion implantation in an oblique manner through the mask plate to control P ion implantation to Between the source region of the N-type Si material and the body region, thereby forming a heavily doped P-type region; performing vertical-doped heavily doped P ion implantation to be perpendicular to the surface of the source region of the N-type Si material Straight surface as the reference, the angle of inclination is More than 15 degrees less than or equal to 45 degrees;
  • Step 5 forming a layer of metal on the surface of the source region of the N-type Si material, and then reacting the metal with the underlying Si material to form a silicide by heat treatment until the generated silicide is in contact with the insulating buried layer.
  • the remaining S i material that does not react with the metal becomes an N-type Si region, and the formed silicide and N-type Si region constitute an N-type source region, and the heavily doped P-type region forms an ohmic contact with the generated silicide.
  • the insulating buried layer, the body region, the N-type Si region of the N-type source region and the silicide and finally completing the structure of the MOS device.
  • step 1 P ion implantation may be performed on the S i material before the gate region is formed.
  • the inclination angle is preferably 35 degrees.
  • the metal is selected from one of Co and Ti.
  • the heat treatment is preferably carried out by a furnace tube annealing process at a temperature of 700 to 900 ° C and a time of 60 to 90 seconds.
  • the method for fabricating an SOI MOS device for realizing ohmic contact of a source body has the beneficial effects of: using a tilt angle ion implantation method and a silicide process, under the N-type Si region of the source region, silicide and body region A heavily doped P-type region is formed to form an ohmic contact between the source region silicide and the heavily doped P region, releasing holes accumulated in the body region of the SOI MOS device, thereby suppressing the floating body effect of the SOI MOS device.
  • the invention effectively suppresses the floating body effect, and has the advantages of not increasing the chip area, and the manufacturing process is simple and compatible with the conventional CMOS process.
  • FIG. 1a is a schematic top view of a MOS structure in which a body contact method is used to suppress a floating body effect in the background art
  • FIG. 1b is a schematic cross-sectional view of a MOS structure in which a body contact method is used to suppress a floating body effect in the background art
  • FIGS. 2a-2e are diagrams using the method of the present invention. Schematic diagram of the process flow for fabricating the MOS device structure.
  • a MOS device structure for suppressing the SOI floating body effect includes: a substrate 10, an insulating buried layer 20 on the substrate 10, an active region on the insulating buried layer 20, and the Active A gate region over the region and a shallow trench isolation (STI) structure 30 located around the active region.
  • STI shallow trench isolation
  • the active region includes: a body region 70, an N-type source region, an N-type drain region 40, and a heavily doped P-type region 60;
  • the N-type source region is composed of a silicide 51 and an N-type Si region 52 connected thereto
  • the two-part source region and the N-type drain region 40 are respectively located at two ends of the body region 70;
  • the heavily doped P-type region 60 is located under the N-type Si region 52 of the N-type source region, and the silicide 51 and
  • the body regions 70 are surrounded by the silicide 51, the insulating buried layer 20, the body region 70, and the N-type Si region 52 without being in contact with the shallow trench isolation structure 30.
  • the gate region includes a gate dielectric layer 81 and a gate electrode 82 on the gate dielectric layer 81.
  • An insulating sidewall spacer 90 is disposed around the gate region.
  • the active area is mainly made of S i material.
  • the body region 70 may be a P-type Si material.
  • the N-type drain region 40 is made of an N-type S i material.
  • the insulating buried layer 20 may be made of silicon dioxide or silicon nitride. In a specific example of the present invention, silicon dioxide, that is, a buried oxide layer (BOX) may be used.
  • the silicide 51 can be any conductive silicide (eg, cobalt silicide, titanium silicide) that can form an ohmic contact with the heavily doped P-type region 60 adjacent thereto for releasing holes accumulated in the body region of the SOI 0S device. Thereby suppressing the floating body effect of the SOI MOS device.
  • the Kink effect due to the floating body effect is not obvious in the SOI PM0S, so the solution of the present invention is mainly directed to the SOI wake up OS device.
  • the above-mentioned method for fabricating the MOSFET device structure for suppressing the S0I floating body effect includes the following steps:
  • Step 1 as shown in FIG. 2a, a shallow trench isolation structure 30 is formed on the Si material (S0I) having the insulating buried layer 20, the active region 700 is isolated, and a gate region is formed on the active region 700, that is, A gate dielectric layer 81 and a gate electrode 82 are sequentially formed on the source region 700, wherein the gate electrode 82 can be made of a polysilicon material. P ion implantation of the active region can be performed to adjust the threshold voltage before the gate region is formed.
  • Step 2 as shown in FIG. 2b, performing high-dose source region light doping (LDS) and drain region light doping (LDD).
  • LDD source region light doping
  • LDD drain region light doping
  • the difference from the conventional LDD/LDS is:
  • the lightly doped source-drain N-type implant dose reaches the order of lel5/cm 2 , so it can be called a highly doped source drain, thus forming a lightly doped N-type source region 500 and a lightly doped N-type drain region.
  • 400 has a higher doping concentration and their actual concentration reaches le 9 /cm 3 .
  • this process still cites the name LDD/LDS that the industry has been using.
  • Step 3 As shown in FIG. 2c, a sidewall spacer 90 is formed around the gate region, and silicon oxide or nitride can be used. Materials such as silicon. Since the high-dose LDD/LDS process is used in step two, it is ensured that the channel current still flows from the source through the N-type LDS, and on the other hand, the low source-drain resistance is ensured, so only this step is required.
  • the primary source and drain regions are ion implanted to form an N-type Si material source region 50 and an N-type drain region 40 without requiring a secondary sidewall spacer process for secondary source-drain implantation. Thus, the body region 70 is formed between the N-type S i material source region 50 and the N-type drain region 40.
  • Step 4 As shown in FIG. 2d, a mask having an opening at the position of the source region 50 of the N-type Si material is used, and a large-angle heavily doped P ion implantation is performed obliquely through the mask. Controlling P ion implantation between the N-type Si material source region 50 and the body region 70, thereby forming a heavily doped P-type region 60; performing the large-angle heavily doped P ion implantation to be perpendicular to the N
  • the vertical surface of the surface of the source material region 50 of the type Si material is used as a reference, and the inclination angle is in the range of more than 15 degrees and less than or equal to 45 degrees, preferably 35 degrees.
  • Step 5 forming a layer of metal, such as Co, Ti, on the exposed surface of the source region 50 of the N-type Si material, and then reacting the metal with the Si material underneath to form a silicide 51 by heat treatment until the silicide 51 is formed.
  • the insulating buried layer 20 is in contact, and the remaining Si material that does not react with the metal becomes the N-type Si region 52.
  • the heat treatment may be carried out by a furnace tube annealing process at a temperature of 700-900 ° C, preferably 800 ° C, and an annealing time of 60-90 seconds, preferably 80 seconds.
  • the silicide 51 formed by the reaction of Co with S i is cobalt silicide, and Ti reacts with S i to form silicon silicide.
  • the generated silicide 51 and the N-type Si region 52 constitute an N-type source region, and the heavily doped P-type region 60 forms an ohmic contact with the generated silicide 51, and respectively with the insulating buried layer 20, the body region 70, N
  • the N-type Si region 52 of the type source region is in contact with the silicide 51, and finally the MOS device structure as shown in Fig. 2e is completed.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

L'invention concerne un procédé de fabrication d'un semiconducteur métal-oxyde (MOS) en silicium sur isolant (SOI) afin de réaliser un contact ohmique entre la source et le corps. Le procédé comprend les étapes suivantes : fabriquer une région de grille ; réaliser des implantations faiblement dopées à haute dose dans une région de source et une région de drain, afin de former une région de source de type n faiblement dopée et une région de drain de type n faiblement dopée à concentration élevée ; préparer des structures d'isolation de parois latérales (90) autour de la région de grille ; effectuer une implantation ionique dans la région de source et de drain ; effectuer une implantation ionique p fortement dopée et à gradient, à l'aide d'un masque présentant une ouverture dans la position de la région de source et la région de corps (70) ; former une couche de métal sur une partie de la surface de la région de source et faire réagir le métal avec le matériau Si sous-jacent pour former du siliciure (51), à l'aide d'un traitement thermique. Le siliciure (51) peut libérer des trous accumulés dans la région de corps (70) du dispositif MOS SOI par formation d'un contact ohmique avec la région latérale de type p fortement dopée (60), ce qui évite l'effet de corps flottant du dispositif MOS SOI et présente les avantages de ne pas augmenter la surface de la puce et d'utiliser des techniques de fabrication compatibles.
PCT/CN2010/076683 2010-07-06 2010-09-07 Procédé de fabrication d'un dispositif mos soi afin de réaliser un contact ohmique de la source et du corps WO2012003659A1 (fr)

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US13/131,126 US8354310B2 (en) 2010-07-06 2010-09-07 SOI MOS device having a source/body ohmic contact and manufacturing method thereof

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CN201010220390.5 2010-07-06
CN2010102203905A CN101950723B (zh) 2010-07-06 2010-07-06 实现源体欧姆接触且基于soi的mos器件制作方法

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Cited By (1)

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US8354310B2 (en) 2010-07-06 2013-01-15 Shanghai Institute Of Microsystem And Information Technology, Chinese Academy Of Sciences SOI MOS device having a source/body ohmic contact and manufacturing method thereof

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CN103311250A (zh) * 2013-05-23 2013-09-18 中国科学院上海微系统与信息技术研究所 一种六晶体管静态随机存储器单元
CN103325788B (zh) * 2013-06-18 2016-03-23 中国科学院上海微系统与信息技术研究所 一种八晶体管静态随机存储器单元
CN109119464B (zh) * 2018-10-24 2023-08-29 创智联慧(重庆)科技有限公司 一种新型离子注入型pd soi器件及其制备方法

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CN1779989A (zh) * 2005-09-23 2006-05-31 中国科学院上海微系统与信息技术研究所 抗辐射加固的特殊体接触绝缘体上硅场效应晶体管及制备方法
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CN101950723A (zh) 2011-01-19

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