WO2012003659A1 - Method of manufacturing soi mos device for achieving ohmic contact of source and body - Google Patents

Method of manufacturing soi mos device for achieving ohmic contact of source and body Download PDF

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Publication number
WO2012003659A1
WO2012003659A1 PCT/CN2010/076683 CN2010076683W WO2012003659A1 WO 2012003659 A1 WO2012003659 A1 WO 2012003659A1 CN 2010076683 W CN2010076683 W CN 2010076683W WO 2012003659 A1 WO2012003659 A1 WO 2012003659A1
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region
type
source
doped
source region
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PCT/CN2010/076683
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French (fr)
Chinese (zh)
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陈静
伍青青
罗杰馨
黄晓橹
王曦
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中国科学院上海微系统与信息技术研究所
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Priority to US13/131,126 priority Critical patent/US8354310B2/en
Publication of WO2012003659A1 publication Critical patent/WO2012003659A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78612—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/78654—Monocrystalline silicon transistors

Definitions

  • the present invention relates to a method of fabricating a MOS (Metal O Oxide Semi conduc tor ) structure, and more particularly to a method of fabricating an SOI MOS device for ohmic contact of a source by a silicide process, and belongs to the field of semiconductor manufacturing technology.
  • MOS Metal O Oxide Semi conduc tor
  • SOI Silicon-on-insulator technology
  • the device In the S0 I technology, the device is only fabricated in a thin silicon film. The device is separated from the substrate by a layer of buried oxide. This structure makes the SOI technology have advantages that are not comparable to bulk silicon. .
  • the small parasitic capacitance makes the S0I device high speed and low power consumption.
  • the all-media isolation of SOI CMOS devices completely eliminates the parasitic latch-up effect of bulk silicon CMOS devices.
  • S0I full-medium isolation makes S0I technology highly integrated and resistant to radiation.
  • S0I technology is widely used in radio frequency, high voltage, anti-irradiation and other fields. As device sizes continue to shrink, S0I technology is likely to replace bulk silicon as the first choice for S i technology.
  • the SOI M0S is divided into a partially depleted SO I MOS (PD SOI ) and a fully depleted SOI MOS ( FD SOI ) depending on whether the active body region is depleted.
  • PD SOI partially depleted SO I MOS
  • FD SOI fully depleted SOI MOS
  • the fully depleted SOI M0S threshold voltage is not easy to control. Therefore, it is still commonly used to partially deplete SO I M0S.
  • the active body region of the partially depleted SOI MOS is not completely depleted, so that the body region is in a floating state, and the charge generated by the impact ionization cannot be quickly removed, which results in a unique floating body effect of the SOI MOS.
  • the hole flows to the body region, and the SOI M0S floating body effect causes the holes to accumulate in the body region, thereby raising the body potential, making the SOI ⁇ OS
  • the threshold voltage is reduced and the leakage current is increased, resulting in a warpage of the output characteristic curve I d Vd of the device. This phenomenon is called the Kink effect.
  • the K ink effect has many adverse effects on device and circuit performance and reliability, and should be suppressed as much as possible during device design.
  • SOI PM0S due to the low ionization rate of holes, the electricity generated by impact ionization The sub-hole pair is much lower than the SOI MN, so the Kink effect in SOI PM0S is not obvious.
  • the body contact is usually connected to a fixed potential (source or ground) by means of a body contact, as shown in Figure la-lb, for a conventional T-gate structure contact,
  • the P + implant region formed at one end of the T-type gate is connected to the P-type body region under the gate.
  • the present invention proposes a novel fabrication process of the MOS structure, which is simple and easy to be compatible with the integrated circuit process.
  • the technical problem to be solved by the present invention is to provide a SOI MOS device manufacturing method for realizing ohmic contact of a source body, which effectively suppresses the S0I floating body effect by a silicide process.
  • a method for fabricating an SO I MOS device for achieving ohmic contact of a source body includes the following steps: Step 1: forming a shallow trench isolation structure on a Si material having an insulating buried layer, isolating an active region, and is in an active region Making a grid area;
  • Step 2 performing high-dose light doping of the source region and light doping of the drain region to form a high concentration lightly doped N-type source region and a lightly doped N-type drain region, the high-dose source region being lightly doped and
  • the light-doped implant dose of the drain region reaches the order of 1 e 15 /cm 2
  • the concentration of the high-concentration lightly doped N-type source region and the lightly doped N-type drain region reaches the order of le 9 /cm 3 ;
  • Step 3 preparing an insulating sidewall spacer structure around the gate region, and then performing ion implantation in the source region and the drain region to form an N-type S i material source region and an N-type drain region, and forming a body region therebetween;
  • Step 4 using a mask plate having an opening at a position of the source region of the N-type Si material, and performing a large-angle heavily doped P ion implantation in an oblique manner through the mask plate to control P ion implantation to Between the source region of the N-type Si material and the body region, thereby forming a heavily doped P-type region; performing vertical-doped heavily doped P ion implantation to be perpendicular to the surface of the source region of the N-type Si material Straight surface as the reference, the angle of inclination is More than 15 degrees less than or equal to 45 degrees;
  • Step 5 forming a layer of metal on the surface of the source region of the N-type Si material, and then reacting the metal with the underlying Si material to form a silicide by heat treatment until the generated silicide is in contact with the insulating buried layer.
  • the remaining S i material that does not react with the metal becomes an N-type Si region, and the formed silicide and N-type Si region constitute an N-type source region, and the heavily doped P-type region forms an ohmic contact with the generated silicide.
  • the insulating buried layer, the body region, the N-type Si region of the N-type source region and the silicide and finally completing the structure of the MOS device.
  • step 1 P ion implantation may be performed on the S i material before the gate region is formed.
  • the inclination angle is preferably 35 degrees.
  • the metal is selected from one of Co and Ti.
  • the heat treatment is preferably carried out by a furnace tube annealing process at a temperature of 700 to 900 ° C and a time of 60 to 90 seconds.
  • the method for fabricating an SOI MOS device for realizing ohmic contact of a source body has the beneficial effects of: using a tilt angle ion implantation method and a silicide process, under the N-type Si region of the source region, silicide and body region A heavily doped P-type region is formed to form an ohmic contact between the source region silicide and the heavily doped P region, releasing holes accumulated in the body region of the SOI MOS device, thereby suppressing the floating body effect of the SOI MOS device.
  • the invention effectively suppresses the floating body effect, and has the advantages of not increasing the chip area, and the manufacturing process is simple and compatible with the conventional CMOS process.
  • FIG. 1a is a schematic top view of a MOS structure in which a body contact method is used to suppress a floating body effect in the background art
  • FIG. 1b is a schematic cross-sectional view of a MOS structure in which a body contact method is used to suppress a floating body effect in the background art
  • FIGS. 2a-2e are diagrams using the method of the present invention. Schematic diagram of the process flow for fabricating the MOS device structure.
  • a MOS device structure for suppressing the SOI floating body effect includes: a substrate 10, an insulating buried layer 20 on the substrate 10, an active region on the insulating buried layer 20, and the Active A gate region over the region and a shallow trench isolation (STI) structure 30 located around the active region.
  • STI shallow trench isolation
  • the active region includes: a body region 70, an N-type source region, an N-type drain region 40, and a heavily doped P-type region 60;
  • the N-type source region is composed of a silicide 51 and an N-type Si region 52 connected thereto
  • the two-part source region and the N-type drain region 40 are respectively located at two ends of the body region 70;
  • the heavily doped P-type region 60 is located under the N-type Si region 52 of the N-type source region, and the silicide 51 and
  • the body regions 70 are surrounded by the silicide 51, the insulating buried layer 20, the body region 70, and the N-type Si region 52 without being in contact with the shallow trench isolation structure 30.
  • the gate region includes a gate dielectric layer 81 and a gate electrode 82 on the gate dielectric layer 81.
  • An insulating sidewall spacer 90 is disposed around the gate region.
  • the active area is mainly made of S i material.
  • the body region 70 may be a P-type Si material.
  • the N-type drain region 40 is made of an N-type S i material.
  • the insulating buried layer 20 may be made of silicon dioxide or silicon nitride. In a specific example of the present invention, silicon dioxide, that is, a buried oxide layer (BOX) may be used.
  • the silicide 51 can be any conductive silicide (eg, cobalt silicide, titanium silicide) that can form an ohmic contact with the heavily doped P-type region 60 adjacent thereto for releasing holes accumulated in the body region of the SOI 0S device. Thereby suppressing the floating body effect of the SOI MOS device.
  • the Kink effect due to the floating body effect is not obvious in the SOI PM0S, so the solution of the present invention is mainly directed to the SOI wake up OS device.
  • the above-mentioned method for fabricating the MOSFET device structure for suppressing the S0I floating body effect includes the following steps:
  • Step 1 as shown in FIG. 2a, a shallow trench isolation structure 30 is formed on the Si material (S0I) having the insulating buried layer 20, the active region 700 is isolated, and a gate region is formed on the active region 700, that is, A gate dielectric layer 81 and a gate electrode 82 are sequentially formed on the source region 700, wherein the gate electrode 82 can be made of a polysilicon material. P ion implantation of the active region can be performed to adjust the threshold voltage before the gate region is formed.
  • Step 2 as shown in FIG. 2b, performing high-dose source region light doping (LDS) and drain region light doping (LDD).
  • LDD source region light doping
  • LDD drain region light doping
  • the difference from the conventional LDD/LDS is:
  • the lightly doped source-drain N-type implant dose reaches the order of lel5/cm 2 , so it can be called a highly doped source drain, thus forming a lightly doped N-type source region 500 and a lightly doped N-type drain region.
  • 400 has a higher doping concentration and their actual concentration reaches le 9 /cm 3 .
  • this process still cites the name LDD/LDS that the industry has been using.
  • Step 3 As shown in FIG. 2c, a sidewall spacer 90 is formed around the gate region, and silicon oxide or nitride can be used. Materials such as silicon. Since the high-dose LDD/LDS process is used in step two, it is ensured that the channel current still flows from the source through the N-type LDS, and on the other hand, the low source-drain resistance is ensured, so only this step is required.
  • the primary source and drain regions are ion implanted to form an N-type Si material source region 50 and an N-type drain region 40 without requiring a secondary sidewall spacer process for secondary source-drain implantation. Thus, the body region 70 is formed between the N-type S i material source region 50 and the N-type drain region 40.
  • Step 4 As shown in FIG. 2d, a mask having an opening at the position of the source region 50 of the N-type Si material is used, and a large-angle heavily doped P ion implantation is performed obliquely through the mask. Controlling P ion implantation between the N-type Si material source region 50 and the body region 70, thereby forming a heavily doped P-type region 60; performing the large-angle heavily doped P ion implantation to be perpendicular to the N
  • the vertical surface of the surface of the source material region 50 of the type Si material is used as a reference, and the inclination angle is in the range of more than 15 degrees and less than or equal to 45 degrees, preferably 35 degrees.
  • Step 5 forming a layer of metal, such as Co, Ti, on the exposed surface of the source region 50 of the N-type Si material, and then reacting the metal with the Si material underneath to form a silicide 51 by heat treatment until the silicide 51 is formed.
  • the insulating buried layer 20 is in contact, and the remaining Si material that does not react with the metal becomes the N-type Si region 52.
  • the heat treatment may be carried out by a furnace tube annealing process at a temperature of 700-900 ° C, preferably 800 ° C, and an annealing time of 60-90 seconds, preferably 80 seconds.
  • the silicide 51 formed by the reaction of Co with S i is cobalt silicide, and Ti reacts with S i to form silicon silicide.
  • the generated silicide 51 and the N-type Si region 52 constitute an N-type source region, and the heavily doped P-type region 60 forms an ohmic contact with the generated silicide 51, and respectively with the insulating buried layer 20, the body region 70, N
  • the N-type Si region 52 of the type source region is in contact with the silicide 51, and finally the MOS device structure as shown in Fig. 2e is completed.

Abstract

A method of manufacturing a silicon-on-insulator metal-oxide-semiconductor (SOI MOS) device for achieving ohmic contact of source and body is provided. The method includes: fabricating a gate region, performing high dose light-doped implantations of a source region and a drain region to form a light-doped N-type source region and a light-doped N-type drain region with high concentration; preparing sidewall isolation structures(90) around the gate region, performing an ion implantation to the source and drain region, performing a sloping heavily-doped P ion implantation by a mask with an opening in the position of the source region to form a heavily-doped P-type region(60) between the source region and the body region(70); forming a layer of metal on partial surface of the source region, and make the metal react with underlying Si material to form silicide(51) by a heat process. The silicide(51) may release holes accumulated in the body region(70) of SOI MOS device by forming ohmic contact with the lateral heavily doped P-type region(60), thus suppressing floating body effect of SOI MOS device, and having advantages of no increasing of chip area and compatible manufacturing techniques.

Description

实现源体欧姆接触的 SOI MOS器件制作方法  SOI MOS device manufacturing method for realizing ohmic contact of source body
技术领域 本发明涉及一种 MOS ( Meta l Oxide Semi conduc tor ) 结构的制作方法， 尤 其是一种通过硅化物工艺实现源体欧姆接触的 SOI M0S器件制作方法， 属于半导 体制造技术领域。 BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating a MOS (Metal O Oxide Semi conduc tor ) structure, and more particularly to a method of fabricating an SOI MOS device for ohmic contact of a source by a silicide process, and belongs to the field of semiconductor manufacturing technology.
背景技术 Background technique
SOI (S i l i con On Insula tor)是指绝缘体上硅技术。 在 S0 I技术中， 器件仅 制造于表层很薄的硅膜中， 器件与衬底之间由一层隐埋氧化层隔开， 正是这种结 构使得 S0I技术具有了体硅无法比拟的优点。 寄生电容小， 使得 S0I器件拥有高 速度和低功耗。 SOI CMOS器件的全介质隔离彻底消除了体硅 CMOS器件的寄生闩 锁效应， S0I全介质隔离使得 S0I技术集成密度高以及抗辐照特性好。 S0I技术 广泛应用于射频、 高压、 抗辐照等领域。 随着器件尺寸的不断缩小， S0I技术极 有可能替代体硅成为 S i技术的首选。 SOI (S i l i con On Insula tor) refers to silicon-on-insulator technology. In the S0 I technology, the device is only fabricated in a thin silicon film. The device is separated from the substrate by a layer of buried oxide. This structure makes the SOI technology have advantages that are not comparable to bulk silicon. . The small parasitic capacitance makes the S0I device high speed and low power consumption. The all-media isolation of SOI CMOS devices completely eliminates the parasitic latch-up effect of bulk silicon CMOS devices. S0I full-medium isolation makes S0I technology highly integrated and resistant to radiation. S0I technology is widely used in radio frequency, high voltage, anti-irradiation and other fields. As device sizes continue to shrink, S0I technology is likely to replace bulk silicon as the first choice for S i technology.
SOI M0S根据有源体区是否耗尽分为部分耗尽 SO I MOS ( PD SOI )和全耗尽 SOI MOS ( FD SOI ) 。 一般来说全耗尽 SOI MOS顶层硅膜会比较薄， 薄膜 SOI硅 片成本高， 另一方面全耗尽 SOI M0S阈值电压不易控制。 因此目前普遍采用的还 是部分耗尽 SO I M0S。  The SOI M0S is divided into a partially depleted SO I MOS (PD SOI ) and a fully depleted SOI MOS ( FD SOI ) depending on whether the active body region is depleted. In general, the fully depleted SOI MOS top silicon film will be thinner, and the thin film SOI silicon wafer is costly. On the other hand, the fully depleted SOI M0S threshold voltage is not easy to control. Therefore, it is still commonly used to partially deplete SO I M0S.
部分耗尽 SOI MOS的有源体区并未完全耗尽， 使得体区处于悬空状态， 碰撞 电离产生的电荷无法迅速移走，这会导致 SOI M0S特有的浮体效应。对于 S0I丽 OS 沟道电子在漏端碰撞电离产生的电子-空穴对， 空穴流向体区， SOI M0S 浮体效 应导致空穴在体区积累， 从而抬高体区电势， 使得 S0I 丽 OS的阈值电压降低继 而漏电流增加， 导致器件的输出特性曲线 IdVd有翘曲现象， 这一现象称为 Kink 效应。 K ink 效应对器件和电路性能以及可靠性产生诸多不利的影响， 在器件设 计时应尽量抑制。 对 SOI PM0S , 由于空穴的电离率比较低， 碰撞电离产生的电 子-空穴对远低于 SOI 丽 OS , 因此 SOI PM0S中的 Kink效应不明显。 The active body region of the partially depleted SOI MOS is not completely depleted, so that the body region is in a floating state, and the charge generated by the impact ionization cannot be quickly removed, which results in a unique floating body effect of the SOI MOS. For the electron-hole pairs generated by the S0I Li OS channel electrons at the drain end collision ionization, the hole flows to the body region, and the SOI M0S floating body effect causes the holes to accumulate in the body region, thereby raising the body potential, making the SOI 丽 OS The threshold voltage is reduced and the leakage current is increased, resulting in a warpage of the output characteristic curve I d Vd of the device. This phenomenon is called the Kink effect. The K ink effect has many adverse effects on device and circuit performance and reliability, and should be suppressed as much as possible during device design. For SOI PM0S, due to the low ionization rate of holes, the electricity generated by impact ionization The sub-hole pair is much lower than the SOI MN, so the Kink effect in SOI PM0S is not obvious.
为了解决部分耗尽 SOI NM0S,通常采用体接触（body contact)的方法将 "体" 接固定电位 （源端或地） , 如图 la-lb 所示， 为传统 T型栅结构体接触， 在 T 型栅的一端形成的 P+注入区与栅下面的 P型体区相连， M0S器件工作时， 体区积 累的载流子通过 P+通道泄放， 达到降低体区电势的目的， 负面作用是造成工艺流 程复杂化， 寄生效应增加， 降低了部分电学性能并且增大了器件面积。 In order to solve the partially depleted SOI NM0S, the body contact is usually connected to a fixed potential (source or ground) by means of a body contact, as shown in Figure la-lb, for a conventional T-gate structure contact, The P + implant region formed at one end of the T-type gate is connected to the P-type body region under the gate. When the MOS device is in operation, the carriers accumulated in the body region are vented through the P + channel to reduce the potential of the body region, and the negative effect It is a process that complicates the process, increases parasitic effects, reduces part of the electrical performance and increases the device area.
鉴于此， 本发明为了抑制 SOI M0S器件中的浮体效应， 提出一种新型的 M0S 结构的制作工艺， 该工艺简单易行与集成电路工艺相兼容。 发明内容 本发明要解决的技术问题在于提供一种实现源体欧姆接触的 SOI M0S器件制 作方法， 通过硅化物工艺有效抑制 S0I浮体效应。  In view of this, in order to suppress the floating body effect in the SOI MOS device, the present invention proposes a novel fabrication process of the MOS structure, which is simple and easy to be compatible with the integrated circuit process. SUMMARY OF THE INVENTION The technical problem to be solved by the present invention is to provide a SOI MOS device manufacturing method for realizing ohmic contact of a source body, which effectively suppresses the S0I floating body effect by a silicide process.
为了解决上述技术问题， 本发明采用如下技术方案：  In order to solve the above technical problem, the present invention adopts the following technical solutions:
一种实现源体欧姆接触的 SO I M0S器件制作方法， 包括以下步骤： 步骤一、 在具有绝缘埋层的 S i材料上制作浅沟槽隔离结构， 隔离出有源区， 并在有源区上制作栅区；  A method for fabricating an SO I MOS device for achieving ohmic contact of a source body includes the following steps: Step 1: forming a shallow trench isolation structure on a Si material having an insulating buried layer, isolating an active region, and is in an active region Making a grid area;
步骤二、 进行高剂量的源区轻掺杂和漏区轻掺杂， 形成高浓度的轻掺杂 N 型源区和轻掺杂 N型漏区，所述高剂量的源区轻掺杂和漏区轻掺杂注入剂量达到 1 e 15 / cm2的量级， 所述高浓度的轻掺杂 N型源区和轻掺杂 N型漏区的浓度达到 lel9/cm3的量级； Step 2: performing high-dose light doping of the source region and light doping of the drain region to form a high concentration lightly doped N-type source region and a lightly doped N-type drain region, the high-dose source region being lightly doped and The light-doped implant dose of the drain region reaches the order of 1 e 15 /cm 2 , and the concentration of the high-concentration lightly doped N-type source region and the lightly doped N-type drain region reaches the order of le 9 /cm 3 ;
步骤三、 在所述栅区周围制备绝缘侧墙隔离结构， 然后进行源区和漏区离子 注入， 形成 N型 S i材料源区和 N型漏区， 在它们之间形成体区；  Step 3, preparing an insulating sidewall spacer structure around the gate region, and then performing ion implantation in the source region and the drain region to form an N-type S i material source region and an N-type drain region, and forming a body region therebetween;
步骤四、 釆用一道在所述 N型 S i材料源区的位置设有开口的掩膜版， 经由 该掩膜版以倾斜的方式进行大角度重掺杂 P离子注入， 控制 P离子注入至所述 N 型 Si材料源区与体区之间， 从而形成重掺杂的 P型区； 进行所述大角度重掺杂 P 离子注入时以垂直于所述 N型 Si材料源区表面的竖直面为基准， 倾斜角度在 大于 15度小于等于 45度的范围内； Step 4: using a mask plate having an opening at a position of the source region of the N-type Si material, and performing a large-angle heavily doped P ion implantation in an oblique manner through the mask plate to control P ion implantation to Between the source region of the N-type Si material and the body region, thereby forming a heavily doped P-type region; performing vertical-doped heavily doped P ion implantation to be perpendicular to the surface of the source region of the N-type Si material Straight surface as the reference, the angle of inclination is More than 15 degrees less than or equal to 45 degrees;
步骤五、 在所述 N型 S i材料源区表面形成一层金属， 然后通过热处理使该 金属与其下的 S i材料反应生成硅化物，直至生成的硅化物与所述绝缘埋层接触， 而剩余的未与该金属反应的 S i材料成为 N型 S i区， 生成的硅化物和 N型 S i 区 构成 N型源区， 重掺杂的 P型区与生成的硅化物形成欧姆接触 , 并分别与所述绝 缘埋层、 体区、 N型源区的 N型 S i区和硅化物接触， 最终完成 M0S器件结构。  Step 5, forming a layer of metal on the surface of the source region of the N-type Si material, and then reacting the metal with the underlying Si material to form a silicide by heat treatment until the generated silicide is in contact with the insulating buried layer. The remaining S i material that does not react with the metal becomes an N-type Si region, and the formed silicide and N-type Si region constitute an N-type source region, and the heavily doped P-type region forms an ohmic contact with the generated silicide. And respectively contacting the insulating buried layer, the body region, the N-type Si region of the N-type source region and the silicide, and finally completing the structure of the MOS device.
进一步地， 步骤一中， 在制作所述栅区之前可以先对 S i材料进行 P离子注 入。 步骤四中， 所述倾斜角度优选为 35 度。 步骤五中， 所述金属选自 Co、 Ti 中的一种。 所述热处理优选为采用炉管退火工艺， 所述热处理的温度为 700-900 °C , 时间为 60-90秒。  Further, in step 1, P ion implantation may be performed on the S i material before the gate region is formed. In the fourth step, the inclination angle is preferably 35 degrees. In the fifth step, the metal is selected from one of Co and Ti. The heat treatment is preferably carried out by a furnace tube annealing process at a temperature of 700 to 900 ° C and a time of 60 to 90 seconds.
本发明公开的实现源体欧姆接触的 SOI M0S器件制作方法，其有益效果在于： 利用倾斜角度离子注入的方法以及硅化物工艺， 在源区的 N型 S i区下方， 硅化 物与体区之间形成了重掺杂的 P型区，使源区硅化物与该重掺杂 P区形成欧姆接 触， 释放 SOI M0S器件在体区积累的空穴， 从而抑制 SOI M0S器件的浮体效应。 本发明在有效抑制浮体效应的同时，还具有不会增加芯片面积， 制造工艺简单与 常规 CMOS工艺相兼容等优点。  The method for fabricating an SOI MOS device for realizing ohmic contact of a source body has the beneficial effects of: using a tilt angle ion implantation method and a silicide process, under the N-type Si region of the source region, silicide and body region A heavily doped P-type region is formed to form an ohmic contact between the source region silicide and the heavily doped P region, releasing holes accumulated in the body region of the SOI MOS device, thereby suppressing the floating body effect of the SOI MOS device. The invention effectively suppresses the floating body effect, and has the advantages of not increasing the chip area, and the manufacturing process is simple and compatible with the conventional CMOS process.
附图说明 图 la为背景技术中采用体接触方法抑制浮体效应的 M0S结构俯视示意图； 图 lb为背景技术中采用体接触方法抑制浮体效应的 M0S结构剖面示意图； 图 2a-2e为利用本发明方法制备 M0S器件结构的工艺流程示意图。 BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1a is a schematic top view of a MOS structure in which a body contact method is used to suppress a floating body effect in the background art; FIG. 1b is a schematic cross-sectional view of a MOS structure in which a body contact method is used to suppress a floating body effect in the background art; FIGS. 2a-2e are diagrams using the method of the present invention; Schematic diagram of the process flow for fabricating the MOS device structure.
具体实施方式 下面结合附图进一步说明本发明， 为了示出的方便附图并未按照比例绘制。 如图 2e所示， 一种抑制 S0I浮体效应的 M0S器件结构， 包括： 衬底 10、 位 于衬底 10之上的绝缘埋层 20、 位于绝缘埋层 20之上的有源区、 位于所述有源 区之上的栅区以及位于所述有源区周围的浅沟槽隔离 （STI ) 结构 30。 所述有源区包括： 体区 70、 N型源区、 N型漏区 40、 重掺杂 P型区 60; 所 述 N型源区由硅化物 51和与之相连的 N型 Si 区 52两部分组成； 所述 N型源区 和 N型漏区 40分别位于体区 70两端； 重掺杂 P型区 60位于所述 N型源区的 N 型 Si区 52下方， 硅化物 51与体区 70之间， 被硅化物 51、 绝缘埋层 20、 体区 70以及 N型 Si区 52包围， 而不与浅沟槽隔离结构 30接触。 The invention is further described in the following with reference to the accompanying drawings, in which As shown in FIG. 2e, a MOS device structure for suppressing the SOI floating body effect includes: a substrate 10, an insulating buried layer 20 on the substrate 10, an active region on the insulating buried layer 20, and the Active A gate region over the region and a shallow trench isolation (STI) structure 30 located around the active region. The active region includes: a body region 70, an N-type source region, an N-type drain region 40, and a heavily doped P-type region 60; the N-type source region is composed of a silicide 51 and an N-type Si region 52 connected thereto The two-part source region and the N-type drain region 40 are respectively located at two ends of the body region 70; the heavily doped P-type region 60 is located under the N-type Si region 52 of the N-type source region, and the silicide 51 and The body regions 70 are surrounded by the silicide 51, the insulating buried layer 20, the body region 70, and the N-type Si region 52 without being in contact with the shallow trench isolation structure 30.
其中， 所述栅区包括栅介质层 81和位于所述栅介质层 81上的栅电极 82。 在所述栅区周围设有绝缘侧墙隔离结构 90。 有源区主要采用 S i材料。 其中体区 70可采用 P型的 Si材料。 N型漏区 40采用 N型的 S i材料。 绝缘埋层 20可采用 二氧化硅或氮化硅材料， 在本发明一具体例子中可采用二氧化硅， 即为埋层氧化 层（BOX ) 。 硅化物 51可以是任何导电的硅化物（例如硅化钴、 硅化钛） ， 使其 可以与旁边的重掺杂 P型区 60形成欧姆接触， 用于释放 SOI 0S器件在体区积 累的空穴， 从而抑制 SOI M0S器件的浮体效应。 由于浮体效应导致的 Kink效应 在 SOI PM0S中不明显， 因此本发明的方案主要是针对 S0I 醒 OS器件。  The gate region includes a gate dielectric layer 81 and a gate electrode 82 on the gate dielectric layer 81. An insulating sidewall spacer 90 is disposed around the gate region. The active area is mainly made of S i material. The body region 70 may be a P-type Si material. The N-type drain region 40 is made of an N-type S i material. The insulating buried layer 20 may be made of silicon dioxide or silicon nitride. In a specific example of the present invention, silicon dioxide, that is, a buried oxide layer (BOX) may be used. The silicide 51 can be any conductive silicide (eg, cobalt silicide, titanium silicide) that can form an ohmic contact with the heavily doped P-type region 60 adjacent thereto for releasing holes accumulated in the body region of the SOI 0S device. Thereby suppressing the floating body effect of the SOI MOS device. The Kink effect due to the floating body effect is not obvious in the SOI PM0S, so the solution of the present invention is mainly directed to the SOI wake up OS device.
上述抑制 S0I浮体效应的 M0S器件结构的制作方法， 如图 2a-2e所示， 包括 以下步骤：  The above-mentioned method for fabricating the MOSFET device structure for suppressing the S0I floating body effect, as shown in Figs. 2a-2e, includes the following steps:
步骤一、 如图 2a , 在具有绝缘埋层 20的 S i材料（ S0I )上制作浅沟槽隔离 结构 30, 隔离出有源区 700， 并在有源区 700上制作栅区， 即在有源区 700上依 次制作栅介质层 81、 栅电极 82， 其中栅电极 82可釆用多晶硅材料。 在制作栅区 之前可以先对有源区进行 P离子注入用于调节阈值电压。  Step 1, as shown in FIG. 2a, a shallow trench isolation structure 30 is formed on the Si material (S0I) having the insulating buried layer 20, the active region 700 is isolated, and a gate region is formed on the active region 700, that is, A gate dielectric layer 81 and a gate electrode 82 are sequentially formed on the source region 700, wherein the gate electrode 82 can be made of a polysilicon material. P ion implantation of the active region can be performed to adjust the threshold voltage before the gate region is formed.
步骤二、 如图 2b， 进行高剂量的源区轻掺杂 （LDS ) 和漏区轻掺杂 （LDD ) ， 在这一步骤中， 与传统的 LDD/LDS 不同之处在于： 本发明实际的轻掺杂源漏 N 型注入剂量达到 lel5/cm2的量级， 所以可以称之为高摻杂源漏了， 由此形成的 轻掺杂 N型源区 500和轻掺杂 N型漏区 400具有较高的掺杂浓度，它们实际的浓 度达到 lel 9/cm3。 然而为了与源漏注入区别， 这道工艺还是援引业界一直釆用的 名称 LDD/LDS。 Step 2, as shown in FIG. 2b, performing high-dose source region light doping (LDS) and drain region light doping (LDD). In this step, the difference from the conventional LDD/LDS is: The lightly doped source-drain N-type implant dose reaches the order of lel5/cm 2 , so it can be called a highly doped source drain, thus forming a lightly doped N-type source region 500 and a lightly doped N-type drain region. 400 has a higher doping concentration and their actual concentration reaches le 9 /cm 3 . However, in order to distinguish it from source-drain injection, this process still cites the name LDD/LDS that the industry has been using.
步骤三、 如图 2c， 在栅区周围制作侧墙隔离结构 90, 可釆用氧化硅或氮化 硅等材料。 由于在步骤二中采用了高剂量的 LDD/LDS工艺，保证了沟道电流依然 从源端通过 N型的 LDS流出， 另一方面保证低的源漏电阻， 所以在这一步骤中仅 需要进行一次源区和漏区离子注入， 形成 N型 Si材料源区 50和 N型漏区 40 , 而不需要二次侧墙工艺来进行二次源漏注入。 这样在 N型 S i材料源区 50和 N 型漏区 40之间形成体区 70。 Step 3: As shown in FIG. 2c, a sidewall spacer 90 is formed around the gate region, and silicon oxide or nitride can be used. Materials such as silicon. Since the high-dose LDD/LDS process is used in step two, it is ensured that the channel current still flows from the source through the N-type LDS, and on the other hand, the low source-drain resistance is ensured, so only this step is required. The primary source and drain regions are ion implanted to form an N-type Si material source region 50 and an N-type drain region 40 without requiring a secondary sidewall spacer process for secondary source-drain implantation. Thus, the body region 70 is formed between the N-type S i material source region 50 and the N-type drain region 40.
步骤四、 如图 2d， 釆用一道在所述 N型 S i材料源区 50的位置设有开口的 掩膜版， 经由该掩膜版以倾斜的方式进行大角度重掺杂 P离子注入， 控制 P离子 注入至所述 N型 Si材料源区 50与体区 70之间 , 从而形成重掺杂的 P型区 60; 进行所述大角度重掺杂 P离子注入时以垂直于所述 N型 Si材料源区 50表面的竖 直面为基准， 倾斜角度在大于 15度小于等于 45度的范围内， 优选 35度。  Step 4: As shown in FIG. 2d, a mask having an opening at the position of the source region 50 of the N-type Si material is used, and a large-angle heavily doped P ion implantation is performed obliquely through the mask. Controlling P ion implantation between the N-type Si material source region 50 and the body region 70, thereby forming a heavily doped P-type region 60; performing the large-angle heavily doped P ion implantation to be perpendicular to the N The vertical surface of the surface of the source material region 50 of the type Si material is used as a reference, and the inclination angle is in the range of more than 15 degrees and less than or equal to 45 degrees, preferably 35 degrees.
步骤五、 在 N型 Si材料源区 50露出的表面形成一层金属， 例如 Co、 Ti , 然后通过热处理使该金属与其下的 S i材料反应生成硅化物 51， 直至生成的硅化 物 51与所述绝缘埋层 20接触， 而剩余的未与该金属反应的 Si材料成为 N型 S i 区 52。 热处理可采用炉管退火工艺， 温度为 700-900 °C , 优选 800°C , 退火时间 为 60-90秒， 优选 80秒。 Co与 S i反应生成的硅化物 51为硅化钴， Ti与 S i反 应生成硅 钛。 生成的硅化物 51和 N型 Si区 52构成 N型源区， 重掺杂的 P型 区 60与生成的硅化物 51形成欧姆接触， 并分别与所述绝缘埋层 20、 体区 70、 N 型源区的 N型 Si区 52和硅化物 51接触，最终完成如图 2e所示的 M0S器件结构。  Step 5, forming a layer of metal, such as Co, Ti, on the exposed surface of the source region 50 of the N-type Si material, and then reacting the metal with the Si material underneath to form a silicide 51 by heat treatment until the silicide 51 is formed. The insulating buried layer 20 is in contact, and the remaining Si material that does not react with the metal becomes the N-type Si region 52. The heat treatment may be carried out by a furnace tube annealing process at a temperature of 700-900 ° C, preferably 800 ° C, and an annealing time of 60-90 seconds, preferably 80 seconds. The silicide 51 formed by the reaction of Co with S i is cobalt silicide, and Ti reacts with S i to form silicon silicide. The generated silicide 51 and the N-type Si region 52 constitute an N-type source region, and the heavily doped P-type region 60 forms an ohmic contact with the generated silicide 51, and respectively with the insulating buried layer 20, the body region 70, N The N-type Si region 52 of the type source region is in contact with the silicide 51, and finally the MOS device structure as shown in Fig. 2e is completed.
本发明中涉及的其他技术属于本领域技术人员熟悉的范畴， 在此不再赘述。 上述实施例仅用以说明而非限制本发明的技术方案。任何不脱离本发明精神和范 围的技术方案均应涵盖在本发明的专利申请范围当中。  Other technologies involved in the present invention are within the scope familiar to those skilled in the art and will not be described herein. The above embodiments are only illustrative and not limiting of the technical solutions of the present invention. Any technical solution that does not depart from the spirit and scope of the present invention should be covered by the scope of the patent application of the present invention.

Claims

权利要求书 Claim
1. 一种实现源体欧姆接触的 SOI M0S 器件制作方法， 其特征在于， 包括以 下步骤： A method of fabricating an SOI MOS device for ohmic contact of a source body, comprising the steps of:
步骤一、 在具有绝缘埋层的 S i材料上制作浅沟槽隔离结构， 隔离出 有源区， 并在有源区上制作栅区；  Step 1: forming a shallow trench isolation structure on the Si material having an insulating buried layer, isolating the active region, and forming a gate region on the active region;
步骤二、 进行高剂量的源区轻掺杂和漏区轻掺杂， 形成高浓度的轻 掺杂 N型源区和轻掺杂 N型漏区， 所述高剂量的源区轻掺杂和漏区轻掺 杂注入剂量达到 lel 5/cm2的量级， 所述高浓度的轻掺杂 N型源区和轻掺 杂 N型漏区的浓度达到 lel9/cm3的量级； Step 2: performing high-dose light doping of the source region and light doping of the drain region to form a high concentration lightly doped N-type source region and a lightly doped N-type drain region, wherein the high-dose source region is lightly doped and The light-doped implant dose of the drain region reaches the order of lel 5/cm 2 , and the concentration of the high-concentration light-doped N-type source region and the lightly doped N-type drain region reaches the order of lel 9/cm 3 ;
步骤三、 在所述栅区周围制备绝缘侧墙隔离结构， 然后进行源区和 漏区离子注入，形成 N型 Si材料源区和 N型漏区，在它们之间形成体区； 步骤四、采用一道在所述 N型 Si材料源区的位置设有开口的掩膜版， 经由该掩膜版以倾斜的方式进行大角度重掺杂 P 离子注入， 控制 P 离子 注入至所述 N型 S i材料源区与体区之间， 从而形成重掺杂的 P型区； 进 行所述大角度重掺杂 P离子注入时以垂直于所述 N型 Si材料源区表面的 竖直面为基准， 倾斜角度在大于 15度小于等于 45度的范围内；  Step 3: preparing an insulating sidewall spacer structure around the gate region, and then performing ion implantation in the source region and the drain region to form an N-type Si material source region and an N-type drain region, and forming a body region therebetween; A mask having an opening at a position of the source region of the N-type Si material is used, and a large-angle heavily doped P ion implantation is performed obliquely through the mask to control P ion implantation to the N-type S Between the source region and the body region of the material, thereby forming a heavily doped P-type region; and performing the large-angle heavily doped P ion implantation on the basis of a vertical plane perpendicular to the surface of the source region of the N-type Si material , the inclination angle is in a range of more than 15 degrees and less than or equal to 45 degrees;
步骤五、 在所述 N型 Si材料源区表面形成一层金属， 然后通过热处 理使该金属与其下的 Si材料反应生成硅化物， 直至生成的硅化物与所述 绝缘埋层接触， 而剩余的未与该金属反应的 S i材料成为 N型 Si 区， 生 成的硅化物和 N型 Si区构成 N型源区， 重掺杂的 P型区与生成的硅化物 形成欧姆接触， 并分别与所述绝缘埋层、 体区、 N型源区的 N型 S i 区和 硅化物接触， 最终完成 M0S器件结构。  Step 5, forming a layer of metal on the surface of the source region of the N-type Si material, and then reacting the metal with the Si material underneath to form a silicide by heat treatment until the generated silicide is in contact with the insulating buried layer, and the remaining The Si material not reacting with the metal becomes an N-type Si region, and the formed silicide and the N-type Si region constitute an N-type source region, and the heavily doped P-type region forms an ohmic contact with the generated silicide, and respectively The insulating buried layer, the body region, and the N-type Si region of the N-type source region are in contact with the silicide, and finally the structure of the MOS device is completed.
2. 根据权利要求 1 所述实现源体欧姆接触的 SOI M0S器件制作方法， 其特 征在于： 步骤一中， 在制作所述栅区之前先对有源区进行 P离子注入。 2. The method of fabricating a source ohmic contact SOI MOS device according to claim 1, wherein: in step 1, P-ion implantation is performed on the active region before the gate region is formed.
3. 根据权利要求 1 所述实现源体欧姆接触的 SOI M0S器件制作方法， 其特 征在于： 步骤四中， 所述倾斜角度为 35度。 3. The method according to claim 1, wherein the step angle is 35 degrees.
4. 根据权利要求 1 所述实现源体欧姆接触的 SOI M0S器件制作方法， 其特 征在于： 步骤五中， 所述金属选自 Co、 Ti中的一种。 4. The method of fabricating an SOI MOS device for ohmic contact of a source according to claim 1, wherein in the step five, the metal is selected from one of Co and Ti.
5. 根据权利要求 1 所述实现源体欧姆接触的 SOI M0S器件制作方法， 其特 征在于： 步骤五中， 所述热处理釆用炉管退火工艺。 5. The method of fabricating a source ohmic contact SOI MOS device according to claim 1, wherein: in the fifth step, the heat treatment is performed by a furnace tube annealing process.
6. 根据权利要求 1 所述实现源体欧姆接触的 SOI M0S器件制作方法， 其特 征在于： 步骤五中， 所述热处理的温度为 700-900°C， 时间为 60-90秒。 6. The method of fabricating a source ohmic contact SOI MOS device according to claim 1, wherein: in the fifth step, the heat treatment temperature is 700-900 ° C, and the time is 60-90 seconds.
PCT/CN2010/076683 2010-07-06 2010-09-07 Method of manufacturing soi mos device for achieving ohmic contact of source and body WO2012003659A1 (en)

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