CN101231956A - Method for realizing portion exhaust insulators upper silicon device physical contact - Google Patents
Method for realizing portion exhaust insulators upper silicon device physical contact Download PDFInfo
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- CN101231956A CN101231956A CNA2007100629812A CN200710062981A CN101231956A CN 101231956 A CN101231956 A CN 101231956A CN A2007100629812 A CNA2007100629812 A CN A2007100629812A CN 200710062981 A CN200710062981 A CN 200710062981A CN 101231956 A CN101231956 A CN 101231956A
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Abstract
The invention relates to the technical field of body contact of SOI devices in the semiconductor technology, and discloses a method for achieving body contact of some depleted SOI devices. The invention comprises the following steps: A. after a polysilicon gate is formed, a body is led out and injected on one side of a source electrode; B. LDS and LDD are injected into source/drain ends; after a primary oxide side wall is formed, N+ is injected into source/drain areas to form shallow junctions in the source/drain areas; C. after the source area is protected with photosensitive resist, the drain area is injected with N+ for the second time so that a junction area on the drain end reaches a buried oxide layer, thus forming a source/drain unsymmetrical structure; D. cobaltic silicide is used; the cobaltic silicide on one side of a source electrode penetrates the source electrode and reaches a body area below, which limits the potential of the body area and inhibits floating effect. By adopting the invention, not only the floating effect is effectively inhibited, but also the performance of some depleted SOI devices is improved. In addition, the invention is compatible with standard complementary metal-oxide-semiconductor transistors, and has the advantages of simple process, low cost and so on.
Description
Technical field
The present invention relates to silicon-on-insulator in the semiconductor technology (SOI) device body contact technical field, relate in particular to a kind of method that realizes the contact of part depletion SOI device body.
Background technology
Along with reducing of device feature size, Moore's Law is just standing more and more acid test.Can Moore's Law sustainable development, depends on the appearance with novelty technology.The technology that has occurred a lot of novelties in recent years, as FinFET, single-electron device, double-gated devices etc., the tool development potentiality of SOI technology wherein.
The SOI device is divided into part depletion and exhausts two kinds entirely.Silicon fiml all exhausted when full depleted device was worked because of device, and potential barrier is very little between the body of source, so the hole of tagma accumulation can be flowed out by source electrode.Therefore, the full-exhaustion SOI device does not have floater effect.
But the full-exhaustion SOI device threshold voltage is very responsive to silicon film thickness, so threshold voltage is not easy control.And the full-exhaustion SOI device so the source ohmic leakage is big, can influence the speed of circuit because silicon fiml is extremely thin.
Therefore, the partial depletion SOI device is more suitable for large-scale production and application.But in partial depletion SOI device when work,, the hole that drain terminal depletion region ionization by collision produces flowed into the tagma, because source body potential barrier is higher, so the accumulation in hole takes place, causes the rising of tagma current potential with the rising of drain terminal voltage, Here it is floater effect.
People have taked a lot of measures to suppress floater effect, and wherein the most frequently used have T type grid and a H type grid body contact technique.But this technology is because the existence of volume resistance and can not effectively suppress floater effect, and raceway groove expanded letter resistance is big more more, floater effect is remarkable more.
BTS (Body-Tied-to-Source) structure is directly to form the P+ district in the source region, but the shortcoming of this method is that the source leakage is asymmetric, and effectively channel width reduces.
Document " Hua-Fang Wei; James E.Chung; et.al; " Improvement of RadiationHardness in Fully-depleted SOI n-MOSFETs Using Ge-Implantation ", IEEETransactions on Nuclear Science, NS-41; No.6; December 1994. " the Lifetime Control technology has been proposed, by injecting generation complex centres such as Ge, Ar, reduce minority carrier lifetime to channel region or source-drain area.But this method can not effectively suppress floater effect, and causes that leakage current is excessive.
Document " Liu Yunlong; Liu Xinyu; et.al; " Simulation of a Novel SchottkyBody-Contacted Structure Suppressing Floating Body Effect inPartially-Depleted SOI nMOSFET ' s "; CHINESE JOURNAL OFSEMICONDUCTOR; Vol.23; No.10; p.1019; Oct.2002 " has proposed the Schottky contact technique, utilize thick silicide in source region and tagma under the source region to form Schottky and contact and clamp down on the tagma current potential, but still there is the problem of volume resistance in this method, and because the existence of Schottky potential barrier can not suppress floater effect fully.
Summary of the invention
(1) technical problem that will solve
In view of this, main purpose of the present invention is to provide a kind of method that realizes the partial depletion SOI device body contact, to suppress the floater effect of SOI device.
(2) technical scheme
For achieving the above object, technical scheme of the present invention is achieved in that
A kind of method that realizes the contact of part depletion SOI device body, this method comprises:
A, after forming polysilicon gate, carry out body in source electrode one side and draw injection;
B, to the source drain terminal carry out the light dope source region (Lightly Doped Source, LDS) and lightly doped drain (Lightly Doped Drain LDD) injects, and after forming once oxidation thing side wall, the N+ that carries out source-drain area injects, and all forms shallow junction at source-drain area;
C, with photoresist after the source region protection, second time N+ is carried out in the drain region injects so that drain terminal interface arrival oxygen buried layer, asymmetric structure is leaked in the formation source;
D, utilize the silicide of cobalt (Co), penetrate the tagma of source electrode below arriving, clamp down on the tagma current potential, the inhibition floater effect at the cobalt silicide of source electrode one side.
Further comprise before the steps A:
A1, at first go up growth one deck sacrificial oxide layer, carry out twice tuned grid then and inject, form suitable Impurity Distribution at channel region at silicon-on-insulator (SOI);
A2, etch away sacrificial oxide layer, growth grid oxygen, the deposit polysilicon forms polysilicon gate with chemical wet etching then.
For silicon-on-insulator N type metal oxide semiconductor field-effect transistor (SOINMOSFET) device, the described body of steps A is drawn to inject and is comprised:
Shelter drain terminal with photoresist the boron ion that SOI NMOSFET device carries out high dose and energy is injected, be used for below source electrode, forming the P+ district of high concentration.
For silicon-on-insulator P-type mos field-effect transistor (SOIPMOSFET) device, the described body of steps A is drawn to inject and is comprised:
The phosphonium ion that SOI PMOSFET device is carried out high dose and energy injects, and is used for forming below source electrode the N+ district of high concentration.
Described in the step B source drain terminal is carried out further comprising after LDS and the LDD injection: deposit one deck tetraethoxysilane also anti-carves and forms a side wall.
For SOI NMOSFET device, the N+ that carries out source-drain area described in the step B injects and comprises: SOI NMOSFET device is carried out low-energy arsenic ion inject.
For SOI PMOSFET device, the N+ that carries out source-drain area described in the step B injects and comprises: SOI PMOSFET device is carried out low-energy boron ion inject.
Described step D comprises: the certain thickness Co film of deposit, make Co and Si reaction generate silicide, remove unreacted Co on the side wall quarter, carry out rapid thermal treatment then at a certain temperature, the silicide break-through shallow junction in source region and the P+ type silicon below the source region form ohmic contact.
The thickness of described Co film is 30nm; The condition that described Co and Si reaction generates silicide was: 670 ℃ of following rapid thermal treatment 5 seconds; The described quick heat treatment condition of carrying out at a certain temperature was: 800 ℃ of following rapid thermal treatment 10 seconds.
(3) beneficial effect
From technique scheme as can be seen, the present invention has following beneficial effect:
1, the method for this realization partial depletion SOI device body contact provided by the invention, after forming polysilicon gate, carry out the boron ion injection of high dose and energy in source electrode one side, with organizator current paths below source electrode, form the source-drain structure of shallow source knot then, form the silicide of cobalt (Co) then, the cobalt silicide of source electrode one side penetrates source electrode and arrives following tagma, has clamped down on the tagma current potential, thereby has effectively suppressed floater effect.
2, the method for this realization partial depletion SOI device body contact provided by the invention, not only effectively suppressed floater effect, improved the partial depletion SOI device performance, and with standard complementary metal oxide semiconductors (CMOS) (Complementary Metal-Oxide-Semiconductor, CMOS) process compatible, it is simple to have technology, low cost and other advantages.
Description of drawings
Fig. 1 is the method flow diagram of realization partial depletion SOI device body contact provided by the invention;
Fig. 2 is a method flow diagram of realizing the partial depletion SOI device body contact according to the embodiment of the invention;
Fig. 3 is a process flow diagram of realizing the partial depletion SOI device body contact according to the embodiment of the invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
As shown in Figure 1, Fig. 1 is the method flow diagram of realization partial depletion SOI device body contact provided by the invention, and this method may further comprise the steps:
Step 101: after forming polysilicon gate, carry out body in source electrode one side and draw injection;
Step 102: the source drain terminal is carried out LDS and LDD injection, and after forming once oxidation thing side wall, the N+ that carries out source-drain area injects, and all forms shallow junction at source-drain area;
Step 103: with photoresist after the protection of source region, the N+ injection second time is carried out in the drain region, so that the drain terminal interface arrives oxygen buried layer, asymmetric structure is leaked in the formation source;
Step 104: utilize the silicide of cobalt Co, penetrate the tagma of source electrode below arriving, clamp down on the tagma current potential, the inhibition floater effect at the cobalt silicide of source electrode one side.
Based on the method flow diagram of the described realization partial depletion SOI of Fig. 1 device body contact, the present invention is realized that the method for partial depletion SOI device body contact further describes below in conjunction with specific embodiment.
Embodiment
As shown in Figure 2, Fig. 2 is a method flow diagram of realizing the partial depletion SOI device body contact according to the embodiment of the invention, and this method may further comprise the steps:
Step 201: one deck sacrificial oxide layer of at first on SOI, growing, carry out twice tuned grid then and inject, form suitable Impurity Distribution at channel region.Shown in (a) among Fig. 3.
Step 202: etch away sacrificial oxide layer, growth grid oxygen, the deposit polysilicon forms polysilicon gate with chemical wet etching then.Shown in (b) among Fig. 3.
Step 203: shelter drain terminal with photoresist, body is carried out in the source draw injection; Shown in (b) among Fig. 3.
In this step, the boron ion that carries out high dose and energy concerning SOI NMOSFET injects, and is used for forming below source electrode the P+ district of high concentration.The phosphonium ion that carries out high dose and energy concerning SOI PMOSFET injects, and is used for forming below source electrode the N+ district of high concentration.When floater effect took place, the body of this high concentration was drawn the injection region and be can be used as the channel that the few son in tagma flows out.
Step 204: carry out LDD/LDS and inject, shown in (c) among Fig. 3, after forming once oxidation thing side wall, the N+ that carries out source-drain area injects, and all forms shallow junction at source-drain area; Shown in (d) among Fig. 3.
In this step, body is drawn the LDS (Lightly Doped Source) and the LDD (Lightly Doped Drain) that carry out leaking in the source after the injection and is injected, deposit one deck tetraethoxysilane (TEOS) also anti-carves side wall of formation, leaks injection so that carry out following source;
Form the source-drain structure of shallow source knot, promptly carry out low-energy arsenic ion earlier and inject (to SOINMOSFET) or boron ion injection (to SOI PMOSFET).
Step 205: with photoresist after the protection of source region, the N+ injection second time is carried out in the drain region, so that the drain terminal interface arrives oxygen buried layer, asymmetric structure is leaked in the formation source like this; Shown in (e) among Fig. 3.
In this step, when the drain region is carried out that the second time, N+ injected, protect the source region with photoresist, second time carried out in the drain region inject, promptly SOI NMOSFET is carried out that high-octane arsenic ion injects or SOI PMOSFET is carried out high-octane boron ion injection.
Step 206: after the photoresist removal, form secondary oxidation thing side wall, so that form the silicide of cobalt at source-drain area.For the foreign atom that activates injection with repair and inject the lattice damage that causes, 1000 ℃ of following rapid thermal treatment 8 seconds.Shown in (f) among Fig. 3.
Step 207: the silicide that forms cobalt.The Co film that deposit 30nm is thick, 670 ℃ of following rapid thermal treatment after 5 seconds Co and Si reaction generate silicide, remove unreacted Co on the side wall quarter, then 800 ℃ of following rapid thermal treatment 10 seconds, make silicide transfer low resistance state to, because source electrode is a shallow source junction structure, the shallow junction that the silicide in source region is dark with break-through 80nm and P+ type silicon below the source region forms ohmic contact.The silicide thick in the drain region will can not damage Lou-the body knot, this be since for the second time oxide side wall make Lou-body ties away from silicide.Shown in (f) among Fig. 3.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. method that realizes part depletion SOI device body contact is characterized in that this method comprises:
A, after forming polysilicon gate, carry out body in source electrode one side and draw injection;
B, the source drain terminal is carried out light dope source region LDS and lightly doped drain LDD inject, after forming once oxidation thing side wall, the N+ that carries out source-drain area injects, and all forms shallow junction at source-drain area;
C, with photoresist after the source region protection, second time N+ is carried out in the drain region injects so that drain terminal interface arrival oxygen buried layer, asymmetric structure is leaked in the formation source;
D, utilize the silicide of cobalt Co, penetrate the tagma of source electrode below arriving, clamp down on the tagma current potential, the inhibition floater effect at the cobalt silicide of source electrode one side.
2. the method for realization part depletion SOI device body contact according to claim 1 is characterized in that, further comprises before the steps A:
A1, growth one deck sacrificial oxide layer on silicon-on-insulator SOI at first carry out twice tuned grid then and inject, and form suitable Impurity Distribution at channel region;
A2, etch away sacrificial oxide layer, growth grid oxygen, the deposit polysilicon forms polysilicon gate with chemical wet etching then.
3. the method for realization part depletion SOI device body contact according to claim 1 is characterized in that, for silicon-on-insulator N type metal oxide semiconductor field-effect transistor SOI NMOSFET device, the described body of steps A is drawn to inject and comprised:
Shelter drain terminal with photoresist the boron ion that SOI NMOSFET device carries out high dose and energy is injected, be used for below source electrode, forming the P+ district of high concentration.
4. the method for realization part depletion SOI device body contact according to claim 1 is characterized in that, for silicon-on-insulator P-type mos field-effect transistor SOI PMOSFET device, the described body of steps A is drawn to inject and comprised:
The phosphonium ion that SOI PMOSFET device is carried out high dose and energy injects, and is used for forming below source electrode the N+ district of high concentration.
5. the method for realization part depletion SOI device body contact according to claim 1, it is characterized in that described in the step B source drain terminal is carried out further comprising after LDS and the LDD injection: deposit one deck tetraethoxysilane also anti-carves and forms a side wall.
6. the method for realization part depletion SOI device body contact according to claim 1, it is characterized in that, for SOI NMOSFET device, the N+ that carries out source-drain area described in the step B injects and comprises: SOI NMOSFET device is carried out low-energy arsenic ion inject.
7. the method for realization part depletion SOI device body contact according to claim 1, it is characterized in that, for SOI PMOSFET device, the N+ that carries out source-drain area described in the step B injects and comprises: SOI PMOSFET device is carried out low-energy boron ion inject.
8. the method for realization part depletion SOI device body contact according to claim 1 is characterized in that described step D comprises:
The certain thickness Co film of deposit makes Co and Si reaction generate silicide, carves and removes unreacted Co on the side wall, carries out rapid thermal treatment then at a certain temperature, and the silicide break-through shallow junction in source region and the P+ type silicon below the source region form ohmic contact.
9. the method for realization part depletion SOI device body contact according to claim 8 is characterized in that the thickness of described Co film is 30nm; The condition that described Co and Si reaction generates silicide was: 670 ℃ of following rapid thermal treatment 5 seconds; The described quick heat treatment condition of carrying out at a certain temperature was: 800 ℃ of following rapid thermal treatment 10 seconds.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101916726A (en) * | 2010-07-06 | 2010-12-15 | 中国科学院上海微系统与信息技术研究所 | Method for manufacturing signal operation instruction (SOI) metal oxide semiconductor (MOS) apparatus structure for restraining floating body effect |
| CN101950723A (en) * | 2010-07-06 | 2011-01-19 | 中国科学院上海微系统与信息技术研究所 | Method for manufacturing SOI MOS device capable of realizing ohmic contact with source body |
| WO2011091655A1 (en) * | 2010-01-28 | 2011-08-04 | 中国科学院上海微系统与信息技术研究所 | Method for suppressing floating-body effect of soi mos device by ion implantation with high angle |
| CN101989551B (en) * | 2009-08-06 | 2012-01-25 | 中芯国际集成电路制造(上海)有限公司 | Method for forming asymmetrical transistor |
| CN103377901A (en) * | 2012-04-28 | 2013-10-30 | 无锡华润上华科技有限公司 | Polysilicon grid forming method |
| CN103489770A (en) * | 2013-09-22 | 2014-01-01 | 上海华力微电子有限公司 | Grid oxide layer growth method and CMOS tube manufacturing method |
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2007
- 2007-01-24 CN CNA2007100629812A patent/CN101231956A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101989551B (en) * | 2009-08-06 | 2012-01-25 | 中芯国际集成电路制造(上海)有限公司 | Method for forming asymmetrical transistor |
| WO2011091655A1 (en) * | 2010-01-28 | 2011-08-04 | 中国科学院上海微系统与信息技术研究所 | Method for suppressing floating-body effect of soi mos device by ion implantation with high angle |
| CN101916726A (en) * | 2010-07-06 | 2010-12-15 | 中国科学院上海微系统与信息技术研究所 | Method for manufacturing signal operation instruction (SOI) metal oxide semiconductor (MOS) apparatus structure for restraining floating body effect |
| CN101950723A (en) * | 2010-07-06 | 2011-01-19 | 中国科学院上海微系统与信息技术研究所 | Method for manufacturing SOI MOS device capable of realizing ohmic contact with source body |
| CN101916726B (en) * | 2010-07-06 | 2012-10-10 | 中国科学院上海微系统与信息技术研究所 | Method for manufacturing signal operation instruction (SOI) metal oxide semiconductor (MOS) apparatus structure for restraining floating body effect |
| CN103377901A (en) * | 2012-04-28 | 2013-10-30 | 无锡华润上华科技有限公司 | Polysilicon grid forming method |
| CN103489770A (en) * | 2013-09-22 | 2014-01-01 | 上海华力微电子有限公司 | Grid oxide layer growth method and CMOS tube manufacturing method |
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