WO2012006805A1 - Composant mos avec une structure bts et son procédé de fabrication - Google Patents

Composant mos avec une structure bts et son procédé de fabrication Download PDF

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Publication number
WO2012006805A1
WO2012006805A1 PCT/CN2010/076678 CN2010076678W WO2012006805A1 WO 2012006805 A1 WO2012006805 A1 WO 2012006805A1 CN 2010076678 W CN2010076678 W CN 2010076678W WO 2012006805 A1 WO2012006805 A1 WO 2012006805A1
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WO
WIPO (PCT)
Prior art keywords
region
type
heavily doped
silicide
mos device
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PCT/CN2010/076678
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English (en)
Chinese (zh)
Inventor
陈静
罗杰馨
伍青青
黄晓橹
王曦
Original Assignee
中国科学院上海微系统与信息技术研究所
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Application filed by 中国科学院上海微系统与信息技术研究所 filed Critical 中国科学院上海微系统与信息技术研究所
Priority to US13/132,879 priority Critical patent/US8354714B2/en
Publication of WO2012006805A1 publication Critical patent/WO2012006805A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78612—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect

Definitions

  • the present invention relates to a method of fabricating a MOS (Metal O Oxide Semiconductor) structure, and more particularly to an SOI MOS device having an improved BTS structure and a method of fabricating the same, and is a field of semiconductor fabrication technology.
  • MOS Metal O Oxide Semiconductor
  • SOI Silicon l icon On Insula tor
  • Si l icon On Insula tor refers to silicon-on-insulator technology.
  • the device is only fabricated in a thin silicon film, and the device is separated from the substrate by a layer of buried oxide. This structure makes the S0I technology have advantages that are not comparable to bulk silicon.
  • the small parasitic capacitance makes the S0I device high speed and low power consumption.
  • the all-media isolation of SOI CMOS devices completely eliminates the parasitic latch-up effect of bulk silicon CMOS devices.
  • S0I full-medium isolation makes S0I technology highly integrated and resistant to radiation.
  • S0I technology is widely used in radio frequency, high voltage, anti-irradiation and other fields. As device sizes continue to shrink, S0I technology is likely to replace bulk silicon as the first choice for Si technology.
  • the SOI M0S is divided into a partially depleted SOI MOS (PDS0I) and a fully depleted SOI MOS (FDS0I) depending on whether the active body region is depleted.
  • PDS0I partially depleted SOI MOS
  • FDS0I fully depleted SOI MOS
  • the fully depleted SO I M0S top silicon film will be thinner, and the thin film S0I silicon wafer is costly.
  • the fully depleted SOI MOS threshold voltage is not easy to control. Therefore, it is still partially exhausted SO I M0S.
  • the active body region of the partially depleted SOI MOS is not completely depleted, so that the body region is in a floating state, and the charge generated by the impact ionization cannot be quickly removed, which results in a unique floating body effect of the SOI MOS.
  • SOI wake OS channel electrons at the drain end impact ionization generated electron-hole pairs, holes flow to the body region, SOI M0S floating body effect causes holes to accumulate in the body region, thereby raising the body potential, making SOI ⁇ OS
  • the decrease in the threshold voltage and the increase in the leakage current cause the device's output characteristic curve I d Vd to warp. This phenomenon is called the Kink effect.
  • the Kink effect has many adverse effects on device and circuit performance and reliability, and should be suppressed as much as possible during device design.
  • SOI PM0S due to the low ionization rate of holes, the electricity generated by impact ionization The sub-hole pairs are much lower than SOI NM0S, so the Kink effect in SOI PM0S is not obvious.
  • the body contact is usually connected to a fixed potential (source or ground) by means of a body contact, as shown in Figure la-lb, for a conventional T-gate structure.
  • the P + implant region formed at one end of the T-gate is connected to the P-type body region under the gate.
  • the carriers accumulated in the body region are vented through the P + channel to reduce the potential of the body region.
  • the effect is to complicate the process, increase parasitic effects, reduce part of the electrical performance and increase the device area.
  • a BTS (Body-Tied-to-Source) structure has been proposed, that is, a source end body extraction structure.
  • the BTS structure can effectively suppress the floating body effect and does not increase the chip area, but the BTS structure makes the MOS device asymmetrical, and another disadvantage is that the existing BTS structure can reduce the effective channel width of the device.
  • the present invention proposes an improved BTS structure based on the existing BTS structure, and the novel BTS structure can effectively suppress the floating body effect of the SOI MOS device without reducing
  • the effective channel width of the device makes the process simple and compatible with integrated circuit processes.
  • the present invention uses the following technical solutions:
  • An SOI MOS device having a BTS structure, comprising: a substrate, an insulating buried layer over the substrate, an active region over the buried insulating layer, and a shallow region around the active region Trench isolation structure;
  • the active region includes: a gate region, a body region under the gate region, an N-type source region and an N-type drain region at both ends of the body region; and a sidewall spacer structure around the gate region ;
  • the N-type source region includes: two heavily doped N-type regions, a heavily doped P-type region between the two heavily doped N-type regions, and the two heavily doped N-type regions and a silicide overlying and in contact with the P-type regions, and a shallow N-type region connected to the silicide; the heavily doped P-type region and the two heavily doped N-type regions,
  • the shallow trench isolation structure, the body region, and the silicide thereon are in contact.
  • the silicide is selected from the group consisting of cobalt silicide and titanium silicide.
  • the body region is made of a P-type Si material.
  • the insulating buried layer is made of silicon oxide or silicon nitride material.
  • a method for fabricating an SOI MOS device having a BTS structure includes the following steps:
  • Step 1 forming a shallow trench isolation structure on the Si material having an insulating buried layer, isolating part of the Si material, and forming a gate region on the portion of the Si material;
  • Step 2 performing light doping in the source region and light doping in the drain region to form a lightly doped N-type source region and a lightly doped N-type drain region;
  • Step 3 fabricating a sidewall spacer structure around the gate region, the sidewall spacer structure covering a surface of the lightly doped N-type source region and the lightly doped N-type drain region, and then performing ion implantation in the source region and the drain region.
  • Step 4 by ion implantation, ions are implanted downward from the surface of the N-type Si material source region which is not covered by the sidewall spacer structure, and is heavily doped Forming a heavily doped P-type region in the middle of the N-type region, the heavily doped P-type region dividing the heavily doped N-type region into two heavily doped N-type regions;
  • Step 5 forming a layer of metal on the surface of the heavily doped P-type region and the two heavily doped N-type regions, and then reacting the metal with the underlying Si material to form a silicide by heat treatment, so that the silicide is
  • the heavily doped P-type region and the two heavily doped N-type regions are in contact, and the generated silicide and the heavily doped P-type region, the two heavily doped N-type regions, and the shallow N-type region constitute an N-type source region, and are finally completed.
  • M0S device structure M0S device structure.
  • step 1 P ion implantation is performed on the isolated portion of the Si material before the gate region is formed.
  • the light doping and the light-drain doping dose of the source region are on the order of le 5 /cm 2 , and the concentrations of the lightly doped N-type source region and the lightly doped N-type drain region are On the order of 19 / cm 3 .
  • a mask is provided at a position in the middle of the heavily doped N-type region, and the mask is aligned with the edge of the sidewall spacer structure, and is vertically doped via the mask. P ions are implanted to form a heavily doped P-type region.
  • the metal is selected from one of Co and Ti; the heat treatment is performed by a furnace tube annealing process; the heat treatment temperature is 700-900 ° C, and the time is 50-70 seconds.
  • the SOI MOS device with BTS structure disclosed in the present invention and the manufacturing method thereof have the beneficial effects that: the SOI MOS device has an improved BTS structure, and the heavily doped N-type region of the source region is divided into two, heavily doped The P-type region is located between them and is provided with silicide thereon. The heavily doped P-type region forms an ohmic contact with the silicide thereon, releasing holes accumulated in the body region of the SOI MOS device, thereby suppressing the floating body effect of the SO I MOS device.
  • the silicide also covers the two heavily doped N-type regions of the source region, so that the invention can effectively suppress the floating body effect without increasing the chip area, thereby eliminating the disadvantage that the conventional BTS structure reduces the effective channel width. Its manufacturing process is simple and compatible with conventional CMOS processes.
  • FIG. 1a is a schematic top view of a MOS structure for suppressing a floating body effect by a body contact method in the background art
  • FIG. 1b is a schematic cross-sectional view of a MOS structure for suppressing a floating body effect by a body contact method in the background art
  • FIGS. 2a-2d are diagrams of the present invention
  • Schematic diagram of a SOI MOS device having a BTS structure FIG. 2a is a top view
  • FIGS. 2b, 2c, and 2d are cross-sectional views of AA, BB, and CC in FIG. 2a, respectively, wherein FIG. 2a is not silicified for convenience of illustration.
  • 3a-3f are schematic diagrams showing the process flow for fabricating a MOS device structure using the method of the present invention.
  • an SOI MOS device having a BTS structure of the present invention includes: a substrate 10, an insulating buried layer 20 over the substrate 10, and an active region above the insulating buried layer 20. And a shallow trench isolation (STI) structure 30 located around the active region;
  • STI shallow trench isolation
  • the active region includes: a gate region, a body region 70 under the gate region, an N-type source region and an N-type drain region 40 at both ends of the body region 70, the N-type source region and the N-type
  • the drain regions 40 are respectively located on both sides of the gate region;
  • the N-type source region includes: two heavily doped N-type regions 52, 53, a heavily doped P-type region 60 between the two heavily doped N-type regions 52, 53, located in the two a silicide 51 overlying and in contact with the heavily doped N-type regions 52, 53 and the heavily doped P-type region 60, and a shallow N-type region 54 connected to the silicide 51; the heavily doped P Pattern 60 and the two heavily doped N-type regions 52, 53 and shallow trench isolation junction
  • the structure 30 and the body region 70 are in contact with each other and form an ohmic contact with the silicide 51 thereon.
  • the gate region includes a gate dielectric layer 81 and a gate electrode 82 on the gate dielectric layer 81.
  • a sidewall spacer structure 90 is also disposed around the gate region.
  • the active area is mainly made of S i material.
  • a P-type S i material can be used in the body region 70.
  • the N-type drain region 40 uses an N-type S i material.
  • the insulating buried layer 20 may be made of a silicon dioxide or silicon nitride material. In a specific example of the present invention, silicon dioxide may be used, that is, a buried oxide layer (BOX).
  • the silicide 51 can be any conductive silicide (eg, cobalt silicide, titanium silicide) that can form an ohmic contact with the underlying heavily doped P-type region 60 for releasing holes accumulated in the body region of the SOI MOS device. Thereby suppressing the floating body effect of the SO I MOS device. And the silicide 51 also covers the two heavily doped N-type regions 52, 53 of the source region, so that the present invention can effectively suppress the floating body effect without increasing the chip area, eliminating the traditional BTS structure and reducing the effective channel width. Disadvantages. Since the Kink effect due to the floating body effect is not obvious in the SOI PM0S, the solution of the present invention is mainly directed to the SOI RIS OS device.
  • conductive silicide eg, cobalt silicide, titanium silicide
  • the method for fabricating the SOI MOS device having the BTS structure described above, as shown in FIGS. 3a-3f, includes the following steps:
  • Step 1 as shown in FIG. 3a, a shallow trench isolation structure 30 is formed on the Si material (S0I) having the insulating buried layer 20, a portion of the Si material 700 is isolated, and a gate region is formed on the portion of the Si material 700. That is, a gate dielectric layer 81 and a gate electrode 82 are sequentially formed on the portion of the Si material 700.
  • the gate electrode 82 can be made of a polysilicon material. P-ion implantation of the active region can be performed to adjust the threshold voltage before the gate region is formed.
  • Step 2 As shown in FIG. 3b, a higher dose source region light doping (LDS) and a drain region light doping (LDD) are performed.
  • LDD source region light doping
  • LDD drain region light doping
  • the difference from the conventional LDD/LDS is:
  • the lightly doped source-drain N-type implant dose reaches the order of Iel 5/cm2, so it can be called a highly doped source drain, thus forming a lightly doped N-type source region 500 and a lightly doped N-type drain.
  • Zones 400 have a higher doping concentration and their actual concentrations reach Iel 9/cm3.
  • this process still cites the name LDD/LDS that the industry has been using.
  • Step 3 As shown in FIG. 3c, a spacer spacer 90 is formed around the gate region by using a material such as silicon oxide or silicon nitride.
  • the spacer spacer 90 is lightly doped with an N-type source region 500 and lightly doped. Part of the surface of the hetero-N-type drain region 400 is covered.
  • source and drain ion implantation is performed to form an N-type Si material source region 50 and an N-type drain region 40, and a body is formed between the N-type Si material source region 50 and the N-type drain region 40.
  • the N-type Si material source region 50 is composed of a shallow N-type region under the sidewall spacer structure 90 and a heavily doped N-type region.
  • Step 4 as shown in FIG. 2d, by ion implantation, ions are implanted downward from the surface of the N-type Si source region 50 that is not covered by the spacer spacer 90, and a heavy is formed in the middle of the heavily doped N-type region.
  • a P-type region 60 is doped that divides the heavily doped N-type region into two heavily doped N-type regions 52, 53 as shown in Figure 3e.
  • the step may employ a mask having an opening at a position in the middle of the heavily doped N-type region, and the opening is aligned with the edge of the spacer spacer 90, via the mask.
  • the plate is vertically doped with P-ion implantation to form a heavily doped P-type region 60.
  • Step 5 forming a layer of metal on the surface of the heavily doped P-type region 60 and the two heavily doped N-type regions 52, 53, , for example, Co, Ti, and then reacting the metal with the underlying Si material by heat treatment to form a silicide 51, the silicide 51 and the heavily doped P-type region 60 and the two heavily doped N-type regions 52, The 53 contact, the generated silicide 51 and the heavily doped P-type region 60, the two heavily doped N-type regions 52, 53 and the shallow N-type region 54 constitute an N-type source region, and finally the MOS device as shown in FIG. 3f is completed. structure.
  • the heat treatment may employ a furnace tube annealing process; the temperature is 700-900 ° C, preferably 800 ° C, and the time is 50-70 seconds, preferably 1 minute.
  • the silicide 51 formed by the reaction of Co with S i is cobalt silicide, and Ti reacts with S i to form titanium silicide.
  • the fabricated MOS device structure is processed by a subsequent semiconductor process to obtain a complete MOS device.
  • the manufacturing process is simple and compatible with conventional CMOS processes.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)

Abstract

L'invention concerne un composant semi-conducteur à oxyde métallique du type silicium sur isolant (MOS SOI) avec une structure de corps lié à la source (BTS), et son procédé de fabrication. La région de source du composant MOS SOI comporte deux régions de type N fortement dopées (52, 53), une région de type P fortement dopée (60) entre les deux régions de type N (52, 53), des siliciures (51) par-dessus les deux régions de type N fortement dopées (52, 53) et la région de type P fortement dopée (60), et une région de type N superficielle (54) reliée aux siliciures (51). La région de type P fortement dopée (60) et les siliciures (51) la recouvrant forment un contact ohmique, les trous accumulés dans la région de corps du composant MOS SOI sont libérés, l'effet de corps flottant du composant MOS SOI peut ainsi être efficacement limité, la surface de puce n'est pas augmentée, et le défaut de réduction de la largeur effective de canal par une structure BTS traditionnelle est supprimé. La région de type P fortement dopée est formée par un procédé d'implantation ionique, puis une couche de métal est formée à la surface de la région de source, et un traitement thermique fait réagir le métal avec le silicium situé en dessous pour générer des siliciures.
PCT/CN2010/076678 2010-07-13 2010-09-07 Composant mos avec une structure bts et son procédé de fabrication WO2012006805A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/132,879 US8354714B2 (en) 2010-07-13 2010-09-07 SOI MOS device having BTS structure and manufacturing method thereof

Applications Claiming Priority (2)

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CN201010225623.0A CN101916776B (zh) 2010-07-13 2010-07-13 具有bts结构的soimos器件及其制作方法
CN201010225623.0 2010-07-13

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103094178A (zh) * 2013-01-16 2013-05-08 中国科学院上海微系统与信息技术研究所 提高部分耗尽型soi器件射频性能的制备方法

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102208449B (zh) * 2011-05-24 2016-03-09 上海华虹宏力半导体制造有限公司 一种soi体接触mos晶体管及其形成方法
CN103681343B (zh) * 2012-09-25 2016-03-23 中国科学院微电子研究所 一种半导体结构的制造方法
US9741857B2 (en) * 2015-08-07 2017-08-22 Ahmad Tarakji Approach for an area-efficient and scalable CMOS performance based on advanced Silicon-On-Insulator (SOI), Silicon-On-Sapphire (SOS) and Silicon-On-Nothing (SON) technologies
CN106952954B (zh) * 2016-01-07 2020-11-13 中国科学院上海微系统与信息技术研究所 一种soi mos器件及其制作方法
CN106952953A (zh) * 2016-01-07 2017-07-14 中国科学院上海微系统与信息技术研究所 一种抗总剂量效应的soi mos器件及其制作方法
CN107516676B (zh) * 2016-06-17 2022-05-17 中国科学院上海微系统与信息技术研究所 一种基于soi的mos器件结构及其制作方法
CN111370310B (zh) * 2018-12-26 2022-10-18 中芯集成电路（宁波）有限公司 半导体结构及其形成方法

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US20030025159A1 (en) * 2001-06-27 2003-02-06 Michiru Hogyoku Semiconductor devices
CN101515586A (zh) * 2008-02-21 2009-08-26 中国科学院微电子研究所 具有紧密体接触的射频soi ldmos器件

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JP2870635B2 (ja) * 1997-04-17 1999-03-17 日本電気株式会社 半導体装置
US7601569B2 (en) * 2007-06-12 2009-10-13 International Business Machines Corporation Partially depleted SOI field effect transistor having a metallized source side halo region

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US20030025159A1 (en) * 2001-06-27 2003-02-06 Michiru Hogyoku Semiconductor devices
CN101515586A (zh) * 2008-02-21 2009-08-26 中国科学院微电子研究所 具有紧密体接触的射频soi ldmos器件

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103094178A (zh) * 2013-01-16 2013-05-08 中国科学院上海微系统与信息技术研究所 提高部分耗尽型soi器件射频性能的制备方法

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