WO2011150750A1 - 包含电阻器的存储单元的制造方法 - Google Patents

包含电阻器的存储单元的制造方法 Download PDF

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Publication number
WO2011150750A1
WO2011150750A1 PCT/CN2011/074323 CN2011074323W WO2011150750A1 WO 2011150750 A1 WO2011150750 A1 WO 2011150750A1 CN 2011074323 W CN2011074323 W CN 2011074323W WO 2011150750 A1 WO2011150750 A1 WO 2011150750A1
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metal
layer
precursor
electrode layer
resistive material
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PCT/CN2011/074323
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English (en)
French (fr)
Inventor
刘力锋
康晋锋
郝跃
刘晓彦
陈沅沙
高滨
王漪
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北京大学
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Publication of WO2011150750A1 publication Critical patent/WO2011150750A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H10N70/023—Formation of switching materials, e.g. deposition of layers by chemical vapor deposition, e.g. MOCVD, ALD
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites

Definitions

  • the present invention relates to a method of fabricating a memory cell including a resistor, and more particularly to metal/oxide/metal
  • MOM resistive random access memory
  • CM0CVD metal organic chemical vapor deposition
  • Non-volatile memory has the advantage of retaining data information when there is no power supply, and has a very important position in the field of information storage. It is also one of the research hotspots of current information storage technology. However, today's mainstream non-volatile memory-flash has problems such as high operating voltage, slow speed, and poor endurance.
  • RRAM has been shown to be a powerful candidate for next-generation semiconductor memories due to its fast speed, high memory density, long data retention time and long-lasting power.
  • the basic memory cell of the RRAM consists of a metal (M) insulator (I) metal (M) sandwich structure resistor with two layers of metal acting as the top and bottom electrodes, respectively.
  • the resistance of the MIM resistor can be switched between high and low resistance states for data writing and erasing.
  • the key to RRAM operation is the resistance transition and memory effect of the MM resistor.
  • the resistance of the resistor can undergo a reversible, large change under voltage or current.
  • metal materials include platinum (Pt), aluminum (Al), titanium nitride (TiN), etc.
  • the insulator materials mainly include various oxide materials and solid electrolyte materials. Since the oxide material has good compatibility with the semiconductor process, the MOM structure has become the focus of research.
  • the RRAM memory cell MOM structure is manufactured by using a sputtering or evaporation method for the top electrode and the bottom electrode, and the oxide material is generally produced by reactive sputtering or atomic layer deposition.
  • M0CVD metal organic chemical vapor deposition
  • the interfacial properties between the metal and oxide materials have an important influence on the resistive properties of the RRAM.
  • the resistance characteristics between a plurality of RRAM devices formed on the same substrate may vary greatly due to interface non-uniformity between the metal and the oxide material due to process variations. .
  • the generation and distribution characteristics of oxygen vacancy defects in oxide materials are closely related to the RRAM resistive switching characteristics.
  • the oxide RRAM can be significantly improved by the miscibility of the oxide metal to change the characteristics of the oxygen vacancies.
  • the resistance switch characteristics, element doping has become an important way to improve the RRAM resistance performance.
  • the above prior art methods are difficult to achieve effective control and adjustment of the characteristics of oxygen vacancies.
  • An object of the present invention is to provide a M0CVD manufacturing method of an RRAM memory cell of a MOM structure which can be integrated at a high density.
  • a method of fabricating a memory cell including a resistor comprising the steps of: a) forming a bottom electrode layer on an insulating substrate; b) forming a resistive material layer on the bottom electrode layer by MOCVD; c) Forming a top electrode layer on the resistive material; and d) patterning the top electrode layer and the resistive material layer to form separate memory cells.
  • M0CVD Compared with sputtering and atomic layer deposition, M0CVD has the advantages of precise control of thickness, composition and doping concentration, and relatively fast growth rate. At the same time, M0CVD also has good step coverage and void filling ability, suitable for large-scale processes. machining. The M0CVD film also has the characteristics of high growth quality and uniform film layer, and an ultra-thin film structure can be obtained.
  • An advantage of the present invention is that a resistive material layer having a thickness, a precisely controlled composition, and a good uniformity can be produced by the M0CVD method, whereby a memory cell of an RRAM of a MOM structure excellent in interface characteristics can be obtained.
  • the use of metal ion doping and/or annealing deoxygenation can create oxygen vacancies in the resistive material layer, thereby significantly improving the resistive switching characteristics of the memory cell.
  • FIG. 1-5 are cross-sectional views showing stages of a method of fabricating a memory cell including a resistor in accordance with the present invention.
  • Figure 6 is a schematic view of a M0CVD apparatus used in the present invention. detailed description
  • various portions of the semiconductor device may be constructed of materials well known to those skilled in the art.
  • the inventors have proposed a method of manufacturing a memory cell of a MOM structure using M0CVD technology.
  • the method includes the steps that are performed sequentially in the following order.
  • the insulating substrate may be a laminated substrate in which the surface layer is an oxide layer.
  • the insulating substrate is a laminated substrate including a single crystal Si base 10 and a SiO 2 layer 11.
  • a part of the single crystal Si underlayer 10 can be converted into Si0 2 by thermal oxidation.
  • the SiO 2 layer 11 is formed on the single crystal Si underlayer 10.
  • a Ti layer 12 is formed as an adhesion layer on the SiO 2 layer 11 by sputtering or evaporation, and then a bottom electrode layer 13 (e.g., Pt) is formed on the Ti layer 12 by sputtering, evaporation, or MOCVD.
  • a bottom electrode layer 13 e.g., Pt
  • the Ti layer 12 is an optional layer mainly used to improve the adhesion strength of the bottom electrode layer 13 on the substrate.
  • the process flow for manufacturing Pt film by M0CVD method is as follows:
  • the substrate temperature is maintained at 200-700 ⁇ ;
  • a resistive material layer 14 is formed on the bottom electrode layer 13 by M0CVD.
  • the composition of the resistive material layer is expressed as (M' X MV X ) admir ⁇ 3 ⁇ , where M Nb, Ta, V, Hf, Zr, Ti, Ce, Sr, Mg, La, Gd, Al, Mn, Pb, a metal of Ba, Ni, Zn, Co, Mo, Fe, Cu, W, Mn, and Cr.
  • M 2 is Nb, Ta, V, Hf, Zr, Ti, Ce, Sr, Mg, La, Gd, a metal different from M 1 among Al, Mn, Sr, Pb, Ba, Ni, Zn, Co, Mo, Fe, Cu, W, Mn, and Cr.
  • M 3 is Mn, Ti, Zr, Ce, Fe a metal of Hf, Al, and Ta. wherein x is 0 1 ; n is 1, 2, or 3, and y is 0, 1 Or 2, z is 1 7.
  • the oxide can be a quaternary oxide such as La. 5 Sr. 5 Mn0 3 , corresponding to M' is La, M 2 is Sr, M 3 is Mn, X is 0.5, n is 1, y is 1, and z is 3.
  • the oxide material may also be a ternary oxide such as SrZr0 3 , corresponding to M' being Sr, M : i being Zr, x being 1, n being 1, y being 1, and z being 3.
  • the oxide may also be a binary oxide, for example, corresponding to M' being Hf, X being 1, n being 1, y being 0, and z being 2.
  • the oxide can also be doped, such as Hf. 97 A1. . 3 0 2 is A1 doped Hf0 2 .
  • a fourth metal M' 1 can also be added to the oxide as a dopant, and its chemical formula is M' X M 2 X , M" , M 3 y 0 z , and M 4 is selected from a lower valence state of the metal ion to be replaced.
  • Metal elements such as Ca miscellaneous L 5 Sr. 5 Mn0 3 , A1 or La miscellaneous Hf0 2 .
  • z is a decimal, it means that the oxide material is deficient in oxygen, which is a non-chemically proportioned oxide material, such as HfO l 7 , z is 1.7, and cerium oxide is in anoxic state.
  • the process flow for manufacturing a resistive material layer by the M0CVD method is as follows:
  • the substrate temperature is maintained at 200-700 ° C;
  • the metal precursors of M', M 2 and M 3 may be alkoxide precursors, metal diketone precursors or metal carbonyl precursors.
  • the alkoxide precursor has the chemical formula M (OR)•, wherein M is a metal of Nb, Ta, Hf, Zr, Ti, W, La and Al; 0 is oxygen; R is an alkyl group, including C 2 3 ⁇ 4, CH ( CH 3 ) 2 , etc., n is 3 or 4.
  • the alkoxide precursor of V (vanadium) has the chemical formula V0 ( OR ) 3 .
  • the chemical formula of the metal- ⁇ -diketone precursor is MC tmhd ) reckon, where M is A metal in Hf, Zr, Ti, Ce, Sr, Mg, La, Gd, Mn, Pb, Ba, Ni, Zn, Co, Mo, Fe, Cu, Mn, and Cr, and n is a valence of the M metal.
  • the metal carbonyl precursor has the formula M (CO) discipline, where M is a metal of Co, Ni, Fe, Cr and W, C is carbon, 0 is oxygen, and n is 3, 4, 5 or 6.
  • the above precursors can be used in a solid form or in a liquid form.
  • the solid or liquid precursor is dissolved in an organic hydrocarbon solvent such as octane, isopropanol or the like to form a liquid precursor.
  • the evaporated liquid precursor is passed into the reaction deposition chamber using a carrier gas such as Ar 2 .
  • the solid precursor can also be passed into the reaction deposition chamber with a carrier gas after sublimation. As is known to those skilled in the art, evaporation of the liquid precursor and sublimation of the solid precursor need to be carried out at an appropriate temperature.
  • a reaction gas such as oxygen, nitrogen oxide, or the like is introduced into the reaction deposition chamber, or a gas component can be partially introduced into the deposition.
  • gases of the film cause the metal precursor of the reaction deposition chamber and oxygen to react on the surface of the substrate to obtain a resistive material. Material layer.
  • Annealing is then carried out under vacuum or a hydrogen-containing atmosphere to deoxidize the resistive material layer to obtain a non-chemically proportioned resistive material layer in an oxygen-deficient state.
  • the conditions in which the resistive material layer is annealed in situ in a hydrogen-containing atmosphere are, for example, an annealing treatment in a hydrogen-containing atmosphere, a gas pressure lower than one atmosphere, and an annealing temperature of 300 800 °C.
  • the hydrogen-containing atmosphere is hydrogen or a mixed atmosphere of hydrogen and nitrogen or an inert gas, wherein the volume of hydrogen in the mixed atmosphere is 5-100%.
  • the condition that the resistive material layer is annealed in situ under vacuum conditions is: annealing under vacuum conditions, a vacuum of 10 - 3 Pa, and an annealing temperature of 300 - 900 °C.
  • oxygen vacancies can be generated in the oxide by metal ion doping.
  • Metal ion doping and annealing deoxidation may be used alone or in combination.
  • Ion-doped precursors are required for metal ion doping, while annealing deoxygenation does not require the use of any precursor.
  • the metal as a dopant should be lower in valence than the metal ion to be replaced.
  • doping +3 valence Gd 3+ in Hf0 2 material since Hf is +4 valence, after every 2 Gd 3+ replacing 2 Hf 4+ , an oxygen vacancy will be generated.
  • a non-stoichiometric hypoxic state of Gd s Hf 1-x 0 z , where z is a fraction between 1 and 2 is formed.
  • a top electrode layer 15 (e.g., Pt or Ti N) is formed on the resistive material layer 14 by sputtering, evaporation, or MOCVD.
  • the method of manufacturing the Pt film is the same as that described in connection with Fig. 2.
  • the process steps for fabricating the TiN film are -
  • the substrate temperature is maintained at 300-50 (TC;
  • TDMA tetramethylammonium titanium
  • the top electrode layer 15 and the resistive material layer 14 are patterned to form a top electrode pattern to form spaced apart memory cells.
  • the patterning may include the steps of: forming a patterned photoresist mask on the top electrode layer 15 by a photolithography process including exposure and development; by thousand etching, such as ion milling, plasma etching, reactive ions Etching, laser ablation, or removal of the exposed portions of the top electrode layer 15 and the resistive material layer 14 by wet etching using an etchant solution, the etching step is stopped at the top of the bottom electrode layer 13; by dissolving in a solvent Or ashing to remove the photoresist mask.
  • the Pt film can be etched by inductively coupled plasma (ICP), and the TiN film can be etched by inductively coupled plasma (ICP) or reactive ion etching (RIE).
  • ICP inductively coupled plasma
  • RIE reactive ion etching
  • the resistive material layer is etched by inductively coupled plasma (ICP) or reactive ion etching (RIE), or the resistive material layer is etched by wet etching.
  • Each of the mutually spaced electrode regions in the pattern of the top electrode layer 15 corresponds to a memory cell of the RRAM.
  • the insulating material is filled in the trenches between the electrode regions to form an isolation structure similar to shallow trench isolation, completing the fabrication of the RRAM memory cell.
  • the bottom electrode and the top electrode of the RRAM memory cell can be taken out as electrodes, and various electrical performance tests such as resistance switching characteristics and holding characteristics are performed.
  • FIG. 1 A schematic diagram of a MOSCVD apparatus employed in a method of fabricating a memory cell including a resistor according to the present invention is shown in FIG.
  • the substrate 107 is mounted on the tray 104 by the robot 106, and the reaction chamber is evacuated to a set vacuum by the vacuum pump unit 105.
  • the substrate 107 is heated to a set temperature by the resistance heating device 102.
  • the precursor gas is passed from the top of the reaction chamber to the reaction chamber 101 through a carrier gas such as Ar 2 and flows to the substrate 107.
  • the reaction gas flows from the side wall into the reaction chamber 101 and flows to the substrate 107.
  • the reaction chamber is maintained at a certain pressure range by adjusting the flow rate of the precursor and the reaction gas.
  • a plasma generating device 100 is disposed in the reaction chamber, and a voltage is applied to the positive and negative electrodes 103, 104, respectively.
  • the precursor gas forms a plasma under the action of a radio frequency electric field between the positive and negative electrodes 103, 104, and reacts on the surface of the substrate 107.
  • the gas reacts to form the desired film.
  • the plasma generating apparatus 100 can transfer the precursor gas to the substrate in the form of a plasma. Since the precursor has a certain amount of energy, this can lower the temperature of the M0CVD reaction and increase the deposition rate.
  • the resistance heating device 102 can adjust the temperature of the reaction substrate.
  • Example 1 An RRAM memory cell in which a Si/SiO 2 /Ti/Pt/Hf0 2 /TiN structure was fabricated by a M0CVD method, a SiO 2 insulating layer was formed by thermal oxidation of a Si crystal, and a Ti film was formed on Si/SiO 2 by a sputtering method.
  • the Si/Si0 2 /Ti structure was placed in a M0CVD reaction chamber.
  • a Pt metal bottom electrode was fabricated. Sublimation of acetylacetone platinum solid as a precursor at 150 ° C to form platinum gas of acetylacetonate, using Ar 2 as a carrier gas into the reaction chamber, 0 2 as a reaction gas into the reaction chamber, substrate temperature The Pt film was formed on the Si/SiO 2 /Ti substrate while maintaining the pressure in the reaction chamber at 100 ° C to obtain a Si/SiO 2 /Ti/Pt structure.
  • Hf ( 0C 2 H 5 ) alkoxide solid was used as a precursor, dissolved in isopropanol to form a liquid precursor, which was evaporated under 150 ⁇ under LOP to form Hf( 0C 2 H 5 ) 4 gas, using Ar 2 as a carrier. Passing into the reaction chamber, introducing oxygen into the reaction gas, maintaining the substrate temperature at 400 ⁇ , and the reaction chamber pressure at 200 Pa, reacting on Si/Si0 2 /Ti/Pt to form Hf0 2 film, and obtaining Si/Si0 2 /Ti/Pt /Hf0 2 structure.
  • TDMA thermally decomposes on the surface of the substrate to form a TiN (C, H) film.
  • the TiN (C, H) film was then plasma treated in situ using a 13 ⁇ 4/plasma to obtain a TiN film.
  • the reaction deposition and plasma treatment were repeated to finally obtain a TiN film of a suitable thickness to obtain a Si/SiO 2 /Ti/Pt/Hf0 2 /TiN structure.
  • a top electrode pattern having an area of 50 ⁇ 50 ⁇ m 2 was formed by spin coating and photolithography using a photoresist as a mask layer. Then, the TiN and Hf0 2 thin films were continuously etched by means of ICP.
  • the ICP conditions were as follows using Cl 2 as a reaction gas, the power was 30/200 W, and the reaction gas pressure was 3 mT. The reactive etching stops to the Pt metal layer. The rate at which Cl 2 etches the Pt metal layer is low, and Pt can serve as an etch stop layer.
  • the photoresist is removed by plasma dry method to complete the fabrication of the RRAM memory cell of Si/Si0 2 /Ti/Pt/Hf0 2 /TiN structure.
  • Example 2 Si/SiO 2 /Ti/Pt/Zr was produced by the M0CVD method. 99 La. .
  • the RRAM memory cell of the A/Pt structure is thermally oxidized by Si crystal to produce a SiO 2 insulating layer, a Ti film is formed on Si/SiO 2 by an evaporation method, and a Si/SiO 2 /Ti structure is placed in a MOCVD chamber.
  • a Pt metal bottom electrode was fabricated.
  • the acetylacetone platinum solid was used as a precursor to sublimate at 15 CTC to form acetylacetone platinum gas, and 1: 2 was used as a carrier gas to pass into the reaction chamber.
  • Oxygen was introduced into the reaction chamber as a reaction gas, and the substrate temperature was maintained at 500 ° C.
  • a Pt film was formed on the Si/SiO 2 substrate to obtain a Si/SiO 2 /Ti/Pt structure.
  • the amount of the two precursors is calculated according to the molar ratio of Zr and La and the average velocity of the two metal depositions, and together dissolve a certain amount of symplectic In the alkane, a liquid precursor having a certain concentration is formed, and a precursor gas is evaporated under 200 ⁇ under lOPa, and Ar 2 is used as a carrier to pass into the reaction chamber, oxygen of the reaction gas is introduced, and the substrate temperature is maintained at 400 ° C.
  • the gas pressure is at 100 Pa, and it is reacted on Si/Si0 2 /Ti/Pt to form a Zr 0 99 La ⁇ ,0 2 film, and Si/Si0 2 /Ti/Pt/Zr is obtained. 99 1 ⁇ , 0 2 structure.
  • acetylacetone platinum solid as a precursor, sublimation at 150 ⁇ to form acetylacetone platinum gas, using Ar 2
  • oxygen is introduced into the reaction chamber as a reaction gas
  • the substrate temperature is maintained at 400 ° C
  • the reaction chamber pressure is 100 Pa at Si/Si 2 2 /Ti/Pt/Zr.
  • a pt film is formed on the structure of e9 L 3 ⁇ 4 ()1 0 2 to obtain Si/Si0 2 /Ti/Pt/Zr. 99 La threading, 0 2 /Pt structure.
  • a top electrode pattern having an area of ⁇ ⁇ ⁇ ⁇ ⁇ 2 was produced by spin coating and photolithography, using a photoresist as a mask layer. Then, the Pt film was etched by the ICP method, and the ICP condition was that Cl 2 was used as the reaction gas, the power was 50/300 W, and the reaction gas pressure was 5 mT. The Pt etching time is obtained according to the etching rate. After the Pt top electrode is etched, the etching conditions are changed, and Zro ⁇ La ⁇ Ck is further etched until the Pt metal layer stops. The etching conditions were such that Cl 2 was used as a reaction gas, the power was 30/200 W, and the reaction gas pressure was 3 mT. (1 2 The rate of etching the Pt metal layer is low, and Pt can be used as an etch stop layer.
  • the photoresist is removed by plasma dry method to complete the fabrication of the RRAM memory cell of Si/SiCVTi/Pt/Zr ⁇ La ⁇ CyPt structure.
  • Example 3 Fabrication of an RRAM memory cell of Si/Si0 2 /Ti/Pt/Ti0 2 ( Kz ⁇ 2 ) /TiN structure by M0CVD
  • a Si0 2 insulating layer was formed by a CVD method on a Si crystal, a Ti thin film was formed on Si/SiO 2 by a sputtering method, and a Si/SiO 2 /Ti structure was placed in a MOCVD chamber.
  • a Pt metal bottom electrode was fabricated.
  • the acetylacetone platinum solid was used as a precursor to sublimate at 15 CTC to form acetylacetonate platinum gas.
  • Ar 2 was used as a carrier gas to pass into the reaction chamber.
  • Oxygen was introduced into the reaction chamber as a reaction gas.
  • the substrate temperature was maintained at 400 ⁇ and the reaction chamber pressure was at 100 Pa.
  • a Pt film was formed on the Si/Si0 2 substrate to obtain a Si/SiO 2 /Ti/Pt structure.
  • Ti (0C 2 H 5) was dissolved in isopropanol, to form a liquid precursor, the precursor gas formed by evaporation in the lOPa 150 ° C, using Ar ⁇ f as a carrier into the reaction chamber, the reaction gas is introduced into 02
  • the substrate temperature was maintained at 400 ° C
  • the reaction chamber pressure was at 100 Pa
  • the Ti 2 2 film was formed on Si/Si 2 2 /Ti/Pt.
  • the Ti0 2 film was annealed in a hydrogen-containing atmosphere / (volume ratio 9/1) at a temperature of 600 ° C and a gas pressure of 1 atm for 1 hour to obtain a Ti z z ( Kz ⁇ 2 ) film to form Si/Si 2 2 /Ti. /Pt/Ti0 z ( Kz ⁇ 2 ) structure.
  • tetramethylammonium titanium TDMAT as a precursor, dissolved in isopropanol, evaporated at 20 CTC, using Ar 2 as a carrier gas, and passing TDMA gas into Si/Si 2 2 /Ti/Pt/TiO z ( Kz ⁇ 2)
  • the reaction deposition chamber of the substrate TDMA thermally decomposes on the surface of the substrate to form a TiN (C, H) film.
  • the TiN (C, H) film was plasma-treated in situ by N 2 /3 ⁇ 4 plasma to obtain a TiN film.
  • the reaction deposition and plasma treatment were repeated to finally obtain a TiN film of a suitable thickness to obtain a Si/SiO 2 /Ti/Pt/Ti0 z ( l ⁇ z ⁇ 2 ) /TiN structure.
  • a top electrode pattern having different areas, such as 30 ⁇ 30 ⁇ m 2 , 50 ⁇ 50 ⁇ 2 , ⁇ 2 was produced by spin coating and photolithography, using a photoresist as a mask layer.
  • the TiN film was etched by ICP.
  • the ICP condition was that Cl 2 was used as the reaction gas, the power was 30/200 W, and the reaction gas pressure was 3 mT.
  • the TiO. is then etched by wet etching until the corrosion of the Pt metal layer stops.
  • the etching solution is buffered HF and the etching temperature is 30 °C.
  • the photoresist is removed by a dry plasma method to complete the fabrication of an RRAM memory cell having a Si/SiO 2 /Ti/Pt/TiO z (l ⁇ z ⁇ 2)/TiN structure.

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Description

包含电阻器的存储单元的制造方法 技术领域
本发明涉及包含电阻器的存储单元的制造方法， 特别涉及金属 /氧化物 /金属
( MOM ) 结构的阻变随机访问存储器 （RRAM ) 的存储单元的金属有机化学气相沉积 CM0CVD ) 制造方法。 背景技术
非挥发性存储器具有在无电源供应时仍能保持数据信息的优点，在信息存储领域 具有非常重要的地位， 也是当前信息存储技术的研究热点之一。 然而， 当今的主流非 挥发存储器-闪存 （flash ) 存在操作电压高、 速度慢、 耐久力差等问题。
RRAM己经表现出工作速度快、 存储密度高、 数据保持时间长、 耐久力强等优点， 是下一代半导体存储器强有力的候选者。 RRAM 的基本存储单元包括一个金属 （M) 绝缘体 （I ) 金属 (M) 三明治结构的电阻器， 其中两层金属分别作为顶电极和底电 极。
通过施加适当的电压或电流脉冲，可以使 MIM电阻器的电阻在高低电阻态之间转 换，以实现数据的写入和擦除。 RRAM工作的关键是 MM电阻器的电阻转变和记忆效应， 在电压或电流作用下电阻器的电阻可以发生可逆的、 巨大的改变。
常用的金属材料包括铂 （Pt )、 铝 （Al )、 氮化钛 （TiN ) 等， 绝缘体材料主要包 括各种氧化物材料和固体电解质材料等。氧化物材料由于具有和半导体工艺良好的兼 容性， 因此 MOM结构成为研究的重点。
目前 RRAM存储单元 MOM结构的制造方法， 顶电极和底电极通常采用溅射或蒸发 的方法制造， 氧化物材料一般采用反应溅射或者原子层沉积的方法制造。 利用金属有 机化学气相沉积（M0CVD )技术制造金属电极材料和氧化物材料进行 RRAM存储单元器 件制造的方法还没有相关报道。
金属和氧化物材料之间的界面特性对 RRAM的阻变性能有着重要的影响。 在上述 现有技术的方法中， 由于工艺变化导致的金属和氧化物材料之间的界面的不均匀性， 在同一个衬底上形成的多个 RRAM器件之间的阻变特性可能差异很大。
另一方面， 氧化物材料中的氧空位缺陷的产生和分布特性与 RRAM阻变开关特性 有密切关系。通过氧化物的金属惨杂以改变氧空位的特性，可以明显改善氧化物 RRAM 的阻变开关特性， 元素掺杂已经成为一个重要的改善 RRAM阻变性能的有效途径。 然 而， 上述现有技术的方法难以实现对氧空位的特性进行有效控制和调节。
这些是 RRAM的研究中应当需要解决的重要问题。 发明内容
本发明的目的是提供一种可以高密度集成的 MOM结构的 RRAM存储单元的 M0CVD 制造方法。
根据本发明， 提供一种包含电阻器的存储单元的制造方法， 包括以下步骤： a) 在绝缘衬底上形成底电极层； b)通过 M0CVD在底电极层上形成阻变材料层； c )在阻 变材料上形成顶电极层； 以及 d) 对顶电极层和阻变材料层进行图案化， 以形成分隔 开的存储单元。
与溅射法和原子层沉积法相比， M0CVD法具有厚度、组成和掺杂浓度可精确控制、 生长速度相对较快的优点， 同时 M0CVD也具有良好的台阶覆盖和空隙填充能力， 适合 大规模工艺加工。 M0CVD薄膜还具有生长质量高、 膜层均匀， 可以获得超薄层薄膜结 构的特点。
本发明的优点是利用 M0CVD法可以制造厚度、组分精确可控且具有良好均匀性的 阻变材料层， 从而可以获得界面特性优良的 MOM结构的 RRAM的存储单元。
有利地， 利用金属离子掺杂和 /或退火脱氧可以在阻变材料层中产生氧空位， 从 而明显改善存储单元的阻变开关特性。
利用本发明的方法， 可以在纳米尺度实现讓存储器件的高密度集成。 附图说明
图 1-5是根据本发明的包含电阻器的存储单元的制造方法各阶段的截面图。 图 6是本发明采用的 M0CVD装置示意图。 具体实施方式
以下将参照附图更详细地描述本发明。 在各个附图中， 相同的元件采用类似的附 图标记来表示。 为了清楚起见， 附图中的各个部分没有按比例绘制。
应当理解， 在描述器件的结构时， 当将一层、 一个区域称为位于另一层、 另一个 区域 "上"、 "上面"或 "上方"时， 可以指直接位于另一层、 另一个区域上面， 或者 在其与另一层、 另一个区域之间还包含其它的层或区域。 并且， 如果将器件翻转， 该 一层、 一个区域将位于另一层、 另一个区域 "下"、 "下面" 或 "下方"。
如果为了描述直接位于另一层、另一个区域上面的情形，本文将采用"直接在…… 上面"或 "在……上面并与之邻接" 的表述方式。
在下文中描述了本发明的许多特定的细节， 例如器件的结构、 材料、 尺寸、 处理 工艺和技术， 以便更清楚地理解本发明。 但正如本领域的技术人员能够理解的那样， 可以不按照这些特定的细节来实现本发明。
除非在下文中特别指出，半导体器件中的各个部分可以由本领域的技术人员公知 的材料构成。
本发明人提出利用 M0CVD技术制造 MOM结构的存储单元的方法。
作为示例性的实例方式， 该方法包括以下顺序执行的步骤。
参见图 1， 准备绝缘衬底。 该绝缘衬底可以是表面层为氧化层的叠层衬底。
例如， 绝缘衬底是包括单晶 Si底层 （base ) 10和 Si02层 11的叠层衬底。 可以 通过热氧化将单晶 Si底层 10的一部分转变成 Si02。 或者， 代替地， 通过化学气相沉 积 (CVD) 的方法在单晶 Si底层 10上形成 Si02层 11。
参见图 2， 通过溅射或蒸发， 在 Si02层 11上形成 Ti层 12作为粘附层， 然后通 过溅射、 蒸发或 M0CVD, 在 Ti层 12上形成底电极层 13 (如 Pt )。
Ti层 12是可选的层， 主要用于改善底电极层 13在衬底上的粘附强度。
M0CVD法制造 Pt薄膜的工艺流程为：
A) 将衬底放入反应沉积室， 衬底温度保持在 200- 700Ό ;
B) 以乙酰丙酮铂作为前驱体， 在 100 20CTC下升华成乙酰丙酮铂气体， 以 Ar2作 为载气， 气压在 10 103Pa， 将乙酰丙酮铂气体通入 M0CVD反应沉积室；
C) 将氧气作为反应气体通入反应沉积室；
D) 乙酰丙酮铂在衬底表面发生热分解反应， 获得 Pt薄膜。
参见图 3， 通过 M0CVD在底电极层 13上形成阻变材料层 14。
阻变材料层的组成表示为 （M'XMVX) „Μ3Α， 其中 M Nb、 Ta、 V、 Hf、 Zr、 Ti、 Ce、 Sr、 Mg、 La、 Gd、 Al、 Mn、 Pb、 Ba、 Ni、 Zn、 Co、 Mo、 Fe、 Cu、 W、 Mn和 Cr中的 —种金属。 M2为 Nb、 Ta、 V、 Hf、 Zr、 Ti、 Ce、 Sr、 Mg、 La、 Gd、 Al、 Mn、 Sr、 Pb、 Ba、 Ni、 Zn、 Co、 Mo、 Fe、 Cu、 W、 Mn和 Cr中的不同于 M1的一种金属。 M3是 Mn、 Ti、 Zr、 Ce、 Fe、 Hf、 Al和 Ta中的一种金属。 其中， x是 0 1 ; n是 1、 2或 3， y是 0、 1 或 2， z是 1 7。
氧化物可以是四元氧化物， 比如 La。5Sr。 5Mn03， 对应 M'是 La， M2是 Sr， M3是 Mn , X是 0. 5， n是 1， y是 1， z是 3。 氧化物材料也可以是三元氧化物， 比如 SrZr03， 对 应 M'是 Sr， M:i是 Zr , x是 1， n是 1， y是 1， z是 3。 氧化物也可以是二元氧化物， 比如 ，对应 M'是 Hf， X是 1 , n是 1 , y是 0， z是 2。氧化物还可以掺杂，如 Hf。 97A1。。302 是 A1掺杂的 Hf02。
氧化物中还可以加入第四种金属 M'1作为惨杂剂， 其化学式为 M'XM2 X, M" , M3 y0z , M4选自比拟替代的金属离子价态低的金属元素， 比如 Ca惨杂的 L 5Sr。5Mn03、 A1 或 La惨杂的 Hf02。
当 z为小数时， 表示氧化物材料缺氧， 是非化学配比的氧化物材料， 比如 HfOl 7 , z是 1. 7， 氧化铪处于缺氧状态。
M0CVD法制造阻变材料层的工艺流程为：
A ) 将衬底放入反应沉积室， 衬底温度保持在 200- 700°C ;
B ) 将用于制造阻变材料层的金属前驱体加入放有衬底的反应沉积室；
C ) 通入反应室的金属前驱体在衬底表面发生反应， 获得阻变材料层。
其中 M'、 M2和 M3金属前驱体可以为醇盐前驱体、 金属 二酮前驱体或者羰基金 属前驱体。 醇盐前驱体的化学式为 M ( OR ) „， 其中， M是 Nb、 Ta、 Hf、 Zr、 Ti、 W、 La和 Al中的金属； 0是氧； R是烷基， 包括 C2¾、 CH ( CH3 ) 2等， n是 3或 4。 V (钒） 的醇盐前驱体化学式是 V0 ( OR ) 3。 金属- β -二酮前驱体的化学式为 M C tmhd ) „, 其 中 M是 Hf、 Zr、 Ti、 Ce、 Sr、 Mg、 La、 Gd、 Mn、 Pb、 Ba、 Ni、 Zn、 Co、 Mo、 Fe、 Cu、 Mn和 Cr中的金属， n是 M金属的化合价。 羰基金属前驱体的化学式为 M ( CO ) „， 其 中 M是 Co、 Ni、 Fe、 Cr和 W中的金属， C是碳， 0是氧， n是 3、 4、 5或 6。
上述前驱体可以以固态形式或者液态形式使用。固态或液态的前驱体溶解在有机 烃溶剂中， 比如辛烷、 异丙醇等， 形成液态前驱体。 利用载气比如 Ar2将蒸发后的液 态前驱体通入反应沉积室。 固态的前驱体也可以在升华后用载气通入反应沉积室。 正 如本领域的技术人员己知的那样，液态前驱体的蒸发和固体前驱体的升华需要在适当 的温度下进行。
在将用于制造阻变材料层的金属前驱体加入放有衬底的反应沉积室的同时， 向反 应沉积室中通入反应气体如氧气、 氧化氮等， 或者通入气体成分能够部分进入沉积薄 膜的其它气体， 使反应沉积室的金属前驱体和氧气在衬底表面发生反应， 获得阻变材 料层。
然后， 在真空或者含氢气氛下进行退火以使阻变材料层脱氧， 获得缺氧状态的非 化学配比的阻变材料层。
阻变材料层在含氢气氛中原位进行退火处理的条件例如是：在含氢气氛中进行退 火处理， 气压低于一个大气压， 退火温度为 300 800°C。 所述含氢气氛为氢气、 或者 是氢气与氮气或惰性气体的混合气氛， 其中混合气氛中氢气体积含量为 5-100%。
阻变材料层在真空条件下原位进行退火处理的条件是：在真空条件下进行退火处 理， 真空度为 10— 3Pa， 退火温度为 300- 900 °C。
代替地， 利用金属离子掺杂的方法可以在氧化物中产生氧空位。
金属离子掺杂和退火脱氧可以单独使用也可以同时结合使用。
在金属离子掺杂时需要使用掺杂离子的前驱体，而退火脱氧则不需要使用任何前 驱体。
不同的掺杂剂可以调整氧化物材料中的氧空位的分布状态。为了利用金属离子掺 杂的方法获得处于缺氧状态的氧化物材料，作为掺杂剂的金属应当比拟替代的金属离 子价态低。 比如在 Hf02材料中掺杂 +3价的 Gd3+， 由于 Hf 是 +4价， 每 2个 Gd3+替代 2 个 Hf4+后， 将产生一个氧空位。 氧离子移出氧化物体内后将形成非化学配比的缺氧态 的 GdsHf1-x0z, 其中 z是 1到 2之间的小数。
参见图 4, 通过溅射、 蒸发或 M0CVD在阻变材料层 14上形成顶电极层 15 (如 Pt 或者 Ti N)。
制造 Pt薄膜的方法与结合图 2所述的步骤相同。
如果顶电极层 15由 TiN薄膜形成， 则制造 TiN薄膜的工艺步骤为-
A) 将衬底放入反应沉积室， 衬底温度保持在 300-50(TC；
B) 以四二甲基胺钛 （TDMAT) 作为前驱体， 以 Ar2作为载气， 将 TDMA通入 M0CVD 反应沉积室；
C) 四二甲基胺钛 （TDMA) 在衬底表面发生热分解反应， 得到 TiN (C, H) 薄膜；
D) 利用 / 等离子体原位对 TiN CC, H) 薄膜进行等离子体处理， 获得 TiN薄 膜；
E) 重复进行步骤 B、 C和 D, 以获得合适厚度的 TiN薄膜。
参见图 5, 对顶电极层 15和阻变材料层 14进行图案化， 形成顶电极图形， 从而 形成分隔开的存储单元。 该图案化可以包括以下步骤： 通过包含曝光和显影的光刻工艺， 在顶电极层 15 上形成含有图案的光抗蚀剂掩模； 通过千法蚀刻， 如离子铣蚀刻、 等离子蚀刻、 反应 离子蚀刻、 激光烧蚀， 或者通过其中使用蚀刻剂溶液的湿法蚀刻， 去除顶电极层 15 和阻变材料层 14的暴露部分， 该蚀刻步骤停止在底电极层 13的顶部； 通过在溶剂中 溶解或灰化去除光抗蚀剂掩模。
具体地，可利用电感耦合等离子（ICP)法刻蚀 Pt薄膜，利用电感耦合等离子（ICP) 法或反应离子刻蚀（RIE)刻蚀 TiN薄膜。 利用电感耦合等离子 （ICP)法或者反应离 子刻蚀 （RIE) 法刻蚀阻变材料层， 或利用湿法腐蚀法腐蚀阻变材料层。
顶电极层 15 的图形中的每一个相互隔开的电极区域对应于 RRAM的一个存储单 元。 在电极区域之间的沟槽中将填充绝缘材料以形成类似浅沟隔离的隔离结构， 完成 RRAM存储单元的制造。
RRAM存储单元的底电极和顶电极将可以分别作为电极引出， 进行电阻开关特性、 保持特性等各种电学性能测试。
在图 6 中示出了在根据本发明的包含电阻器的存储单元的制造方法中采用的 M0CVD装置示意图。
利用机械手 106把衬底 107装在托盘 104上，利用真空泵装置 105将反应室抽到 设定真空度。 利用电阻加热装置 102将衬底 107升温到设定温度。将前驱体气体通过 载气如 Ar2， 从反应室顶部通入反应室 101， 流向衬底 107。 反应气体从侧壁通入反应 室 101， 流向衬底 107。 通过调节前驱体和反应气体的流量保持反应室在一定的压力 范围。 反应室中装有等离子体产生装置 100, 分别向正负电极 103， 104施加电压， 前驱体气体在正负电极 103， 104之间的射频电场作用下形成等离子体， 在衬底 107 表面和反应气体反应生成所需薄膜。等离子体产生装置 100可以将前驱体气体以等离 子体的形式传送到衬底。由于前驱体带有一定能量，这样可以降低 M0CVD反应的温度， 提高沉积速率电阻加热装置 102可以调节反应衬底的温度。
以下将描述用于说明实现本发明的方法的实例。
实例 1 : 利用 M0CVD法制造 Si/Si02/Ti/Pt/Hf02/TiN结构的 RRAM存储单元 利用 Si晶体热氧化产生 Si02绝缘层， 利用溅射法在 Si/Si02上制造 Ti薄膜， 将
Si/Si02/Ti结构放入 M0CVD反应室。
首先制造 Pt金属底电极。以乙酰丙酮铂固体作为前驱体在 150°C下升华形成乙酰 丙酮铂气体， 利用 Ar2作为载气通入反应室， 02作为反应气体通入反应室， 衬底温度 保持在 400°C， 反应室气压在 100Pa， 在 Si/Si02/Ti 衬底上形成 Pt 薄膜， 获得 Si/Si02/Ti/Pt结构。
利用 Hf ( 0C2H5 ) 的醇盐固体作为前驱体， 溶解在异丙醇中， 形成液态前驱体， 在 lOPa下 150Ό下蒸发形成 Hf ( 0C2H5) 4气体， 利用 Ar2作为载体通入反应室， 通入 反应气体氧气， 衬底温度保持在 400Ό , 反应室气压在 200Pa， 在: Si/Si02/Ti/Pt上反 应生成 Hf02薄膜， 获得 Si/Si02/Ti/Pt/Hf02结构。
利用四二甲基胺钛 TDMAT作为前驱体， 溶解在异丙醇中， 在 20CTC下蒸发， 以 Ar2 作为载气， 将 TDMA气体通入放有 Si/Si02/Ti/Pt/Hf02衬底的反应沉积室。 TDMA在衬 底表面发生热分解反应， 生成 TiN ( C， H ) 薄膜。 然后利用 1¾/ 等离子体原位对 TiN ( C， H )薄膜进行等离子体处理， 获得 TiN薄膜。重复进行反应沉积和等离子体处理， 最终获得合适厚度的 TiN薄膜， 获得 Si/Si02/Ti/Pt/Hf02/TiN结构。
利用旋涂和光刻方法制作出具有 50 Χ 50 μ m2面积的顶电极图形，利用光刻胶作为 掩膜层。 然后利用 ICP的方式连续刻蚀 TiN和 Hf02薄膜， ICP条件为利用 Cl2为反应 气体， 功率为 30/200W, 反应气压为 3mT。 反应刻蚀到 Pt金属层停止。 Cl2刻蚀 Pt金 属层的速率低， Pt可以作为刻蚀停止层。
最后利用等离子体干法去胶去除光刻胶， 完成 Si/Si02/Ti/Pt/Hf02/TiN 结构的 RRAM存储单元的制造。
实例 2： 利用 M0CVD法制造 Si/Si02/Ti/Pt/Zr。 99La。。A/Pt结构的 RRAM存储单元 利用 Si晶体热氧化产生 Si02绝缘层， 利用蒸发法在 Si/Si02上制造 Ti薄膜， 将 Si/Si02/Ti结构放入 M0CVD反应室。
首先制造 Pt金属底电极。以乙酰丙酮铂固体作为前驱体在 15CTC下升华形成乙酰 丙酮铂气体， 利用 1：2作为载气通入反应室， 氧气作为反应气体通入反应室， 衬底温 度保持在 500°C， 反应室气压在 100Pa， 在 Si/Si02衬底上形成 Pt 薄膜， 获得 Si/Si02/Ti/Pt结构。
利用 Zr C tmhd ) 4固体和 La C tmhd ) 3作为前驱体， 根据 Zr和 La的摩尔比以及两 种金属沉积的平均速度计算出两种前驱体所需的量， 共同溶解在一定量的辛烷中， 形 成具有一定浓度的液态前驱体， 在 lOPa下 200Ό下蒸发形成前驱体气体， 利用 Ar2作 为载体通入反应室，通入反应气体氧气，衬底温度保持在 400°C，反应室气压在 100Pa， 在 Si/Si02/Ti/Pt上反应生成 Zr0 99La„。,02薄膜，获得 Si/Si02/Ti/Pt/Zr。 991^。,02结构。
以乙酰丙酮铂固体作为前驱体， 在 150Ό下升华形成乙酰丙酮铂气体， 利用 Ar2 作为载气通入反应室， 氧气作为反应气体通入反应室， 衬底温度保持在 400°C， 反应 室气压在 lOOPa , 在 Si/Si02/Ti/Pt/Zr。e9L¾ ()102结构上形成 Pt 薄膜， 获得 Si/Si02/Ti/Pt/Zr。 99La„„,02/Pt结构。
利用旋涂和光刻方法制作出具有 ΙΟΟ Χ ΙΟΟ μ ΐΏ2面积的顶电极图形，利用光刻胶作 为掩膜层。 然后利用 ICP方法刻蚀 Pt薄膜， ICP条件为利用 Cl2为反应气体， 功率为 50/300W, 反应气压为 5mT。 Pt刻蚀时间根据刻蚀速率获得。 Pt顶电极刻蚀结束后改 变刻蚀条件， 进一步刻蚀 Zro ^La^Ck直到 Pt金属层停止。 刻蚀条件为利用 Cl2为反 应气体， 功率为 30/200W, 反应气压为 3mT。 （12刻蚀 Pt金属层的速率低， Pt可以作 为刻蚀停止层。
最后利用等离子体干法去胶去除光刻胶， 完成 Si/SiCVTi/Pt/Zr^La^CyPt结 构的 RRAM存储单元的制造。
实例 3： 利用 M0CVD法制造 Si/Si02/Ti/Pt/Ti02 ( Kz<2 ) /TiN结构的 RRAM存 储单元
利用 Si晶体上 CVD法制造 Si02绝缘层， 利用溅射法在 Si/Si02上制造 Ti薄膜， 将 Si/Si02/Ti结构放入 M0CVD反应室。
首先制造 Pt金属底电极。以乙酰丙酮铂固体作为前驱体在 15CTC下升华形成乙酰 丙酮铂气体， 利用 Ar2作为载气通入反应室， 氧气作为反应气体通入反应室， 衬底温 度保持在 400Ό， 反应室气压在 100Pa， 在 Si/Si02衬底上形成 Pt 薄膜， 获得 Si/Si02/Ti/Pt结构。
利用 Ti ( 0C2H5) 溶解在异丙醇中， 形成液态前驱体， 在 lOPa下 150°C下蒸发形 成前驱体气体， 利用 Ar^f为载体通入反应室， 通入反应气体 02， 衬底温度保持在 400 °C , 反应室气压在 lOOPa, 在 Si/Si02/Ti/Pt上反应生成 Ti02薄膜。将 Ti02薄膜在 含氢气氛 / (体积比 9/1 ) , 温度为 600°C， 气压为 1个大气压， 退火 1小时， 获得 Ti0z ( Kz<2 ) 薄膜， 形成 Si/Si02/Ti/Pt/Ti0z ( Kz<2 ) 结构。
利用四二甲基胺钛 TDMAT作为前驱体， 溶解在异丙醇中， 在 20CTC下蒸发， 以 Ar2 作为载气， 将 TDMA气体通入放有 Si/Si02/Ti/Pt/TiOz ( Kz<2 )衬底的反应沉积室。 TDMA在衬底表面发生热分解反应， 生成 TiN (C， H) 薄膜。 然后利用 N2/¾等离子体 原位对 TiN (C, H) 薄膜进行等离子体处理， 获得 TiN薄膜。 重复进行反应沉积和等 离子体处理，最终获得合适厚度的 TiN薄膜，获得 Si/Si02/Ti/Pt/Ti0z ( l <z<2 ) /TiN 结构。 利用旋涂和光刻方法制作出具有不同面积， 如 30Χ30μπι2， 50Χ50 πι2, ΙΟΟΧΙΟΟμιη2的顶电极图形， 利用光刻胶作为掩膜层。 然后利用 ICP的方式刻蚀 TiN 薄膜， ICP条件为利用 Cl2为反应气体， 功率为 30/200W, 反应气压为 3mT。 然后利用 湿法腐蚀的方法腐蚀 TiO.,, 直到腐蚀到 Pt金属层停止。 腐蚀液为缓冲 HF， 腐蚀温度 为 30°C。
最后用利等离子体干法去胶去除光刻胶，完成 Si/Si02/Ti/Pt/TiOz(l<z<2)/TiN 结构的 RRAM存储单元的制造。
以上描述只是为了示例说明和描述本发明， 而非意图穷举和限制本发明。 因此， 本发明不局限于所描述的实例方式。 对于本领域的技术人员明显可知的变型或更改， 均在本发明的保护范围之内。

Claims

权 利 要 求
1、 一种包含电阻器的存储单元的制造方法， 包括以下步骤：
a) 在绝缘衬底上形成底电极层；
b ) 通过 M0CVD在底电极层上形成阻变材料层；
c ) 在阻变材料上形成顶电极层； 以及
d ) 对顶电极层和阻变材料层进行图案化， 以形成分隔开的存储单元。
2、 根据权利要求 1所述的方法， 其中在所述绝缘衬底包括单晶 Si底层和位于单 晶 Si底层上的 Si02层。
3、 根据权利要求 1 所述的方法， 其中在步骤 a) 中， 通过溅射、 蒸发或 M0CVD 形成底电极层。
4、 根据权利要求 3所述的方法， 其中所述底电极层由 Pt组成。
5、 根据权利要求 1所述的方法， 在步骤 a)和 b ) 之间还包括以下步骤： 通过溅 射或蒸发在绝缘衬底上形成金属粘附层，
其中， 在步骤 b ) 中， 在金属粘附层上形成所述底电极层。
6、 根据权利要求 5所述的方法， 其中所述金属粘附层由 Ti组成。
7、 根据权利要求 1 所述的方法， 其中在步骤 c ) 中， 通过溅射、 蒸发或 M0CVD 形成顶电极层。
8、 根据权利要求 7所述的方法， 其中所述顶电极层由 TiN或 Pt组成。
9、 根据权利要求 1所述的方法， 其中所述阻变材料层由 （M'XMVX)„Μ3Λ组成， 其 中 M'为 Nb、 Ta、 V、 Hf、 Zr、 Ti、 Ce、 Sr、 Mg、 La、 Gd、 Al、 Mn、 Pb、 Ba、 Ni、 Zn、 Co、 Mo、 Fe、 Cu、 W、 Mn和 Cr中的一种金属， M2为 Nb、 Ta、 V、 Hf、 Zr、 Ti、 Ce、 Sr、 Mg、 La、 Gd、 Al、 Mn, Sr、 Pb、 Ba、 Ni、 Zn、 Co、 Mo、 Fe、 Cu、 W、 Mn和 Cr中的不同 于 M'的一种金属， M3是 Mn、 Ti、 Zr、 Ce、 Fe、 Hf、 Al和 Ta中的一种金属， 其中， x 是 0-1 ; n是 1、 2或 3, y是 0、 1或 2, z是 1 - 7。
10、 根据权利要求 9所述的方法， 其中在步骤 b ) 中， M'、 M2、 M3的前驱体分别为 选自醇盐前驱体、 金属 - β -二酮前驱体或者羰基金属前驱体构成的组中的至少一种。
11、 根据权利要求 9所述的方法， 其中所述阻变材料层还包括作为掺杂剂的金属 M'， M'替代 Μ'、 Μ2、 Μ3中的一种金属的一部分， 并且比替代的金属的离子价态低。
12、 根据权利要求 11所述的方法， 其中在步骤 b ) 中， M4的前驱体为选自醇盐前 驱体、 金属 _ β 二酮前驱体或者羰基金属前驱体构成的组中的至少一种。
13、 根据权利要求 1所述的方法， 其中在步骤 b) 和 c ) 之间还包括退火脱氧， 以在阻变材料层中形成氧空位。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115014584A (zh) * 2022-06-05 2022-09-06 江苏师范大学 一种皮肤触觉仿生系统及其制备方法

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103236499B (zh) * 2013-05-07 2016-01-20 山东科技大学 一种单极型忆阻器及其制备方法
CN104576926B (zh) * 2013-10-25 2019-05-14 华邦电子股份有限公司 电阻式存储器及其制造方法
CN103594620B (zh) * 2013-11-05 2015-10-14 山东科技大学 一种单层纳米薄膜忆阻器及其制备方法
CN104726847B (zh) * 2015-03-30 2017-03-22 武汉理工大学 一种铜酸钆薄膜的制备方法
CN106299107A (zh) * 2015-05-25 2017-01-04 中国科学院苏州纳米技术与纳米仿生研究所 低形成电压的阻变存储器及其制备方法
CN105552223B (zh) * 2015-12-25 2017-12-01 山东科技大学 一种基于Sr(Ti1‑xMgx)O3‑x的单层纳米薄膜忆阻器的制备方法
CN105742487B (zh) * 2016-01-21 2018-02-06 山东科技大学 一种双极型纳米薄膜忆阻器的制备方法
CN111668252A (zh) * 2020-06-22 2020-09-15 中国科学院微电子研究所 阻变存储器及其制备方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101212019A (zh) * 2006-12-26 2008-07-02 北京大学 一种电阻式随机存取存储器的存储单元及其制备方法
CN101281952A (zh) * 2008-04-29 2008-10-08 北京大学 一种具有稳定阻变特性的材料及阻变存储器
US20090283736A1 (en) * 2007-06-05 2009-11-19 Yoshihiko Kanzawa Nonvolatile memory element, manufacturing method thereof, and nonvolatile semiconductor apparatus using the nonvolatile memory element

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101212019A (zh) * 2006-12-26 2008-07-02 北京大学 一种电阻式随机存取存储器的存储单元及其制备方法
US20090283736A1 (en) * 2007-06-05 2009-11-19 Yoshihiko Kanzawa Nonvolatile memory element, manufacturing method thereof, and nonvolatile semiconductor apparatus using the nonvolatile memory element
CN101281952A (zh) * 2008-04-29 2008-10-08 北京大学 一种具有稳定阻变特性的材料及阻变存储器

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
N, K.-C. ET AL.: "NiO thin films by MOCVD of Ni(dmamb)2 and their resistance switching phenomena", SURFACE & COATINGS TECHNOLOGY, vol. 201, 3 May 2007 (2007-05-03), pages 9252 - 9255 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115014584A (zh) * 2022-06-05 2022-09-06 江苏师范大学 一种皮肤触觉仿生系统及其制备方法
CN115014584B (zh) * 2022-06-05 2024-04-05 江苏师范大学 一种皮肤触觉仿生系统及其制备方法

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