WO2011122406A1 - 金属ベース基板およびその製造方法 - Google Patents
金属ベース基板およびその製造方法 Download PDFInfo
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- WO2011122406A1 WO2011122406A1 PCT/JP2011/056913 JP2011056913W WO2011122406A1 WO 2011122406 A1 WO2011122406 A1 WO 2011122406A1 JP 2011056913 W JP2011056913 W JP 2011056913W WO 2011122406 A1 WO2011122406 A1 WO 2011122406A1
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- sintered ceramic
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- C04B2237/708—Forming laminates or joined articles comprising layers of a specific, unusual thickness of one or more of the interlayers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
- Y10T156/10—Methods of surface bonding and/or assembly therefor
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24942—Structurally defined web or sheet [e.g., overall dimension, etc.] including components having same physical characteristic in differing degree
- Y10T428/2495—Thickness [relative or absolute]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/26—Web or sheet containing structurally defined element or component, the element or component having a specified physical dimension
- Y10T428/263—Coating layer not in excess of 5 mils thick or equivalent
- Y10T428/264—Up to 3 mils
- Y10T428/265—1 mil or less
Definitions
- the present invention relates to a metal base substrate that provides a heat dissipation function while mounting a semiconductor element and the like, and a method of manufacturing the same, and in particular, a metal that combines a ceramic layer and a metal plate that are formed using a low-temperature sintered ceramic material.
- the present invention relates to a base substrate and a manufacturing method thereof.
- the metal base substrate has a relatively high heat dissipation function, and is advantageously used for mounting electronic parts that require heat dissipation, such as semiconductor elements.
- a ceramic material is used as a material constituting the substrate layer combined with the metal plate.
- a low-temperature sintered ceramic material is a ceramic material that can be sintered at a temperature of 1050 ° C. or lower. Therefore, if the metal base substrate has a ceramic layer formed of a low-temperature sintered ceramic material formed on the metal plate, raw low-temperature sintering can be performed without using a metal plate made of a metal having a very high melting point. The ceramic layer and the metal plate can be obtained by batch firing.
- Patent Document 1 Japanese Patent Application Laid-Open No. 5-270934
- Patent Document 2 Japanese Patent Publication No. 11-514627
- Patent Document 3 Japanese Patent Publication No. 11-511719
- such a bonded glass layer is intended to function as a bonding material, and thus is a very weak layer from the viewpoint of bending strength.
- an object of the present invention is to provide a metal base substrate that can solve the above-described problems and a manufacturing method thereof.
- the present invention is first directed to a metal base substrate comprising a metal plate, a glass layer formed on the metal plate, and a low-temperature sintered ceramic layer formed on the glass layer.
- the glass layer has a thickness of 1 to 5 ⁇ m.
- the glass layer is made of Cu—Ba—Si based glass, and the low-temperature sintered ceramic layer is barium converted to BaO. 10 to 40 mol% and 40 to 80 mol% of silicon in terms of SiO 2 can be realized.
- the present invention is also directed to a method for manufacturing a metal base substrate.
- the method for producing a metal base substrate according to the present invention comprises a step of preparing a metal plate containing at least a Cu component on the surface, and 10-40 mol% of barium in terms of BaO and silicon in terms of SiO 2 on the surface of the metal plate.
- a step of producing a raw laminate by laminating a low-temperature sintered ceramic green layer containing a low-temperature sintered ceramic material containing 40 to 80 mol% at a low temperature sintered ceramic green layer And a step of firing at a temperature for sintering.
- the glass layer having a relatively low strength is thin, the flexural strength is increased, and thus the glass layer is hardly cracked.
- the low-temperature sintered ceramic green layer is directly formed on the metal plate and fired without using a separately formed bonding glass layer.
- a glass layer can be formed between the metal plate and the low-temperature sintered ceramic layer, and the metal plate and the low-temperature sintered ceramic layer are joined by this glass layer.
- this glass layer has a thickness in the range of 1 to 5 ⁇ m.
- the composition of the glass layer is substantially the same as the composition of the low-temperature sintered ceramic layer. Since it is the same, a crack becomes difficult to enter at an interface.
- the electronic component device 11 shown in FIG. 1 includes a metal base substrate 12 and a semiconductor element 13 mounted thereon.
- the metal base substrate 12 includes a metal plate 14, a glass layer 22 formed on the metal plate 14, a low-temperature sintered ceramic layer 15 formed on the glass layer 22, and further includes a constraining layer 16. ing.
- the metal plate 14 is bonded to the low-temperature sintered ceramic layer 15 via the glass layer 22.
- the low-temperature sintered ceramic layers 15 and the constraining layers 16 are alternately stacked, and the uppermost layer is provided by the constraining layers 16. Note that the uppermost layer may be provided by the low-temperature sintered ceramic layer 15.
- the low-temperature sintered ceramic layer 15 is thicker than the constraining layer 16.
- the low-temperature sintered ceramic layer 15 is made of a sintered body of a low-temperature sintered ceramic material.
- the constraining layer 16 includes a hardly-sinterable ceramic material that does not sinter at the sintering temperature of the low-temperature sintered ceramic material. When a part of the material flows into the constraining layer 16, the hardly sinterable ceramic material is solidified and densified.
- the glass layer 22 has a thickness of 1 to 5 ⁇ m.
- a circuit pattern is formed on the laminate portion 17 constituted by the low-temperature sintered ceramic layer 15 and the constraining layer 16 in the metal base substrate 12.
- some circuit patterns are not shown, but in connection with the semiconductor element 13, for example, some surface conductors 18, some interlayer connection conductors 19, and some in-plane wirings
- a conductor 20 is formed. Further, a specific one of the surface conductors 18 and the semiconductor element 13 are electrically connected by a bonding wire 21.
- heat generated in the semiconductor element 13 is conducted to the metal plate 14 through the stacked body portion 17 and is radiated from the metal plate 14.
- the glass layer 22 consists only of the component of the metal plate 14 and the component of the low-temperature sintered ceramic layer 15. More specifically, when the metal plate 14 includes a Cu component as in the case where the metal plate 14 is a copper plate, the glass layer 22 is made of a Cu—Ba—Si-based glass, and the low-temperature sintered ceramic layer 15 is made of barium with BaO. 10 to 40 mole% and silicon in terms of containing 40 to 80 mol% in terms of SiO 2.
- the metal plate 14 whole is It need not be composed of a uniform material.
- the surface of the metal plate 14 includes a Cu component
- the surface of the metal plate other than the copper plate includes a Cu component only on the surface, such as a surface of a metal plate pasted or copper plated. There may be.
- the glass layer 22 does not contain a filler. This is because the bonding strength between the metal plate 14 and the low-temperature sintered ceramic layer 15 is increased. When the filler is included, the bending strength can be improved. However, since the glass layer 22 has the bending strength improved by reducing the thickness to 1 to 5 ⁇ m, it is necessary to include the filler for the purpose of improving the bending strength. Because it is low.
- the metal base substrate 12 used in such an electronic component device 11 is preferably manufactured as follows.
- the metal plate 14 is prepared, and the low-sintered ceramic slurry containing the low-temperature sintered ceramic material and the hard-sintered material containing the hardly-sinterable ceramic material that does not sinter at the sintering temperature of the low-temperature sintered ceramic material Each of the ceramic ceramic slurry is prepared.
- the metal plate 14 at least a surface containing a Cu component is prepared.
- the low-temperature sintered ceramic material a material containing 10 to 40 mol% of barium in terms of BaO and 40 to 80 mol% of silicon in terms of SiO 2 is used.
- a low-temperature sintered ceramic green layer made of low-temperature sintered ceramic slurry and a hardly-sinterable ceramic green layer made of hardly-sinterable ceramic slurry are laminated on the metal plate 14, whereby the metal base substrate 12.
- a raw laminate corresponding to the state before firing is obtained.
- the low-temperature sintered ceramic green layer is to be the low-temperature sintered ceramic layer 15, and the hardly sinterable ceramic green layer is to be the constraining layer 16.
- the surface conductor 18, the interlayer connection conductor 19, and the in-plane wiring conductor 20 described above are provided in a specific ceramic green layer as necessary.
- low-temperature sintering is performed by forming a hardly-sinterable ceramic slurry into a sheet on a ceramic green sheet obtained by forming the low-temperature-sintered ceramic slurry into a sheet.
- a ceramic green sheet obtained by forming the low-temperature-sintered ceramic slurry into a sheet.
- a low-temperature sintered ceramic green sheet obtained by forming a low-temperature sintered ceramic slurry, and a hardly-sinterable ceramic green sheet obtained by forming a hardly-sinterable ceramic slurry may be alternately stacked.
- the formation of the hardly sinterable ceramic green layer and the formation of the low temperature sintered ceramic green layer may be repeated on the low temperature sintered ceramic green sheet.
- a step of collectively firing the raw laminate including the metal plate 14 and the low-temperature sintered ceramic green layer and the hardly sinterable ceramic green layer is performed.
- the low-temperature sintered ceramic material contained in the low-temperature sintered ceramic green layer is sintered to form a low-temperature sintered ceramic layer 15.
- a part of this low-temperature sintered ceramic material flows into the hardly sinterable ceramic green layer, solidifies the hardly sinterable ceramic material contained in the hardly sinterable ceramic green layer, and The green layer is densified to form the constraining layer 16.
- the hardly sinterable ceramic green layer does not substantially shrink in the planar direction in the firing step, it acts to suppress shrinkage in the planar direction of the low-temperature sintered ceramic green layer. Therefore, the shrinkage
- a glass layer 22 having a thickness of 1 to 5 ⁇ m is formed between the metal plate 14 and the low-temperature sintered ceramic layer 15, and the glass layer 22 and the low-temperature sintered ceramic layer 15 form a low temperature. A good bonding state is achieved with the sintered ceramic layer 15.
- the low-temperature sintered ceramic layer 15 contains 10 to 40 mol% of barium in terms of BaO and 40 to 80 mol% of silicon in terms of SiO 2 .
- the metal plate 14 contains a Cu component at least on the surface. Since the glass layer 22 is derived from a reaction layer generated between the metal plate 14 and the low-temperature sintered ceramic layer 15, at least the surface components of the metal plate 14 and the components of the low-temperature sintered ceramic layer 15 are combined. Therefore, in this embodiment, it is made of a Cu—Ba—Si based glass.
- the glass layer 22 may contain a component of the constraining layer 16.
- the low-temperature sintered ceramic layer 15 formed on the metal plate 14 includes a part of the laminated body portion 17 in which the plurality of low-temperature sintered ceramic layers 15 and the constraining layers 16 are alternately stacked.
- the present invention can also be applied to a metal base substrate having a structure in which only a low-temperature sintered ceramic layer is formed on a metal plate.
- Example 1 Preparation of composite green sheet BaCO 3 , Al 2 O 3 , and SiO 2 (quartz) powders are prepared, and mixed powders obtained by mixing these are calcined at a temperature of 840 ° C. for 120 minutes to prepare raw material powders The raw material powder and the MnCO 3 powder are mixed in an organic solvent to which a dispersant is added, and then a resin and a plasticizer are added and further mixed to obtain a low-temperature sintered ceramic slurry containing a low-temperature sintered ceramic material. Got.
- Table 1 shows the composition ratio of inorganic solids contained in the low-temperature sintered ceramic slurry.
- BaCO 3 is shown in terms of BaO
- MnCO 3 is shown in terms of MnO.
- a ceramic green sheet to be a low-temperature sintered ceramic green layer having a thickness of 40 ⁇ m was prepared by a doctor blade method.
- SiO 2 55.0 mol%, BaO: 20.0 mol%, MgO: 0.5 mol%, CaO: 5.5 mol%, Al 2 O 3: 4.0 mol%, B 2 O 3
- an organic solvent to which a dispersant is added at a ratio of 40 parts by weight to 60 parts by weight of glass powder and Al 2 O 3 powder consisting of 10.0 mol% and Li 2 O: 5.0 mol%
- a resin and a plasticizer were added and further mixed to obtain a hardly sinterable ceramic slurry containing a hardly sinterable ceramic material.
- the non-sinterable ceramic slurry was defoamed, it was formed into a sheet with a thickness of 4.0 ⁇ m by the doctor blade method on the ceramic green sheet described above. In this way, a composite green sheet was obtained in which the low temperature sintered ceramic green layer provided by the ceramic green sheet and the hardly sintered ceramic green layer formed from the hardly sintered ceramic slurry were superimposed.
- the ceramic molded body obtained by molding the hardly sinterable ceramic slurry alone is not sintered even when fired under the firing conditions described later.
- the unfired first evaluation sample was degreased in a nitrogen neutral atmosphere, and then fired in a nitrogen / hydrogen reducing atmosphere at the top temperature shown in the column “Baking Temperature” in Table 2, A sample for evaluation 1 was obtained.
- a capacitor is configured as the seventh and eighth composite green sheets from the copper plate side. Except for using a composite green sheet in which conductor patterns having a plane size of 4 mm ⁇ are formed at the same position using copper paste, the same operation as in the case of the first evaluation sample was performed, and the second evaluation sample was used. A sample was obtained.
- planar porosity The planar porosity was obtained in order to evaluate the sinterability.
- the first evaluation sample was subjected to cross-sectional polishing, and a scanning electron microscope (SEM) was used at a magnification of 1000 times. The ceramic portion was observed, and the planar porosity was measured by image analysis. Ten visual field images were analyzed for each sample, and the average values are shown in Table 2.
- SiO 2 is less than 40 mol%, and “insulation reliability” is low.
- SiO 2 exceeds 80 mol%, “planar porosity” is low, and “insulation reliability” is low.
- Al 2 O 3 is an optional component that is added to increase chemical durability and bending strength, but may not be included. Moreover, when the addition amount exceeds 25 mol%, it has been confirmed that defective sintering is caused. Further, MnO functions as a sintering aid, which may be replaced with glass, but it has been confirmed that when the added amount exceeds 14 mol%, strength is reduced.
- Table 3 shows the composition ratio of inorganic solids contained in this low-temperature sintered ceramic slurry.
- BaCO 3 is shown in terms of BaO
- H 3 BO 3 is shown in terms of B 2 O 3 .
- a ceramic green sheet to be a low-temperature sintered ceramic green layer having a thickness of 40 ⁇ m was prepared by a doctor blade method.
- SiO 2 55.0 mol%, BaO: 20.0 mol%, MgO: 0.5 mol%, CaO: 5.5 mol%, Al 2 O 3: 4.0 mol%, B 2 O 3
- an organic solvent to which a dispersant is added in a ratio of 35 parts by weight to 65 parts by weight of glass powder and Al 2 O 3 powder consisting of 10.0 mol% and Li 2 O: 5.0 mol%
- a resin and a plasticizer were added and further mixed to obtain a hardly sinterable ceramic slurry containing a hardly sinterable ceramic material.
- the non-sinterable ceramic slurry was defoamed, it was formed into a sheet shape with a thickness of 3.0 ⁇ m by the doctor blade method on the ceramic green sheet described above. In this way, a composite green sheet was obtained in which the low temperature sintered ceramic green layer provided by the ceramic green sheet and the hardly sintered ceramic green layer formed from the hardly sintered ceramic slurry were superimposed.
- the ceramic molded body obtained by molding the hardly sinterable ceramic slurry alone is not sintered even when fired under the firing conditions described later.
- SiO 2 is less than 40 mol%, and the “insulation reliability” is low.
- SiO 2 exceeds 80 mol%, “planar porosity” is low, and “insulation reliability” is low.
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Abstract
Description
1.複合グリーンシートの作製
BaCO3、Al2O3、およびSiO2(クオーツ)の各粉末を用意し、これらを混合した混合粉末を840℃の温度で120分間仮焼することによって、原料粉末を作製し、この原料粉末およびMnCO3粉末を、分散剤が添加された有機溶剤中で混合し、後に樹脂および可塑剤を添加してさらに混合して、低温焼結セラミック材料を含む低温焼結セラミックスラリーを得た。
(1)第1の評価用試料
平面寸法30mm□、厚み0.8mmの純銅からなる銅板の両面に、上記複合グリーンシートを10枚ずつ積層し、温度80℃、圧力80kgf/cm2の条件で300秒間プレスし、未焼成の第1の評価用試料を作製した。ここで、銅板には、複合グリーンシートの低温焼結セラミックグリーン層側が接し、この評価用試料の両主面には、難焼結性セラミックグリーン層が露出するように積層した。
上記第1の評価用試料の作製途中の複合グリーンシートの積層段階において、銅板側から7層目および8層目の複合グリーンシートとして、コンデンサを構成するように銅ペーストを用いて平面寸法4mm□の導体パターンを互いに同じ位置に形成した複合グリーンシートを用いたことを除いて、第1の評価用試料の場合と同様の操作を経て、第2の評価用試料を得た。
表2に示すように、「平面気孔率」、「界面接合性」および「絶縁信頼性」を評価した。
平面気孔率は、焼結性を評価するために求めたもので、第1の評価用試料を断面研磨し、走査型電子顕微鏡(SEM)を用いて、倍率1000倍でセラミック部分を観察し、画像解析により平面気孔率を測定した。各試料につき10視野画像解析し、その平均値を表2に示した。
第1の評価用試料を断面研磨し、SEMを用いて、倍率5000倍で銅板とセラミック部分との界面部でのクラック発生状況を観察した。各試料で30視野観察し、クラックの全く発生していない場合は界面接合性が良好であると判定し、表2において「○」で示し、他方、1箇所でもクラックが発生している場合は界面接合性が不良であると判定し、表2において「×」で示した。
第2の評価用試料を用い、温度:121℃、湿度:100%、導体パターン間への印加電圧:100DCV、および試験時間:300時間の条件で試験した。試験後の抵抗値を測定電圧:100DCVで測定した。この測定結果が表2に示されている。
1.複合グリーンシートの作製
BaCO3、Al2O3、SiO2(クオーツ)、およびH3BO3の各粉末を用意し、これらを混合した混合粉末を840℃の温度で120分間仮焼することによって、原料粉末を作製し、この原料粉末を、分散剤が添加された有機溶剤中で混合し、後に樹脂および可塑剤を添加してさらに混合して、低温焼結セラミック材料を含む低温焼結セラミックスラリーを得た。
実験例1の場合と同様の操作を経て、第1の評価用試料および第2の評価用試料を得た。
実験例1の場合と同様の方法で、表4に示すように、「平面気孔率」、「界面接合性」および「絶縁信頼性」を評価した。
12 金属ベース基板
14 金属板
15 低温焼結セラミック層
16 拘束層
22 ガラス層
Claims (4)
- 金属板と、
前記金属板の上に形成された厚み1~5μmのガラス層と、
前記ガラス層の上に形成された低温焼結セラミック層と
を備える、金属ベース基板。 - 前記ガラス層は、前記金属板の少なくとも表面の成分と前記低温焼結セラミック層の成分との少なくとも一部からなる、請求項1に記載の金属ベース基板。
- 前記金属板は、少なくとも表面にCu成分を含み、
前記ガラス層は、Cu-Ba-Si系のガラスからなり、
前記低温焼結セラミック層は、バリウムをBaO換算で10~40モル%およびケイ素をSiO2換算で40~80モル%含む、請求項1または2に記載の金属ベース基板。 - 少なくとも表面にCu成分を含む金属板を準備する工程と、
前記金属板の表面上に、バリウムをBaO換算で10~40モル%およびケイ素をSiO2換算で40~80モル%含む低温焼結セラミック材料を含む、低温焼結セラミックグリーン層を積層することによって、生の積層体を作製する工程と、
前記生の積層体を、前記低温焼結セラミックグリーン層が焼結する温度で焼成する工程と
を備える、金属ベース基板の製造方法。
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JP2012508230A JP5585649B2 (ja) | 2010-03-30 | 2011-03-23 | 金属ベース基板およびその製造方法 |
CN201180015855.6A CN102822112B (zh) | 2010-03-30 | 2011-03-23 | 金属基基板及其制造方法 |
US13/630,049 US8980028B2 (en) | 2010-03-30 | 2012-09-28 | Metal base substrate and manufacturing method thereof |
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CN105555058B (zh) * | 2015-12-14 | 2018-08-28 | 生益电子股份有限公司 | 一种基板的制作方法 |
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JPS63277549A (ja) * | 1987-05-08 | 1988-11-15 | Fujitsu Ltd | 超伝導セラミックスペ−スト組成物 |
US5256469A (en) | 1991-12-18 | 1993-10-26 | General Electric Company | Multi-layered, co-fired, ceramic-on-metal circuit board for microelectronic packaging |
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JPH11514627A (ja) | 1995-11-03 | 1999-12-14 | サーノフ コーポレイション | 多層共焼成セラミック組成物およびセラミックオンメタル回路基板 |
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US6753277B2 (en) * | 2000-02-29 | 2004-06-22 | Kyocera Corporation | Ceramics having excellent high-frequency characteristics and method of producing the same |
CN1142615C (zh) * | 2000-05-29 | 2004-03-17 | 北京科大天宇微电子材料技术开发有限公司 | 一种薄膜集成天线及其制作方法 |
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JPH05270934A (ja) * | 1991-12-18 | 1993-10-19 | General Electric Co <Ge> | セラミック・オン金属回路基板およびその製造方法 |
JPH05286776A (ja) * | 1992-04-06 | 1993-11-02 | Noritake Co Ltd | 金属−セラミックス複合構造体及びその製造方法 |
JPH10107174A (ja) * | 1996-09-26 | 1998-04-24 | Fuji Electric Co Ltd | 半導体装置用基板およびその製造方法 |
JPH10167851A (ja) * | 1996-12-05 | 1998-06-23 | Ngk Insulators Ltd | 金属とセラミックスの接合方法 |
JP2001267443A (ja) * | 2000-03-14 | 2001-09-28 | Kyocera Corp | 半導体素子収納用パッケージ |
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US20130264723A1 (en) | 2013-10-10 |
JPWO2011122406A1 (ja) | 2013-07-08 |
US8980028B2 (en) | 2015-03-17 |
JP5585649B2 (ja) | 2014-09-10 |
CN102822112A (zh) | 2012-12-12 |
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