WO2011099817A2 - Carte de circuit imprimé encastrée et son procédé de fabrication - Google Patents

Carte de circuit imprimé encastrée et son procédé de fabrication Download PDF

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Publication number
WO2011099817A2
WO2011099817A2 PCT/KR2011/000950 KR2011000950W WO2011099817A2 WO 2011099817 A2 WO2011099817 A2 WO 2011099817A2 KR 2011000950 W KR2011000950 W KR 2011000950W WO 2011099817 A2 WO2011099817 A2 WO 2011099817A2
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WO
WIPO (PCT)
Prior art keywords
circuit pattern
electronic device
chip
layer
embedded
Prior art date
Application number
PCT/KR2011/000950
Other languages
English (en)
Other versions
WO2011099817A3 (fr
Inventor
Min Seok Lee
Original Assignee
Lg Innotek Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lg Innotek Co., Ltd. filed Critical Lg Innotek Co., Ltd.
Publication of WO2011099817A2 publication Critical patent/WO2011099817A2/fr
Publication of WO2011099817A3 publication Critical patent/WO2011099817A3/fr

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/188—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10636—Leadless chip, e.g. chip capacitor or resistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a method of manufacturing an embedded printed circuit board (PCB) and an embedded PCB structure obtained by the manufacturing method. Particularly, the invention relates to a technique capable of forming an efficient electrical connecting structure of an electronic device chip and a PCB, which can be widely used.
  • PCB printed circuit board
  • PCB printed circuit board
  • a printed circuit board becomes an important electronic component and is widely used as a component constructing circuits of electric and electronic devices ranging from various electric and electronic products such as radio, TV and PCS to computers and high-tech electronic equipment.
  • Recent remarkable advancement in the technology of the electric and electronic devices requires a high-quality PCB, and thus the circuit density of the PCB rapidly increases.
  • high quality and high circuit density are achieved through a masking process using dry film resist and a process of plating regions on which components will be mounted with a metal such as Au.
  • the most important part of the technology of the embedded PCB is whether embedded components cope with high I/O count. This can be represented as the level of fine pitch.
  • Most techniques of manufacturing the embedded PCB use fine pattern circuit technology such as a bonding process using via/land, metal bump/land or solder/pad structure to connect an electronic device chip to a circuit.
  • FIG. 1 illustrates a process of mounting an electronic device chip 5 on a PCB using a solder/pad structure in a conventional method of manufacturing an embedded PCB.
  • a solder ball 7 is formed on a solder ball pad 6 and indirectly connected to a portion of the circuit pattern 3. Then, the circuit board is turned over and an insulating layer 8 is formed on the circuit board including the electronic device chip 5. Subsequently, an external circuit pattern 10 is formed or a via-hole 11 is formed and plating is performed to accomplish the circuit.
  • the present invention provides a method of manufacturing an embedded PCB and an embedded PCB structure in which embedded components are directly connected to a PCB without using an additional structure such as via/land, metal bump/land, solder/pad or conductive paste/pad to achieve micro fine pitch input/output interconnection, secure commoditization of electronic components and maximize the degree of freedom in the design of PCB.
  • a method of manufacturing an embedded PCB which comprises a first step of forming an internal circuit pattern exposing a chip terminal of an electronic device chip embedded in an insulating layer and a second step of forming a first circuit pattern that directly connects the chip terminal and the internal circuit pattern.
  • the first step may comprise a step a1 of forming the internal circuit pattern on a metal seed layer; a step a2 of mounting the electronic device chip on a mounting region spaced apart from the internal circuit pattern; a step a3 of forming an external circuit pattern layer including the insulating layer in which the electronic device chip and the connecting terminal are embedded; and a step a4 of exposing the chip terminal of the electronic device chip to the outside.
  • the metal seed layer is formed on a carrier board. That is, the step a1 forms the internal circuit pattern on the carrier board on which the metal seed layer is formed and the step a4 removes the carrier board and exposes the chip terminal of the electronic device chip to the outside.
  • the step a1 may form a dry film resist pattern on the metal seed layer and then performs plating.
  • the step a2 may bond an active device or a passive device onto the mounting region that exposes the metal seed layer using a non-conductive adhesive.
  • the step a3 may align at least one first insulating film formed around the electronic device chip and a second insulating film covering the top of the first insulating film, forms an external circuit layer on the second insulating film, and heats and presses the external circuit layer. Otherwise, the step a3 may align at least one first insulating film formed around the electronic device chip, a second insulating film covering the top of the first insulating film and an external circuit layer with a third insulating film including a circuit pattern arranged between the first insulating film and the second insulating film.
  • the step a4 may comprise the steps of removing the carrier board and removing the metal seed layer through half etching and may further comprise a step of dry-etching the half-etched face after the half etching step.
  • the second step forms the first circuit pattern including a connecting region where the chip terminal of the electronic device chip and the internal circuit pattern are directly connected to each other.
  • the second step may comprise the steps of coating dry film resist on the top face or bottom face of the internal circuit pattern and patterning the dry film resist; plating the patterned region to form the first circuit pattern; patterning the external circuit layer to form an external circuit pattern; and removing the dry film resist. Otherwise, the second step may comprise the steps of forming a metal thin film on the top face or bottom face of the internal circuit pattern; patterning the metal thin film through photolithography to form the first circuit pattern; and patterning the external circuit layer to form an external circuit pattern.
  • the manufacturing method may further comprises a third step of forming an insulating layer and an external circuit layer on both sides of the PCB including the first circuit pattern; a fourth step of forming a via-hole that electrically connects the first circuit pattern and at least one region of the internal circuit pattern; a fifth step of patterning the external circuit layer to form a second circuit pattern; a sixth step of forming a solder resist layer on a predetermined region of the second circuit pattern; and a seventh step of performing surface treatment on a region of the second circuit pattern on which the solder resist layer is not formed.
  • An embedded PCB manufactured through the aforementioned method comprise an electronic device chip including an external chip terminal; a first circuit pattern including a connecting region that is directly connected to the end of the chip terminal of the electronic device chip; an insulating layer in which the electronic device chip and the first circuit pattern are embedded; and a second circuit pattern electrically connected to the first circuit pattern.
  • the connecting region may be composed of the first circuit pattern directly connected to the chip terminal and an internal circuit pattern formed under the first circuit pattern.
  • the connecting region may be constructed in such a manner that a predetermined portion of the first circuit pattern covers a portion of the top face or side of the chip terminal.
  • the level of the bottom face of the first circuit pattern may be equal to or higher than the level of the top face of the end of the chip terminal in the connecting region.
  • the level of the top face of the internal circuit pattern may be equal to or lower than the level of the bottom face of the end of the chip terminal in the connecting region.
  • the electronic device chip may be an active device or a passive device.
  • embedded components can be directly connected to a PCB without using an additional structure such as via/land, metal bump/land, solder/pad or conductive paste/pad to achieve micro fine pitch input/output interconnection, secure commoditization of electronic components and maximize the degree of freedom in the design of PCB.
  • FIG. 1 illustrates a conventional process of mounting electronic device chips on a PCB in an embedded structure
  • FIG. 2 is a flowchart showing a method of manufacturing an embedded PCB according to the present invention
  • FIG. 3 and FIG. 4 illustrate the process of manufacturing an embedded PCB according to the present invention
  • FIG. 5 is a flowchart showing a manufacturing process following the process shown in FIG. 3 according to the present invention.
  • FIG. 6 illustrates the manufacturing process shown in FIG. 4.
  • FIG. 7 is a magnifying view of a connecting region where an electronic device chip terminal and a circuit pattern are connected to each other in a PCB structure according to the present invention.
  • the present invention provides a method of manufacturing an embedded PCB, which exposes input/output terminals of embedded components to the outside of the PCB and directly connects the input/output terminals to a circuit pattern of the PCB through plating without using via/land, metal bump/land, solder/pad or conductive paste/pad and a PCB structure obtained by the manufacturing method.
  • the manufacturing method includes a first step of forming an internal circuit pattern exposing a terminal of an electronic device chip embedded in an insulating layer and a second step of forming a first circuit pattern that directly connects the terminal and the internal circuit pattern.
  • a PCB manufactured by the manufacturing method includes an electronic device chip with an external chip connecting terminal, a first circuit pattern having a connecting region directly connected to the end of the chip connecting terminal of the electronic device chip, an insulating layer in which the electronic device chip and the first circuit pattern are embedded, and a second circuit pattern electrically connected to the first circuit pattern.
  • the method of manufacturing an embedded PCB includes the first step of forming an internal circuit pattern layer exposing a terminal of an electronic device chip embedded in an insulating layer and the second step of forming a first circuit pattern that directly connects the terminal and the internal circuit pattern layer.
  • the first step can form the internal circuit pattern layer in such a manner that a separate circuit pattern is formed on a metal seed layer or the circuit pattern is formed on the metal seed layer formed on a carrier board.
  • the metal seed layer is formed on the carrier board.
  • the process of forming the circuit pattern on the metal seed layer formed on the carrier board is distinguished from a process of the forming the circuit pattern on the metal seed layer without the carrier board only by a carrier board removal step.
  • a carrier board on which the metal seed layer is formed is prepared in step S1, and the internal circuit pattern layer corresponding to a separate circuit pattern is formed on the metal seed layer and an electronic device chip is mounted thereon in step S2. Then, an insulating layer is formed on the internal circuit pattern layer and the electronic device chip in step S3, a connecting terminal (referred to as chip terminal hereinafter) of the electronic device chip is exposed in steps S4 and S5, and the chip terminal is directly connected to the circuit pattern through plating in step S6.
  • chip terminal referred to as chip terminal hereinafter
  • a predetermined internal circuit pattern 130 is formed on the carrier board 110 on which the metal seed layer 120 is formed in step S1.
  • the internal circuit pattern 130 can be formed in such a manner that dry film resist is coated on the metal seed layer 120 and patterned and plating is performed on the metal seed layer 120 including the dry film resist pattern.
  • the electronic device chip 150 is mounted on a portion of the metal seed layer 130 on which the internal circuit pattern 130 is not formed in step S2.
  • the electronic device chip 150 includes an active device or a passive device.
  • an active device 153 having a chip terminal 152 formed on the bottom face thereof and a passive device 151 having a chip terminal 152 surrounding the side thereof are shown as the electronic device chips 150.
  • the mounting process can be performed in such a manner that a non-conductive adhesive 140 is coated on the metal seed layer and the electronic device chip 150 is bonded onto the non-conductive adhesive 140.
  • the insulating layer 160 and an external circuit layer 170 are formed to surround the electronic device chip 150 in step S3.
  • the insulating layer 160 may be formed in a multi-level structure. Specifically, at least one first insulating film 161 formed around the electronic device chip 150 and a second insulating film 162 covering the top of the first insulating film 161 are aligned, and the external circuit layer 170 is formed on the second insulating film 162, heated and pressed to form an external circuit pattern layer.
  • the first insulating film 161 and the second insulating film 162 can be stacked in B-stage in step S31.
  • each of the first and second insulating films 161 and 162 can be composed of multiple layers. Epoxy, phenol resin, prepreg, polyimide film or ABF film can be used as the material of the first and second insulating films 161 and 162.
  • one of the at least one first insulating film 161 can be formed in a structure (third insulating film) including circuit patterns 164 respectively formed on both sides of an insulating layer 163 and a conductive via 165 electrically connecting the circuit patterns 164 to each other in step S32.
  • the carrier board 110 is removed in step S4.
  • the following step will be explained on the assumption that the structure from which the carrier board has been removed is flipped such that the chip terminal of the electronic device chip faces upward.
  • the chip terminal (connecting terminal of the electronic device chip) is exposed to the outside in step S5.
  • the metal seed layer 120 is removed through half etching in steps S51 and S52. Subsequently, dry etching may be performed on the half-etched face to expose the chip terminal more efficiently in step S53.
  • step S6 After the first step is performed through the above-described process, the second step of forming the first circuit pattern that directly connects the chip terminal of the electronic device chip and the internal circuit pattern is carried out in step S6.
  • a photosensitive material 155 such as dry film resist is coated on the PCB on which the exposed chip terminal 152, 154 is formed and patterned, and then plating is carried out on the PCB including the dry film resist pattern 155 to form a first circuit pattern 180.
  • the dry film resist 155 is coated the top face or bottom face of the internal circuit pattern 130 and patterned and the first circuit pattern 180 is formed in the patterned region through plating.
  • the external circuit layer 170 is patterned, and then the dry film resist is removed in steps S61, S62 and S63.
  • a metal thin film can be used to form the first circuit pattern. Specifically, the metal thin film is formed through plating and patterned through photolithography to form the first circuit pattern. Then, the external circuit layer is patterned and the dry film resist is removed.
  • the first circuit pattern including connecting regions 181a, 181b, 181c and 181d where the chip terminal of the electronic device chip and the internal circuit pattern is directly connected to each other in step S6.
  • the chip terminal of the electronic device chip is directly connected to the circuit pattern without using an additional via/land, metal bump/land, solder/pad or conductive paste/pad.
  • the first circuit pattern can be formed using a metal such as Cu on the exposed chip terminal corresponding to an input/output terminal without forming a via and a land.
  • the first circuit pattern can be formed in various shapes such as linear, circular and polygonal shapes and connected to the chip terminal and the position of the first circuit pattern can be freely changed according to circuit layout.
  • components can be effectively embedded to achieve a highly integrated PCB even under the condition that the pitch of the input/output terminals is reduced and the number of input/output terminal pads decreases with the high integration of semiconductor devices. Furthermore, physical forms (bumping, electronic material, etc) of the embedded components are not restricted, and thus applicability of widely used components and the degree of freedom in the design of PCB can be improved.
  • an external circuit layer including an insulating layer is formed on both sides of the PCB in steps S7 and S8, and then a via-hole forming and plating material filling step S9, a second circuit pattern forming step S10 and S11 and a solder resist coating or surface treatment step S12 and S13 may be additionally performed.
  • an insulating layer 210 and an external circuit layer 220 are sequentially formed on both sides of the PCB on which the chip terminal and the first circuit pattern are connected to each other in steps S7 and S8.
  • a via-hole H for electrically connecting the first circuit pattern and at least one region of the internal circuit pattern is formed in step S9.
  • the via-hole H is formed through a process such as laser treatment and a metal 230 is filled in the via-hole H in step S10.
  • the metal can be one of Cu, Ag, Sn, Au and Ni, Pd.
  • the metal can be filled in the via-hole H using electroless plating, electroplating, screen printing, sputtering, evaporation, ink-jetting, dispensing, or a combination of these methods.
  • the external circuit layer 220 is patterned to form a second circuit pattern 221. Then, a solder resist layer 240 is formed on predetermined portions of the second circuit pattern 221 and surface treatment is performed on the portions on which the solder resist layer 240 is not formed.
  • the surface treatment can be performed in such a manner that the surface of the second circuit pattern 221 is plated with Cu, Ni, Pd, Au, Sn, Ag, Co, or a binary alloy or a ternary alloy of these metals to form a single plating layer or multiple plating layers.
  • the manufacturing process according to the present invention which includes the first and second steps for integration of products, can produce a full stack type high-integration PCB by using a PCB having a cavity formed in a copper compound layer (CCL) in which electronic device chips are primarily embedded.
  • CCL copper compound layer
  • a generally used physical method such as surface grinding is not used, and thus stability of embedded components of the PCB can be secured.
  • FIG. 7 is a cross-sectional view of the embedded PCB accomplished through the method of manufacturing an embedded PCB according to the present invention, particularly, a magnifying view of a region at which an electronic device chip terminal is directly connected to the circuit pattern.
  • the PCB according to the present invention may include the electronic device chip 150 with the external chip terminal 152, circuit patterns 130 and 180 having the connecting region 180d directly connected to the end of the chip terminal 152, the insulating layer 160 in which the electronic device chip 160 and the circuit patterns 130 and 180 are embedded, and the second circuit pattern 221 electrically connected to the first circuit pattern 180.
  • the connecting region 180d can be composed of the first circuit pattern 180 directly connected to the chip terminal 152 and the internal circuit pattern 130 formed under the first circuit pattern 180. Particularly, a region of the first circuit pattern 180 can cover the top face or the side of the chip terminal 152.
  • the chip terminal 152 and the first circuit pattern 180 can be arranged and connected such that the level X of the bottom face of the first circuit pattern 180 is equal to or higher than the level Y1 of the top face of the end of the chip terminal 152.
  • the connecting region can be formed such that the level Z of the top face of the internal circuit pattern 130 is equal to or lower than the level Y2 of the bottom face of the end of the chip terminal 152.
  • FIG. 6 shows only a passive device as the electronic device chip 150
  • the present invention can arrange terminals of an active device in the same layout as that of the passive device shown in FIG. 6.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Cette invention concerne un procédé de fabrication d'une carte de circuit imprimé encastrée. Ledit procédé comprend une première étape consistant à former un tracé de circuit interne exposant une borne de puce d'une puce de dispositif électronique encastrée dans une couche isolante. Le procédé comprend en outre une seconde étape consistant à former un premier tracé de circuit qui relie correctement la borne de puce au tracé de circuit interne. La carte de circuit imprimé encastrée produite par ledit procédé de fabrication comprend une puce de dispositif électronique comprenant une borne de puce externe, un premier tracé de circuit comprenant une zone de connexion directement reliée à une extrémité de la borne de puce de la puce de dispositif électronique, une couche isolante dans laquelle sont encastrés la puce de dispositif électronique et le premier tracé de circuit, et un second tracé de circuit électriquement relié au premier tracé de circuit. De cette manière, les composants intégrés et la carte de circuit imprimé peuvent être directement connectés sans recours à une structure complémentaire telle qu'un trou/plage de connexion, bosse métallique/plage de connexion, brasure/pastille ou pâte conductrice/pastille pour atteindre une interconnexion d'entrée/sortie à pas fin, assurer la banalisation des composants électriques et maximiser le degré de liberté dans la conception des cartes de circuit imprimé.
PCT/KR2011/000950 2010-02-12 2011-02-11 Carte de circuit imprimé encastrée et son procédé de fabrication WO2011099817A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2010-0013439 2010-02-12
KR1020100013439A KR101134519B1 (ko) 2010-02-12 2010-02-12 매립형 인쇄회로기판 및 그 제조방법

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Publication Number Publication Date
WO2011099817A2 true WO2011099817A2 (fr) 2011-08-18
WO2011099817A3 WO2011099817A3 (fr) 2012-02-02

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KR (1) KR101134519B1 (fr)
TW (1) TWI419630B (fr)
WO (1) WO2011099817A2 (fr)

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AT13436U1 (de) * 2011-08-31 2013-12-15 Austria Tech & System Tech Verfahren zur integration eines bauteils in eine leiterplatte oder ein leiterplatten-zwischenprodukt sowie leiterplatte oder leiterplatten-zwischenprodukt

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KR101438915B1 (ko) * 2012-11-02 2014-09-11 엘지이노텍 주식회사 인쇄회로기판 및 그의 제조 방법
CN104244582A (zh) * 2013-06-13 2014-12-24 宏启胜精密电子(秦皇岛)有限公司 埋入式高密度互连印刷电路板及其制作方法
KR102194718B1 (ko) * 2014-10-13 2020-12-23 삼성전기주식회사 임베디드 기판 및 임베디드 기판의 제조 방법
TWI581690B (zh) * 2014-12-30 2017-05-01 恆勁科技股份有限公司 封裝裝置及其製作方法

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WO2011099817A3 (fr) 2012-02-02

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