WO2011099817A3 - Carte de circuit imprimé encastrée et son procédé de fabrication - Google Patents

Carte de circuit imprimé encastrée et son procédé de fabrication Download PDF

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Publication number
WO2011099817A3
WO2011099817A3 PCT/KR2011/000950 KR2011000950W WO2011099817A3 WO 2011099817 A3 WO2011099817 A3 WO 2011099817A3 KR 2011000950 W KR2011000950 W KR 2011000950W WO 2011099817 A3 WO2011099817 A3 WO 2011099817A3
Authority
WO
WIPO (PCT)
Prior art keywords
circuit pattern
embedded
electronic device
manufacturing
pcb
Prior art date
Application number
PCT/KR2011/000950
Other languages
English (en)
Other versions
WO2011099817A2 (fr
Inventor
Min Seok Lee
Original Assignee
Lg Innotek Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lg Innotek Co., Ltd. filed Critical Lg Innotek Co., Ltd.
Publication of WO2011099817A2 publication Critical patent/WO2011099817A2/fr
Publication of WO2011099817A3 publication Critical patent/WO2011099817A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/188—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10636—Leadless chip, e.g. chip capacitor or resistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Cette invention concerne un procédé de fabrication d'une carte de circuit imprimé encastrée. Ledit procédé comprend une première étape consistant à former un tracé de circuit interne exposant une borne de puce d'une puce de dispositif électronique encastrée dans une couche isolante. Le procédé comprend en outre une seconde étape consistant à former un premier tracé de circuit qui relie correctement la borne de puce au tracé de circuit interne. La carte de circuit imprimé encastrée produite par ledit procédé de fabrication comprend une puce de dispositif électronique comprenant une borne de puce externe, un premier tracé de circuit comprenant une zone de connexion directement reliée à une extrémité de la borne de puce de la puce de dispositif électronique, une couche isolante dans laquelle sont encastrés la puce de dispositif électronique et le premier tracé de circuit, et un second tracé de circuit électriquement relié au premier tracé de circuit. De cette manière, les composants intégrés et la carte de circuit imprimé peuvent être directement connectés sans recours à une structure complémentaire telle qu'un trou/plage de connexion, bosse métallique/plage de connexion, brasure/pastille ou pâte conductrice/pastille pour atteindre une interconnexion d'entrée/sortie à pas fin, assurer la banalisation des composants électriques et maximiser le degré de liberté dans la conception des cartes de circuit imprimé.
PCT/KR2011/000950 2010-02-12 2011-02-11 Carte de circuit imprimé encastrée et son procédé de fabrication WO2011099817A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2010-0013439 2010-02-12
KR1020100013439A KR101134519B1 (ko) 2010-02-12 2010-02-12 매립형 인쇄회로기판 및 그 제조방법

Publications (2)

Publication Number Publication Date
WO2011099817A2 WO2011099817A2 (fr) 2011-08-18
WO2011099817A3 true WO2011099817A3 (fr) 2012-02-02

Family

ID=44368332

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2011/000950 WO2011099817A2 (fr) 2010-02-12 2011-02-11 Carte de circuit imprimé encastrée et son procédé de fabrication

Country Status (3)

Country Link
KR (1) KR101134519B1 (fr)
TW (1) TWI419630B (fr)
WO (1) WO2011099817A2 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AT13436U1 (de) * 2011-08-31 2013-12-15 Austria Tech & System Tech Verfahren zur integration eines bauteils in eine leiterplatte oder ein leiterplatten-zwischenprodukt sowie leiterplatte oder leiterplatten-zwischenprodukt
KR101438915B1 (ko) * 2012-11-02 2014-09-11 엘지이노텍 주식회사 인쇄회로기판 및 그의 제조 방법
CN104244582A (zh) * 2013-06-13 2014-12-24 宏启胜精密电子(秦皇岛)有限公司 埋入式高密度互连印刷电路板及其制作方法
KR102194718B1 (ko) * 2014-10-13 2020-12-23 삼성전기주식회사 임베디드 기판 및 임베디드 기판의 제조 방법
TWI581690B (zh) * 2014-12-30 2017-05-01 恆勁科技股份有限公司 封裝裝置及其製作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20070076798A (ko) * 2006-01-20 2007-07-25 삼성전기주식회사 임베디드 인쇄회로기판 및 그 제작방법
JP2008177552A (ja) * 2006-12-18 2008-07-31 Dainippon Printing Co Ltd 電子部品内蔵配線板、及び電子部品内蔵配線板の放熱方法
JP2008288298A (ja) * 2007-05-16 2008-11-27 Toppan Printing Co Ltd 電子部品を内蔵したプリント配線板の製造方法
KR20090131877A (ko) * 2008-06-19 2009-12-30 삼성전기주식회사 칩 내장 인쇄회로기판 및 그 제조방법

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI295912B (en) * 2005-10-14 2008-04-11 Advanced Semiconductor Eng Method for manufacturing a substrate embedded with an electronic component and device from the same
KR100926657B1 (ko) * 2008-04-22 2009-11-17 대덕전자 주식회사 웨이퍼 레벨 패키지 된 인쇄회로기판 및 제조 방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20070076798A (ko) * 2006-01-20 2007-07-25 삼성전기주식회사 임베디드 인쇄회로기판 및 그 제작방법
JP2008177552A (ja) * 2006-12-18 2008-07-31 Dainippon Printing Co Ltd 電子部品内蔵配線板、及び電子部品内蔵配線板の放熱方法
JP2008288298A (ja) * 2007-05-16 2008-11-27 Toppan Printing Co Ltd 電子部品を内蔵したプリント配線板の製造方法
KR20090131877A (ko) * 2008-06-19 2009-12-30 삼성전기주식회사 칩 내장 인쇄회로기판 및 그 제조방법

Also Published As

Publication number Publication date
TW201204204A (en) 2012-01-16
KR20110093408A (ko) 2011-08-18
KR101134519B1 (ko) 2012-04-19
TWI419630B (zh) 2013-12-11
WO2011099817A2 (fr) 2011-08-18

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