WO2011087310A2 - Group iii nitride semiconductor light-emitting device - Google Patents

Group iii nitride semiconductor light-emitting device Download PDF

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WO2011087310A2
WO2011087310A2 PCT/KR2011/000281 KR2011000281W WO2011087310A2 WO 2011087310 A2 WO2011087310 A2 WO 2011087310A2 KR 2011000281 W KR2011000281 W KR 2011000281W WO 2011087310 A2 WO2011087310 A2 WO 2011087310A2
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nitride semiconductor
group iii
iii nitride
electrode
semiconductor layer
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WO2011087310A3 (en
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김창태
이태희
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주식회사 에피밸리
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate

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  • the present disclosure relates to a semiconductor light emitting device as a whole, and more particularly, to a group III nitride semiconductor light emitting device for improving the separation of a pad to be wire bonded.
  • the group III nitride semiconductor light emitting element is a group III nitride of Al (x) Ga (y) In (1-xy) N (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1).
  • Means a light emitting device such as a light emitting diode including a semiconductor layer, and additionally excludes the inclusion of a material consisting of elements of other groups such as SiC, SiN, SiCN, CN or a semiconductor layer made of these materials. no.
  • FIG. 1 is a view illustrating an example of a conventional Group III nitride semiconductor light emitting device, wherein the Group III nitride semiconductor light emitting device is grown on the substrate 100, the buffer layer 200 grown on the substrate 100, and the buffer layer 200.
  • the p-side electrode 600 formed on the group nitride semiconductor layer 500, the p-side bonding pad 700 formed on the p-side electrode 600, the p-type group III nitride semiconductor layer 500 and the active layer 400 are formed.
  • the n-side electrode 800 and the passivation layer 900 are formed on the n-type group III nitride semiconductor layer 300 exposed by mesa etching.
  • a GaN-based substrate is used as the homogeneous substrate, and a sapphire substrate, a SiC substrate, or a Si substrate is used as the heterogeneous substrate. Any substrate may be used as long as the group III nitride semiconductor layer can be grown.
  • the n-side electrode 800 may be formed on the SiC substrate side.
  • Group III nitride semiconductor layers grown on the substrate 100 are mainly grown by MOCVD (organic metal vapor growth method).
  • the buffer layer 200 is intended to overcome the difference in lattice constant and thermal expansion coefficient between the dissimilar substrate 100 and the group III nitride semiconductor, and US Pat.
  • a technique for growing an AlN buffer layer having a thickness of US Pat. No. 5,290,393 describes Al (x) Ga (1-x) N having a thickness of 10 kPa to 5000 kPa at a temperature of 200 to 900 C on a sapphire substrate. (0 ⁇ x ⁇ 1)
  • a technique for growing a buffer layer is described, and US Patent Publication No. 2006/154454 discloses growing a SiC buffer layer (seed layer) at a temperature of 600 ° C.
  • the undoped GaN layer is grown prior to the growth of the n-type Group III nitride semiconductor layer 300, which may be viewed as part of the buffer layer 200 or as part of the n-type Group III nitride semiconductor layer 300. .
  • n-type contact layer In the n-type group III nitride semiconductor layer 300, at least a region (n-type contact layer) in which the n-side electrode 800 is formed is doped with impurities, and the n-type contact layer is preferably made of GaN and doped with Si. .
  • U. S. Patent No. 5,733, 796 describes a technique for doping an n-type contact layer to a desired doping concentration by controlling the mixing ratio of Si and other source materials.
  • the active layer 400 is a layer that generates photons (light) through recombination of electrons and holes, and is mainly composed of In (x) Ga (1-x) N (0 ⁇ x ⁇ 1), and one quantum well layer (single quantum wells) or multiple quantum wells.
  • the p-type III-nitride semiconductor layer 500 is doped with an appropriate impurity such as Mg, and has an p-type conductivity through an activation process.
  • U.S. Patent No. 5,247,533 describes a technique for activating a p-type group III nitride semiconductor layer by electron beam irradiation, and U.S. Patent No. 5,306,662 annealing at a temperature of 400 DEG C or higher to A technique for activating is described, and US Patent Publication No.
  • 2006/157714 discloses a p-type III-nitride semiconductor layer without an activation process by using ammonia and a hydrazine-based source material together as a nitrogen precursor for growing the p-type III-nitride semiconductor layer. Techniques for having this p-type conductivity have been described.
  • the p-side electrode 600 is provided to supply a good current to the entire p-type group III nitride semiconductor layer 500.
  • US Patent No. 5,563,422 is formed over almost the entire surface of the p-type group III nitride semiconductor layer.
  • a light-transmitting electrode made of Ni and Au in ohmic contact with the p-type III-nitride semiconductor layer 500 is described.
  • US Pat. No. 6,515,306 discloses n on the p-type III-nitride semiconductor layer. A technique is described in which a type superlattice layer is formed and then a translucent electrode made of indium tin oxide (ITO) is formed thereon.
  • ITO indium tin oxide
  • the p-side electrode 600 may be formed to have a thick thickness so as not to transmit light, that is, to reflect the light toward the substrate side, this technique is referred to as flip chip (flip chip) technology.
  • U. S. Patent No. 6,194, 743 describes a technique relating to an electrode structure including an Ag layer having a thickness of 20 nm or more, a diffusion barrier layer covering the Ag layer, and a bonding layer made of Au and Al covering the diffusion barrier layer.
  • the p-side bonding pad 700 and the n-side electrode 800 are for supplying current and wire bonding to the outside, and US Patent No. 5,563,422 describes a technique in which the n-side electrode is composed of Ti and Al.
  • the passivation layer 900 is formed of a material such as silicon dioxide and may be omitted.
  • the n-type III-nitride semiconductor layer 300 or the p-type III-nitride semiconductor layer 500 may be composed of a single layer or a plurality of layers, and recently, the substrate 100 may be formed by laser or wet etching. A technique for manufacturing a vertical light emitting device by separating from group III nitride semiconductor layers has been introduced.
  • such a light emitting device may cause a problem that the p-side bonding pad 700 is peeled off from the light emitting device when wire bonding to the p-side bonding pad 700.
  • FIG. 1 is a view showing an example of a conventional group III nitride semiconductor light emitting device
  • FIGS. 2 and 3 are views showing an example of a group III nitride semiconductor light emitting device according to the present disclosure
  • FIG. 4 is a view showing another example of a group III nitride semiconductor light emitting device according to the present disclosure.
  • FIG. 5 and 6 are views showing another example of the group III nitride semiconductor light emitting device according to the present disclosure.
  • FIG. 7 is a view showing another example of a group III nitride semiconductor light emitting device according to the present disclosure.
  • the group III nitride semiconductor light emitting device includes a substrate 10, a buffer layer 11 formed on the substrate 10, and A first group III nitride semiconductor layer 12 formed on the buffer layer 11, an active layer 13 formed on the first group III nitride semiconductor layer 12 to generate light by recombination of electrons and holes, and an active layer
  • the first group III nitride semiconductor layer in which the bonding pad 15 and the first electrode 17 formed on the group nitride semiconductor layer 14, and the second group III nitride semiconductor layer 14 and the active layer 13 are etched and exposed.
  • the second electrode 20 is formed on the (12).
  • the first group III nitride semiconductor layer 12 and the second group III nitride semiconductor layer 14 are provided to have different conductivity.
  • the first group III nitride semiconductor layer 12 is formed of an n-type semiconductor layer
  • the Group 2 III nitride semiconductor layer 14 was formed of a p-type semiconductor layer.
  • the first opening 21 is formed on the second group III nitride semiconductor layer 14 using an E-beam evaporator.
  • the translucent electrode 16 is laminated as much as possible.
  • the first opening 21 has a diameter of 5 to 10 micrometers and is formed at a position where the first electrode 17 is to be formed instead of the front surface of the translucent electrode 16.
  • the first opening 21 is for increasing the area where the second group III nitride semiconductor layer 14 and the first electrode 17 contact each other, and the shape of the first opening 21 and the plurality of first openings 21 are increased.
  • the arrangement form of is not particularly limited.
  • first opening 21 and the first electrode 17 extend from the bonding pad 15 toward the second electrode 20
  • shape of the first electrode 17 is The present invention is not limited thereto and may be formed to extend to a plurality of branch electrodes in order to facilitate current diffusion.
  • the bonding pad 15 is formed to contact the second group III nitride semiconductor layer 14.
  • the bonding pad 15 may be pulled by the wire when wire bonding or after the wire bonding is performed, and thus peeling may occur.
  • the bonding pad 15 may include a first electrode formed to fill the first opening 21. 17) the area in contact with the second group III nitride semiconductor layer 14 is widened, so that the adhesive force can be improved to improve this phenomenon.
  • FIG. 4 is a view illustrating another example of the group III nitride semiconductor light emitting device according to the present disclosure. Unlike FIG. 3, a bonding pad 15 is formed on the light transmissive electrode 16, and the bonding pad 15 is formed of the first electrode 17. ) Is electrically connected to the second group III nitride semiconductor layer 14.
  • FIG. 5 and 6 illustrate another example of a group III nitride semiconductor light emitting device according to the present disclosure, in which a second opening 18 is formed in a region where a bonding pad 15 is to be formed, thereby forming a second group III nitride semiconductor.
  • the light transmissive electrode 16 is formed such that the layer 14 is exposed.
  • the diameter of the circle is set to about 110 to 120 micrometers in consideration of the size of the bonding pad 15, and the second opening 18 formed in the region is formed in the region where the first electrode 17 is to be formed.
  • the first opening 21 is formed to have a diameter of 5 to 10 micrometers as shown in FIG. 3, the shape and size of the first opening 21 and the second opening 18 are not limited thereto.
  • the bonding pad 15 is smaller than the second opening 18 (eg, 100 micrometers).
  • the bonding pad 15 and the translucent electrode 16 are electrically connected by a third electrode 19 formed in a bridge shape as shown in FIG. 5.
  • the third electrode 19 may be formed in plural, and it is preferable that the third electrode 19 be radially formed to smoothly supply current.
  • the bonding pad 15, the first electrode 17, and the third electrode 19 are simultaneously formed, but may be formed through separate processes.
  • the contact edge of the bonding pad 15 is weak when the wire is bonded or after bonding, so that the outer edge of the bonding pad 15 is peeled off and peeled. It is a trigger of the peeling, which may cause the bonding pad 15 and the translucent electrode 16 to be separated from each other to cause peeling, but the bonding pad 15 and the translucent electrode 16 are isolated as described above. Since the bonding pad 15 is formed and electrically connected by the third electrode 19 to increase the area in which the bonding pad 15 is in contact with the second group III nitride semiconductor layer 14, the adhesive force may be improved.
  • FIG. 7 is a view illustrating another example of the group III nitride semiconductor light emitting device according to the present disclosure.
  • the first opening 21 is formed in a rectangular shape on the second group III nitride semiconductor layer 14, and the first electrode ( 17 is formed to fill a part of the first opening 21 in a form extending from the bonding pad 15 toward the second electrode 20.
  • the first opening 21 forms a barrier against the flow of current (arrow direction), thereby preventing the current from being concentrated in the center of the device, thereby facilitating overall current diffusion.
  • a group III nitride semiconductor light emitting device A group III nitride semiconductor light emitting device.
  • a group III nitride semiconductor light emitting element wherein the first electrode extends from the bonding pad toward the second electrode.
  • a group III nitride semiconductor light emitting element wherein the first electrode is formed so as to fill all of the plurality of openings.
  • the present disclosure it is possible to improve the yield by improving the bonding pad is separated from the light emitting device during wire bonding.

Abstract

The present disclosure relates to a group III nitride semiconductor light-emitting device, comprising a plurality of group III nitride semiconductor layers including a first group III nitride semiconductor layer having a first conductivity, a second group III nitride semiconductor layer having a second conductivity different from the first conductivity, and an activation layer interposed between the first group III nitride semiconductor layer and the second group III-nitride semiconductor layer, so as to generate light through the recombination of electrons and holes; a bonding pad electrically connected to the plurality of group III nitride semiconductor layers; a light-transmitting electrode which is formed on the second group III nitride semiconductor layer, and which has a plurality of openings for exposing the second group III nitride semiconductor layer; a first electrode formed to fill at least a portion of the plurality of openings; and a second electrode formed on the first group III nitride semiconductor layer, wherein said bonding pad and the first electrode are electrically connected together.

Description

3족 질화물 반도체 발광소자Group III nitride semiconductor light emitting device
본 개시(Disclosure)는 전체적으로 반도체 발광소자에 관한 것으로, 특히 와이어 본딩이 되는 패드가 떨어져 나가는 것을 개선하기 위한 3족 질화물 반도체 발광소자에 관한 것이다.The present disclosure relates to a semiconductor light emitting device as a whole, and more particularly, to a group III nitride semiconductor light emitting device for improving the separation of a pad to be wire bonded.
여기서, 3족 질화물 반도체 발광소자는 Al(x)Ga(y)In(1-x-y)N (0≤x≤1, 0≤y≤1, 0≤x+y≤1)로 된 3족 질화물 반도체층을 포함하는 발광다이오드와 같은 발광소자를 의미하며, 추가적으로 SiC, SiN, SiCN, CN와 같은 다른 족(group)의 원소들로 이루어진 물질이나 이들 물질로 된 반도체층을 포함하는 것을 배제하는 것은 아니다.Here, the group III nitride semiconductor light emitting element is a group III nitride of Al (x) Ga (y) In (1-xy) N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). Means a light emitting device such as a light emitting diode including a semiconductor layer, and additionally excludes the inclusion of a material consisting of elements of other groups such as SiC, SiN, SiCN, CN or a semiconductor layer made of these materials. no.
여기서는, 본 개시에 관한 배경기술이 제공되며, 이들이 반드시 공지기술을 의미하는 것은 아니다(This section provides background information related to the present disclosure which is not necessarily prior art).This section provides background information related to the present disclosure which is not necessarily prior art.
도 1은 종래의 3족 질화물 반도체 발광소자의 일 예를 나타내는 도면으로서, 3족 질화물 반도체 발광소자는 기판(100), 기판(100) 위에 성장되는 버퍼층(200), 버퍼층(200) 위에 성장되는 n형 3족 질화물 반도체층(300), n형 3족 질화물 반도체층(300) 위에 성장되는 활성층(400), 활성층(400) 위에 성장되는 p형 3족 질화물 반도체층(500), p형 3족 질화물 반도체층(500) 위에 형성되는 p측 전극(600), p측 전극(600) 위에 형성되는 p측 본딩 패드(700), p형 3족 질화물 반도체층(500)과 활성층(400)이 메사 식각되어 노출된 n형 3족 질화물 반도체층(300) 위에 형성되는 n측 전극(800), 그리고 보호막(900)을 포함한다.1 is a view illustrating an example of a conventional Group III nitride semiconductor light emitting device, wherein the Group III nitride semiconductor light emitting device is grown on the substrate 100, the buffer layer 200 grown on the substrate 100, and the buffer layer 200. n-type group III nitride semiconductor layer 300, an active layer 400 grown on the n-type group III nitride semiconductor layer 300, p-type group III nitride semiconductor layer 500, p-type 3 grown on the active layer 400 The p-side electrode 600 formed on the group nitride semiconductor layer 500, the p-side bonding pad 700 formed on the p-side electrode 600, the p-type group III nitride semiconductor layer 500 and the active layer 400 are formed. The n-side electrode 800 and the passivation layer 900 are formed on the n-type group III nitride semiconductor layer 300 exposed by mesa etching.
기판(100)은 동종기판으로 GaN계 기판이 이용되며, 이종기판으로 사파이어 기판, SiC 기판 또는 Si 기판 등이 이용되지만, 3족 질화물 반도체층이 성장될 수 있는 기판이라면 어떠한 형태이어도 좋다. SiC 기판이 사용될 경우에 n측 전극(800)은 SiC 기판 측에 형성될 수 있다.As the substrate 100, a GaN-based substrate is used as the homogeneous substrate, and a sapphire substrate, a SiC substrate, or a Si substrate is used as the heterogeneous substrate. Any substrate may be used as long as the group III nitride semiconductor layer can be grown. When a SiC substrate is used, the n-side electrode 800 may be formed on the SiC substrate side.
기판(100) 위에 성장되는 3족 질화물 반도체층들은 주로 MOCVD(유기금속기상성장법)에 의해 성장된다.Group III nitride semiconductor layers grown on the substrate 100 are mainly grown by MOCVD (organic metal vapor growth method).
버퍼층(200)은 이종기판(100)과 3족 질화물 반도체 사이의 격자상수 및 열팽창계수의 차이를 극복하기 위한 것이며, 미국특허 제5,122,845호에는 사파이어 기판 위에 380℃에서 800℃의 온도에서 100Å에서 500Å의 두께를 가지는 AlN 버퍼층을 성장시키는 기술이 기재되어 있으며, 미국특허 제5,290,393호에는 사파이어 기판 위에 200℃에서 900℃의 온도에서 10Å에서 5000Å의 두께를 가지는 Al(x)Ga(1-x)N (0≤x<1) 버퍼층을 성장시키는 기술이 기재되어 있고, 미국공개특허공보 제2006/154454호에는 600℃에서 990℃의 온도에서 SiC 버퍼층(씨앗층)을 성장시킨 다음 그 위에 In(x)Ga(1-x)N (0<x≤1) 층을 성장시키는 기술이 기재되어 있다. 바람직하게는 n형 3족 질화물 반도체층(300)의 성장에 앞서 도핑되지 않는 GaN층이 성장되며, 이는 버퍼층(200)의 일부로 보아도 좋고, n형 3족 질화물 반도체층(300)의 일부로 보아도 좋다.The buffer layer 200 is intended to overcome the difference in lattice constant and thermal expansion coefficient between the dissimilar substrate 100 and the group III nitride semiconductor, and US Pat. A technique for growing an AlN buffer layer having a thickness of US Pat. No. 5,290,393 describes Al (x) Ga (1-x) N having a thickness of 10 kPa to 5000 kPa at a temperature of 200 to 900 C on a sapphire substrate. (0 ≦ x <1) A technique for growing a buffer layer is described, and US Patent Publication No. 2006/154454 discloses growing a SiC buffer layer (seed layer) at a temperature of 600 ° C. to 990 ° C., followed by In (x Techniques for growing a Ga (1-x) N (0 <x≤1) layer are described. Preferably, the undoped GaN layer is grown prior to the growth of the n-type Group III nitride semiconductor layer 300, which may be viewed as part of the buffer layer 200 or as part of the n-type Group III nitride semiconductor layer 300. .
n형 3족 질화물 반도체층(300)은 적어도 n측 전극(800)이 형성된 영역(n형 컨택층)이 불순물로 도핑되며, n형 컨택층은 바람직하게는 GaN로 이루어지고, Si으로 도핑된다. 미국특허 제5,733,796호에는 Si과 다른 소스 물질의 혼합비를 조절함으로써 원하는 도핑농도로 n형 컨택층을 도핑하는 기술이 기재되어 있다.In the n-type group III nitride semiconductor layer 300, at least a region (n-type contact layer) in which the n-side electrode 800 is formed is doped with impurities, and the n-type contact layer is preferably made of GaN and doped with Si. . U. S. Patent No. 5,733, 796 describes a technique for doping an n-type contact layer to a desired doping concentration by controlling the mixing ratio of Si and other source materials.
활성층(400)은 전자와 정공의 재결합을 통해 광자(빛)를 생성하는 층으로서, 주로 In(x)Ga(1-x)N (0<x≤1)로 이루어지고, 하나의 양자우물층(single quantum well)이나 복수개의 양자우물층들(multi quantum wells)로 구성된다.The active layer 400 is a layer that generates photons (light) through recombination of electrons and holes, and is mainly composed of In (x) Ga (1-x) N (0 <x≤1), and one quantum well layer (single quantum wells) or multiple quantum wells.
p형 3족 질화물 반도체층(500)은 Mg과 같은 적절한 불순물을 이용해 도핑되며, 활성화(activation) 공정을 거쳐 p형 전도성을 가진다. 미국특허 제5,247,533호에는 전자빔 조사에 의해 p형 3족 질화물 반도체층을 활성화시키는 기술이 기재되어 있으며, 미국특허 제5,306,662호에는 400℃ 이상의 온도에서 열처리(annealing)함으로써 p형 3족 질화물 반도체층을 활성화시키는 기술이 기재되어 있고, 미국공개특허공보 제2006/157714호에는 p형 3족 질화물 반도체층 성장의 질소전구체로서 암모니아와 하이드라진계 소스 물질을 함께 사용함으로써 활성화 공정없이 p형 3족 질화물 반도체층이 p형 전도성을 가지게 하는 기술이 기재되어 있다.The p-type III-nitride semiconductor layer 500 is doped with an appropriate impurity such as Mg, and has an p-type conductivity through an activation process. U.S. Patent No. 5,247,533 describes a technique for activating a p-type group III nitride semiconductor layer by electron beam irradiation, and U.S. Patent No. 5,306,662 annealing at a temperature of 400 DEG C or higher to A technique for activating is described, and US Patent Publication No. 2006/157714 discloses a p-type III-nitride semiconductor layer without an activation process by using ammonia and a hydrazine-based source material together as a nitrogen precursor for growing the p-type III-nitride semiconductor layer. Techniques for having this p-type conductivity have been described.
p측 전극(600)은 p형 3족 질화물 반도체층(500) 전체로 전류가 잘 공급되도록 하기 위해 구비되는 것이며, 미국특허 제5,563,422호에는 p형 3족 질화물 반도체층의 거의 전면에 걸쳐서 형성되며 p형 3족 질화물 반도체층(500)과 오믹접촉하고 Ni과 Au로 이루어진 투광성 전극(light-transmitting electrode)에 관한 기술이 기재되어 있으며, 미국특허 제6,515,306호에는 p형 3족 질화물 반도체층 위에 n형 초격자층을 형성한 다음 그 위에 ITO(Indium Tin Oxide)로 이루어진 투광성 전극을 형성한 기술이 기재되어 있다.The p-side electrode 600 is provided to supply a good current to the entire p-type group III nitride semiconductor layer 500. US Patent No. 5,563,422 is formed over almost the entire surface of the p-type group III nitride semiconductor layer. A light-transmitting electrode made of Ni and Au in ohmic contact with the p-type III-nitride semiconductor layer 500 is described. US Pat. No. 6,515,306 discloses n on the p-type III-nitride semiconductor layer. A technique is described in which a type superlattice layer is formed and then a translucent electrode made of indium tin oxide (ITO) is formed thereon.
한편, p측 전극(600)이 빛을 투과시키지 못하도록, 즉 빛을 기판 측으로 반사하도록 두꺼운 두께를 가지게 형성할 수 있는데, 이러한 기술을 플립칩(flip chip) 기술이라 한다. 미국특허 제6,194,743호에는 20nm 이상의 두께를 가지는 Ag 층, Ag 층을 덮는 확산 방지층, 그리고 확산 방지층을 덮는 Au와 Al으로 이루어진 본딩 층을 포함하는 전극 구조에 관한 기술이 기재되어 있다.On the other hand, the p-side electrode 600 may be formed to have a thick thickness so as not to transmit light, that is, to reflect the light toward the substrate side, this technique is referred to as flip chip (flip chip) technology. U. S. Patent No. 6,194, 743 describes a technique relating to an electrode structure including an Ag layer having a thickness of 20 nm or more, a diffusion barrier layer covering the Ag layer, and a bonding layer made of Au and Al covering the diffusion barrier layer.
p측 본딩 패드(700)와 n측 전극(800)은 전류의 공급과 외부로의 와이어 본딩을 위한 것이며, 미국특허 제5,563,422호에는 n측 전극을 Ti과 Al으로 구성한 기술이 기재되어 있다.The p-side bonding pad 700 and the n-side electrode 800 are for supplying current and wire bonding to the outside, and US Patent No. 5,563,422 describes a technique in which the n-side electrode is composed of Ti and Al.
보호막(900)은 이산화규소와 같은 물질로 형성되며, 생략될 수도 있다.The passivation layer 900 is formed of a material such as silicon dioxide and may be omitted.
한편, n형 3족 질화물 반도체층(300)이나 p형 3족 질화물 반도체층(500)은 단일의 층이나 복수개의 층으로 구성될 수 있으며, 최근에는 레이저 또는 습식 식각을 통해 기판(100)을 3족 질화물 반도체층들로부터 분리하여 수직형 발광소자를 제조하는 기술이 도입되고 있다.Meanwhile, the n-type III-nitride semiconductor layer 300 or the p-type III-nitride semiconductor layer 500 may be composed of a single layer or a plurality of layers, and recently, the substrate 100 may be formed by laser or wet etching. A technique for manufacturing a vertical light emitting device by separating from group III nitride semiconductor layers has been introduced.
그러나, 이러한 발광소자는 p측 본딩 패드(700)에 와이어 본딩을 할 때, p측 본딩 패드(700)가 발광소자로부터 떨어져 나가는(peeling off) 문제가 발생할 수 있다.However, such a light emitting device may cause a problem that the p-side bonding pad 700 is peeled off from the light emitting device when wire bonding to the p-side bonding pad 700.
이에 대하여 '발명의 실시를 위한 구체적인 내용'의 후단에 기술한다.This is described later in the section titled 'Details of the Invention.'
여기서는, 본 개시의 전체적인 요약(Summary)이 제공되며, 이것이 본 개시의 외연을 제한하는 것으로 이해되어서는 아니된다(This section provides a general summary of the disclosure and is not a comprehensive disclosure of its full scope or all of its features).This section provides a general summary of the disclosure and is not a comprehensive disclosure of its full scope or all, provided that this is a summary of the disclosure. of its features).
본 개시에 따른 일 태양에 의하면(According to one aspect of the present disclosure), 제1 전도성을 지니는 제1 3족 질화물 반도체층, 제1 전도성과 다른 제2 전도성을 지니는 제2 3족 질화물 반도체층, 그리고 제1 3족 질화물 반도체층과 제2 3족 질화물 반도체층 사이에 위치하며, 전자와 정공의 재결합을 통해 빛을 생성하는 활성층을 구비하는 복수개의 3족 질화물 반도체층; 복수개의 3족 질화물 반도체층과 전기적으로 연결되는 본딩 패드; 제2 3족 질화물 반도체층 상에 형성되며 제2 반도체층이 노출되도록 복수개의 개구부를 구비하는 투광성 전극; 복수개의 개구부의 적어도 일부를 메우도록 형성되는 제1 전극; 그리고, 제1 3족 질화물 반도체층 상에 형성되는 제2 전극;을 포함하고 본딩 패드 및 제1 전극은 전기적으로 연결되어 있는 것을 특징으로 하는 3족 질화물 반도체 발광소자가 제공된다.According to one aspect of the present disclosure, According to one aspect of the present disclosure, a first group III nitride semiconductor layer having a first conductivity, a second group III nitride semiconductor layer having a second conductivity different from the first conductivity, And a plurality of group III nitride semiconductor layers positioned between the first group III nitride semiconductor layers and the second group III nitride semiconductor layers, the plurality of Group III nitride semiconductor layers including an active layer that generates light through recombination of electrons and holes; Bonding pads electrically connected to the plurality of Group III nitride semiconductor layers; A translucent electrode formed on the second group III nitride semiconductor layer and having a plurality of openings to expose the second semiconductor layer; A first electrode formed to fill at least a portion of the plurality of openings; And a second electrode formed on the first group III nitride semiconductor layer, wherein the bonding pad and the first electrode are electrically connected to each other.
이에 대하여 '발명의 실시를 위한 구체적인 내용'의 후단에 기술한다.This is described later in the section titled 'Details of the Invention.'
도 1은 종래의 3족 질화물 반도체 발광소자의 일 예를 나타내는 도면,1 is a view showing an example of a conventional group III nitride semiconductor light emitting device,
도 2 및 도 3은 본 개시에 따른 3족 질화물 반도체 발광소자의 일 예를 나타내는 도면,2 and 3 are views showing an example of a group III nitride semiconductor light emitting device according to the present disclosure;
도 4는 본 개시에 따른 3족 질화물 반도체 발광소자의 다른 예를 나타낸 도면,4 is a view showing another example of a group III nitride semiconductor light emitting device according to the present disclosure;
도 5 및 도 6은 본 개시에 따른 3족 질화물 반도체 발광소자의 또 다른 예를 나타낸 도면,5 and 6 are views showing another example of the group III nitride semiconductor light emitting device according to the present disclosure;
도 7은 본 개시에 따른 3족 질화물 반도체 발광소자의 또 다른 예를 나타낸 도면.7 is a view showing another example of a group III nitride semiconductor light emitting device according to the present disclosure.
이하, 본 개시를 첨부된 도면을 참고로 하여 자세하게 설명한다(The present disclosure will now be described in detail with reference to the accompanying drawing(s)).The present disclosure will now be described in detail with reference to the accompanying drawing (s).
도 2 및 도 3은 본 개시에 따른 3족 질화물 반도체 발광소자의 일 예를 나타내는 도면으로서, 3족 질화물 반도체 발광소자는 기판(10)과, 기판(10) 위에 형성되는 버퍼층(11)과, 버퍼층(11) 위에 형성되는 제1 3족 질화물 반도체층(12)과, 제1 3족 질화물 반도체층(12) 위에 형성되고 전자와 정공의 재결합에 의해 빛을 생성하는 활성층(13)과, 활성층(13) 위에 형성되는 제2 3족 질화물 반도체층(14)과, 제2 3족 질화물 반도체층(14) 위에서 제1 개구부(21)를 가지도록 형성되는 투광성 전극(16)과, 제2 3족 질화물 반도체층(14) 위에 형성되는 본딩 패드(15) 및 제1 전극(17)과, 제2 3족 질화물 반도체층(14)과 활성층(13)이 식각되어 드러나는 제1 3족 질화물 반도체층(12) 위에 형성되는 제2 전극(20)을 포함한다.2 and 3 are views illustrating an example of a group III nitride semiconductor light emitting device according to the present disclosure. The group III nitride semiconductor light emitting device includes a substrate 10, a buffer layer 11 formed on the substrate 10, and A first group III nitride semiconductor layer 12 formed on the buffer layer 11, an active layer 13 formed on the first group III nitride semiconductor layer 12 to generate light by recombination of electrons and holes, and an active layer The second group III nitride semiconductor layer 14 formed on the (13), the translucent electrode 16 formed to have the first opening 21 on the second group III nitride semiconductor layer 14, and the second third The first group III nitride semiconductor layer in which the bonding pad 15 and the first electrode 17 formed on the group nitride semiconductor layer 14, and the second group III nitride semiconductor layer 14 and the active layer 13 are etched and exposed. The second electrode 20 is formed on the (12).
제1 3족 질화물 반도체층(12)과 제2 3족 질화물 반도체층(14)은 서로 다른 도전성을 갖도록 구비되는데 본 실시예에서는 제1 3족 질화물 반도체층(12)은 n형 반도체층, 제2 3족 질화물 반도체층(14)은 p형 반도체층으로 형성하였다.The first group III nitride semiconductor layer 12 and the second group III nitride semiconductor layer 14 are provided to have different conductivity. In this embodiment, the first group III nitride semiconductor layer 12 is formed of an n-type semiconductor layer, The Group 2 III nitride semiconductor layer 14 was formed of a p-type semiconductor layer.
제2 3족 질화물 반도체층(14) 형성 후, 도 2에 개시된 바와 같이, 전자빔 증착기(E-beam evaporator)를 이용하여 제2 3족 질화물 반도체층(14) 위에 제1 개구부(21)가 형성되도록 투광성 전극(16)을 적층한다. 본 개시에서 제1 개구부(21)는 5 내지 10 마이크로미터의 지름을 가지며, 투광성 전극(16)의 전면이 아닌 제1 전극(17)이 형성될 위치에 형성된다. 또한 제1 개구부(21)는 제2 3족 질화물 반도체층(14)과 제1 전극(17)이 접하는 면적을 증가시키기 위한 것으로 제1 개구부(21)의 형상 및 복수의 제1 개구부(21)의 배열 형태는 특별히 제한되지 않는다.After the formation of the second group III nitride semiconductor layer 14, as shown in FIG. 2, the first opening 21 is formed on the second group III nitride semiconductor layer 14 using an E-beam evaporator. The translucent electrode 16 is laminated as much as possible. In the present disclosure, the first opening 21 has a diameter of 5 to 10 micrometers and is formed at a position where the first electrode 17 is to be formed instead of the front surface of the translucent electrode 16. In addition, the first opening 21 is for increasing the area where the second group III nitride semiconductor layer 14 and the first electrode 17 contact each other, and the shape of the first opening 21 and the plurality of first openings 21 are increased. The arrangement form of is not particularly limited.
그리고 본 실시예에서는 제1 개구부(21) 및 제1 전극(17)이 본딩 패드(15)로부터 제2 전극(20)을 향해 뻗어있는 구조가 기재되어 있으나 제1 전극(17)의 형태는 이에 한정되지 않으며 전류확산을 원활히 하기 위해 복수의 가지전극으로 뻗어나가는 형태로 형성될 수 있다.In this embodiment, a structure in which the first opening 21 and the first electrode 17 extend from the bonding pad 15 toward the second electrode 20 is described, but the shape of the first electrode 17 is The present invention is not limited thereto and may be formed to extend to a plurality of branch electrodes in order to facilitate current diffusion.
이후, 25℃의 상온에서 6×10-6torr의 압력으로 Cr, Ni, Au층들을 순차적으로 적층하여 본딩 패드(15) 및 제1 전극(17)을 동시에 형성하는데, 이는 별도의 공정을 통해 형성될 수도 있다. 노출된 제2 3족 질화물 반도체층(14) 위에 Cr, Ni, Au층들을 적층하여 제1 개구부(21)를 메운 다음, 투광성 전극(16) 위에서 본딩 패드(15) 및 제1 전극(17)이 전기적으로 연결되도록 형성된다. 본 개시에서 제1 전극(17)은 제1 개구부(21)를 전부 메우도록 형성되었으나 일부를 메우도록 형성될 수도 있다. 또한 본 개시에서 본딩 패드(15)는 제2 3족 질화물 반도체층(14)에 접하도록 형성되었다.Subsequently, Cr, Ni and Au layers are sequentially stacked at a pressure of 6 × 10 −6 torr at a room temperature of 25 ° C. to simultaneously form a bonding pad 15 and a first electrode 17. It may be formed. Cr, Ni, and Au layers are stacked on the exposed second group III nitride semiconductor layer 14 to fill the first opening 21, and then the bonding pad 15 and the first electrode 17 are disposed on the light transmissive electrode 16. It is formed to be electrically connected. In the present disclosure, the first electrode 17 may be formed to fill all of the first openings 21, but may be formed to fill a part of the first electrode 17. In addition, in the present disclosure, the bonding pad 15 is formed to contact the second group III nitride semiconductor layer 14.
이후, 3족 질화물 반도체 발광소자에 전기를 공급하기 위한 와이어가 본딩된다. 본딩 패드(15)는 와이어 본딩을 할 때, 또는 와이어 본딩이 이루어진 후 와이어에 의해 당겨지게 되어 패드가 떨어지는 필링이 발생할 수 있으나, 상기와 같이 제1 개구부(21)를 메우도록 형성된 제1 전극(17)으로 인하여 제2 3족 질화물 반도체층(14)과 접촉하는 면적이 넓어지므로 접착력이 향상되어 이러한 현상을 개선할 수 있다. Thereafter, a wire for supplying electricity to the group III nitride semiconductor light emitting device is bonded. The bonding pad 15 may be pulled by the wire when wire bonding or after the wire bonding is performed, and thus peeling may occur. However, as described above, the bonding pad 15 may include a first electrode formed to fill the first opening 21. 17) the area in contact with the second group III nitride semiconductor layer 14 is widened, so that the adhesive force can be improved to improve this phenomenon.
도 4는 본 개시에 따른 3족 질화물 반도체 발광소자의 다른 예를 나타낸 도면으로서, 도 3과 달리 투광성 전극(16) 위에 본딩 패드(15)가 형성되고 본딩 패드(15)는 제1 전극(17)과 접촉하여 제2 3족 질화물 반도체층(14)과 전기적으로 연결된다.4 is a view illustrating another example of the group III nitride semiconductor light emitting device according to the present disclosure. Unlike FIG. 3, a bonding pad 15 is formed on the light transmissive electrode 16, and the bonding pad 15 is formed of the first electrode 17. ) Is electrically connected to the second group III nitride semiconductor layer 14.
도 5 및 도 6은 본 개시에 따른 3족 질화물 반도체 발광소자의 또 다른 예를 나타낸 도면으로서, 본딩 패드(15)가 형성될 영역에 제2 개구부(18)가 형성되어 제2 3족 질화물 반도체층(14)이 노출되도록 투광성 전극(16)이 형성된다. 본 실시예에서 상기 영역에 형성되는 제2 개구부(18)는 본딩 패드(15)의 크기를 고려하여 원의 지름을 110 내지 120 마이크로미터 내외로 설정하였고 제1 전극(17)이 형성될 영역의 제1 개구부(21)는 도 3에서와 같이 5 내지 10 마이크로미터의 지름을 갖도록 형성하였으나 제1 개구부(21) 및 제2 개구부(18)의 형태, 크기가 이에 한정되는 것은 아니다.5 and 6 illustrate another example of a group III nitride semiconductor light emitting device according to the present disclosure, in which a second opening 18 is formed in a region where a bonding pad 15 is to be formed, thereby forming a second group III nitride semiconductor. The light transmissive electrode 16 is formed such that the layer 14 is exposed. In the present embodiment, the diameter of the circle is set to about 110 to 120 micrometers in consideration of the size of the bonding pad 15, and the second opening 18 formed in the region is formed in the region where the first electrode 17 is to be formed. Although the first opening 21 is formed to have a diameter of 5 to 10 micrometers as shown in FIG. 3, the shape and size of the first opening 21 and the second opening 18 are not limited thereto.
이후, 25℃의 상온에서 6×10-6torr의 압력으로 Cr, Ni, Au층들을 순차적으로 적층하는데 본딩 패드(15)는 제2 개구부(18)보다 작은 크기(예: 100 마이크로미터)로 형성하고 본딩 패드(15)와 투광성 전극(16)은 도 5에 나타난 바와 같이 브릿지 형상으로 형성된 제3 전극(19)에 의해서 전기적으로 연결된다. 제3 전극(19)은 복수개 형성될 수 있으며, 전류의 원활한 공급을 위하여 방사형으로 형성되는 것이 바람직하다. 그리고 본 실시예에서 본딩 패드(15), 제1 전극(17) 및 제3 전극(19)은 동시에 형성되는데 별도의 공정을 통해 형성될 수도 있다.Subsequently, Cr, Ni, and Au layers are sequentially stacked at a pressure of 6 × 10 −6 torr at room temperature of 25 ° C., and the bonding pad 15 is smaller than the second opening 18 (eg, 100 micrometers). And the bonding pad 15 and the translucent electrode 16 are electrically connected by a third electrode 19 formed in a bridge shape as shown in FIG. 5. The third electrode 19 may be formed in plural, and it is preferable that the third electrode 19 be radially formed to smoothly supply current. In the present embodiment, the bonding pad 15, the first electrode 17, and the third electrode 19 are simultaneously formed, but may be formed through separate processes.
본딩 패드(15)의 외곽 테두리가 투광성 전극(16)과 접촉되어 형성되는 경우, 와이어 본딩 시, 또는 본딩 후 투광성 전극(16)과 접촉력이 약하여 본딩 패드(15)의 외곽 테두리 부분이 떨어지면서 필링(peeling)의 시발점(trigger)이 되며, 이로 인해 본딩 패드(15)와 투광성 전극(16)이 전반적으로 분리되어 필링을 유발할 수 있으나 상기와 같이 본딩 패드(15) 및 투광성 전극(16)이 격리되어 형성되고 제3 전극(19)에 의해 전기적으로 연결됨으로써 본딩 패드(15)가 제2 3족 질화물 반도체층(14)과 접촉되는 면적이 증가하여 접착력이 향상되므로 이러한 현상을 개선할 수 있다.When the outer edge of the bonding pad 15 is formed in contact with the translucent electrode 16, the contact edge of the bonding pad 15 is weak when the wire is bonded or after bonding, so that the outer edge of the bonding pad 15 is peeled off and peeled. It is a trigger of the peeling, which may cause the bonding pad 15 and the translucent electrode 16 to be separated from each other to cause peeling, but the bonding pad 15 and the translucent electrode 16 are isolated as described above. Since the bonding pad 15 is formed and electrically connected by the third electrode 19 to increase the area in which the bonding pad 15 is in contact with the second group III nitride semiconductor layer 14, the adhesive force may be improved.
도 7은 본 개시에 따른 3족 질화물 반도체 발광소자의 또 다른 예를 나타낸 도면으로서, 제2 3족 질화물 반도체층(14) 위에 제1 개구부(21)가 직사각형의 형상으로 형성되고 제1 전극(17)이 본딩 패드(15)로부터 제2 전극(20)을 향해 뻗어있는 형태로 제1 개구부(21)의 일부를 메우도록 형성되어 있다. 제1 개구부(21)가 전류의 흐름(화살표 방향)에 대해 장벽을 형성함으로써 소자의 가운데로 전류가 집중되는 현상을 방지하여 전체적인 전류확산을 원활히 할 수 있게 된다.FIG. 7 is a view illustrating another example of the group III nitride semiconductor light emitting device according to the present disclosure. The first opening 21 is formed in a rectangular shape on the second group III nitride semiconductor layer 14, and the first electrode ( 17 is formed to fill a part of the first opening 21 in a form extending from the bonding pad 15 toward the second electrode 20. The first opening 21 forms a barrier against the flow of current (arrow direction), thereby preventing the current from being concentrated in the center of the device, thereby facilitating overall current diffusion.
상기 실시예는 본 개시의 기술적 사상을 구체적으로 설명하기 위한 일례로서, 본 개시는 이에 한정되지 않으며, 다양한 형태의 변형이 가능하고 이러한 기술적 사상의 여러 실시 형태가 모두 본 개시의 보호범위에 속함은 당연하다.The above embodiment is an example for describing the technical idea of the present disclosure in detail, and the present disclosure is not limited thereto, and various modifications may be made, and various embodiments of the technical idea belong to the protection scope of the present disclosure. Of course.
이하 본 개시의 다양한 실시 형태에 대하여 설명한다.Hereinafter, various embodiments of the present disclosure will be described.
(1) 제1 전도성을 지니는 제1 3족 질화물 반도체층, 제1 전도성과 다른 제2 전도성을 지니는 제2 3족 질화물 반도체층, 그리고 제1 3족 질화물 반도체층과 제2 3족 질화물 반도체층 사이에 위치하며, 전자와 정공의 재결합을 통해 빛을 생성하는 활성층을 구비하는 복수개의 3족 질화물 반도체층; 복수개의 3족 질화물 반도체층과 전기적으로 연결되는 본딩 패드; 제2 3족 질화물 반도체층 상에 형성되며 제2 반도체층이 노출되도록 복수개의 개구부를 구비하는 투광성 전극; 복수개의 개구부의 적어도 일부를 메우도록 형성되는 제1 전극;그리고, 제1 3족 질화물 반도체층 상에 형성되는 제2 전극;을 포함하고 본딩 패드 및 제1 전극은 전기적으로 연결되어 있는 것을 특징으로 하는 3족 질화물 반도체 발광소자.(1) a first group III nitride semiconductor layer having a first conductivity, a second group III nitride semiconductor layer having a second conductivity different from the first conductivity, and a first group III nitride semiconductor layer and a second group III nitride semiconductor layer A plurality of group III nitride semiconductor layers positioned between and having an active layer generating light through recombination of electrons and holes; Bonding pads electrically connected to the plurality of Group III nitride semiconductor layers; A translucent electrode formed on the second group III nitride semiconductor layer and having a plurality of openings to expose the second semiconductor layer; A first electrode formed to fill at least a portion of the plurality of openings; and a second electrode formed on the first group III nitride semiconductor layer; wherein the bonding pad and the first electrode are electrically connected to each other. A group III nitride semiconductor light emitting device.
(2) 본딩 패드는 투광성 전극의 위에 형성되는 것을 특징으로 하는 3족 질화물 반도체 발광소자.(2) A group III nitride semiconductor light emitting element, wherein the bonding pad is formed on the light transmissive electrode.
(3) 본딩 패드 및 투광성 전극을 전기적으로 연결하는 제3 전극;을 포함하는 것을 특징으로 하는 3족 질화물 반도체 발광소자.And (3) a third electrode electrically connecting the bonding pad and the translucent electrode.
(4) 제1 전극은 본딩 패드로부터 제2 전극을 향해 뻗어있는 것을 특징으로 하는 3족 질화물 반도체 발광소자.(4) A group III nitride semiconductor light emitting element, wherein the first electrode extends from the bonding pad toward the second electrode.
(5) 제1 전극은 복수개의 개구부를 전부 메우도록 형성되는 것을 특징으로 하는 3족 질화물 반도체 발광소자.(5) A group III nitride semiconductor light emitting element, wherein the first electrode is formed so as to fill all of the plurality of openings.
본 개시에 따른 하나의 반도체 발광소자에 의하면, 본딩 패드가 와이어 본딩 시 발광소자로부터 떨어져 나가는 것을 개선하여 수율을 향상시킬 수 있다.According to one semiconductor light emitting device according to the present disclosure, it is possible to improve the yield by improving the bonding pad is separated from the light emitting device during wire bonding.
본 개시에 따른 다른 반도체 발광소자에 의하면, 본딩 패드의 견고한 접착이 가능하며, 발광소자에 전류가 원활하게 공급될 수 있다.According to another semiconductor light emitting device according to the present disclosure, it is possible to firmly bond the bonding pads, and the current may be smoothly supplied to the light emitting device.

Claims (6)

  1. 제1 전도성을 지니는 제1 3족 질화물 반도체층, 제1 전도성과 다른 제2 전도성을 지니는 제2 3족 질화물 반도체층, 그리고 제1 3족 질화물 반도체층과 제2 3족 질화물 반도체층 사이에 위치하며, 전자와 정공의 재결합을 통해 빛을 생성하는 활성층을 구비하는 복수개의 3족 질화물 반도체층;A first group III nitride semiconductor layer having a first conductivity, a second group III nitride semiconductor layer having a second conductivity different from the first conductivity, and located between the first group III nitride semiconductor layer and the second group III nitride semiconductor layer A plurality of group III nitride semiconductor layers having an active layer that generates light through recombination of electrons and holes;
    복수개의 3족 질화물 반도체층과 전기적으로 연결되는 본딩 패드;Bonding pads electrically connected to the plurality of Group III nitride semiconductor layers;
    제2 3족 질화물 반도체층 상에 형성되며 제2 반도체층이 노출되도록 복수개의 개구부를 구비하는 투광성 전극; A translucent electrode formed on the second group III nitride semiconductor layer and having a plurality of openings to expose the second semiconductor layer;
    복수개의 개구부의 적어도 일부를 메우도록 형성되는 제1 전극; 그리고,A first electrode formed to fill at least a portion of the plurality of openings; And,
    제1 3족 질화물 반도체층 상에 형성되는 제2 전극;을 포함하고And a second electrode formed on the first group III nitride semiconductor layer.
    본딩 패드 및 제1 전극은 전기적으로 연결되어 있는 것을 특징으로 하는 3족 질화물 반도체 발광소자.The group III nitride semiconductor light emitting device of claim 3, wherein the bonding pad and the first electrode are electrically connected to each other.
  2. 청구항 1에 있어서,The method according to claim 1,
    본딩 패드는 투광성 전극의 위에 형성되는 것을 특징으로 하는 3족 질화물 반도체 발광소자.A bonding pad is a group III nitride semiconductor light emitting device, characterized in that formed on the light transmitting electrode.
  3. 청구항 1에 있어서,The method according to claim 1,
    본딩 패드 및 투광성 전극을 전기적으로 연결하는 제3 전극;을 포함하는 것을 특징으로 하는 3족 질화물 반도체 발광소자.And a third electrode electrically connecting the bonding pad and the light transmissive electrode.
  4. 청구항 1에 있어서,The method according to claim 1,
    제1 전극은 본딩 패드로부터 제2 전극을 향해 뻗어있는 것을 특징으로 하는 3족 질화물 반도체 발광소자.The group III nitride semiconductor light emitting device of claim 1, wherein the first electrode extends from the bonding pad toward the second electrode.
  5. 청구항 1에 있어서,The method according to claim 1,
    제1 전극은 복수개의 개구부를 전부 메우도록 형성되는 것을 특징으로 하는 3족 질화물 반도체 발광소자.The group III nitride semiconductor light emitting device according to claim 1, wherein the first electrode is formed to completely fill the plurality of openings.
  6. 청구항 1에 있어서,The method according to claim 1,
    본딩 패드는 투광성 전극의 위에 형성되고,Bonding pads are formed on the translucent electrode,
    본딩 패드 및 투광성 전극을 전기적으로 연결하는 제2 전극;을 포함하며,And a second electrode electrically connecting the bonding pad and the light transmissive electrode.
    제1 전극은 본딩 패드로부터 제2 전극을 향해 뻗어있으며,The first electrode extends from the bonding pad toward the second electrode,
    제1 전극은 복수개의 개구부를 전부 메우도록 형성되는 것을 특징으로 하는 3족 질화물 반도체 발광소자.The group III nitride semiconductor light emitting device according to claim 1, wherein the first electrode is formed to completely fill the plurality of openings.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103178183A (en) * 2011-12-26 2013-06-26 Lg伊诺特有限公司 Light emitting device

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101223226B1 (en) * 2011-01-20 2013-01-31 갤럭시아포토닉스 주식회사 Light Emitting Diode having an open part and its Light Emitting Diode package
KR101969307B1 (en) * 2012-09-07 2019-04-17 삼성전자주식회사 Semiconductor light emitting device
KR102070088B1 (en) 2013-06-17 2020-01-29 삼성전자주식회사 Semiconductor light emitting device
WO2015170848A1 (en) * 2014-05-08 2015-11-12 엘지이노텍 주식회사 Light emitting device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100452751B1 (en) * 2003-06-03 2004-10-15 삼성전기주식회사 III-Nitride compound semiconductor light emitting device with mesh type electrode
KR20050076140A (en) * 2004-01-19 2005-07-26 삼성전기주식회사 Flip chip type nitride semiconductor light emitting diode
JP2006128227A (en) * 2004-10-26 2006-05-18 Mitsubishi Cable Ind Ltd Nitride semiconductor light emitting element
JP2006237574A (en) * 2005-01-31 2006-09-07 Mitsubishi Cable Ind Ltd GaN-BASED LIGHT EMITTING DIODE
KR20090044311A (en) * 2007-10-31 2009-05-07 한국광기술원 Light emitting diode and its manufacturing method
KR20090119258A (en) * 2008-05-15 2009-11-19 주식회사 에피밸리 Semiconductor light emitting device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100452751B1 (en) * 2003-06-03 2004-10-15 삼성전기주식회사 III-Nitride compound semiconductor light emitting device with mesh type electrode
KR20050076140A (en) * 2004-01-19 2005-07-26 삼성전기주식회사 Flip chip type nitride semiconductor light emitting diode
JP2006128227A (en) * 2004-10-26 2006-05-18 Mitsubishi Cable Ind Ltd Nitride semiconductor light emitting element
JP2006237574A (en) * 2005-01-31 2006-09-07 Mitsubishi Cable Ind Ltd GaN-BASED LIGHT EMITTING DIODE
KR20090044311A (en) * 2007-10-31 2009-05-07 한국광기술원 Light emitting diode and its manufacturing method
KR20090119258A (en) * 2008-05-15 2009-11-19 주식회사 에피밸리 Semiconductor light emitting device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103178183A (en) * 2011-12-26 2013-06-26 Lg伊诺特有限公司 Light emitting device
US10128412B2 (en) 2011-12-26 2018-11-13 Lg Innotek Co., Ltd. Light emitting device

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