WO2010047482A2 - Group iii nitride semiconductor light emitting device - Google Patents

Group iii nitride semiconductor light emitting device Download PDF

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Publication number
WO2010047482A2
WO2010047482A2 PCT/KR2009/005707 KR2009005707W WO2010047482A2 WO 2010047482 A2 WO2010047482 A2 WO 2010047482A2 KR 2009005707 W KR2009005707 W KR 2009005707W WO 2010047482 A2 WO2010047482 A2 WO 2010047482A2
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nitride semiconductor
iii nitride
substrate
group iii
light emitting
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PCT/KR2009/005707
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French (fr)
Korean (ko)
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WO2010047482A3 (en
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김창태
나민규
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주식회사 에피밸리
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Priority to CN200980142327XA priority Critical patent/CN102217103A/en
Priority to US12/647,750 priority patent/US20100102352A1/en
Publication of WO2010047482A2 publication Critical patent/WO2010047482A2/en
Publication of WO2010047482A3 publication Critical patent/WO2010047482A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers

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  • the present disclosure relates to a group III nitride semiconductor light emitting device as a whole, and more particularly, to a group III nitride semiconductor light emitting device in which scattering regions are formed inside a substrate to improve light extraction efficiency.
  • the group III nitride semiconductor light emitting device has a compound semiconductor layer of Al (x) Ga (y) In (1-xy) N (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1).
  • Means a light emitting device, such as a light emitting diode comprising a and does not exclude the inclusion of a material consisting of elements of other groups such as SiC, SiN, SiCN, CN or a semiconductor layer of these materials.
  • FIG. 1 is a view illustrating an example of a conventional Group III nitride semiconductor light emitting device, wherein the Group III nitride semiconductor light emitting device is grown on the substrate 100, the buffer layer 200 grown on the substrate 100, and the buffer layer 200.
  • the p-side electrode 600 formed on the group nitride semiconductor layer 500, the p-side bonding pad 700 formed on the p-side electrode 600, the p-type group III nitride semiconductor layer 500 and the active layer 400 are formed.
  • the n-side electrode 800 and the passivation layer 900 are formed on the n-type group III nitride semiconductor layer 300 exposed by mesa etching.
  • a GaN-based substrate is used as the homogeneous substrate, and a sapphire substrate, a SiC substrate, or a Si substrate is used as the heterogeneous substrate. Any substrate may be used as long as the group III nitride semiconductor layer can be grown.
  • the n-side electrode 800 may be formed on the SiC substrate side.
  • Group III nitride semiconductor layers grown on the substrate 100 are mainly grown by MOCVD (organic metal vapor growth method).
  • the buffer layer 200 is intended to overcome the difference in lattice constant and thermal expansion coefficient between the dissimilar substrate 100 and the group III nitride semiconductor, and US Pat.
  • a technique for growing an AlN buffer layer having a thickness of US Pat. No. 5,290,393 describes Al (x) Ga (1-x) N having a thickness of 10 kPa to 5000 kPa at a temperature of 200 to 900 C on a sapphire substrate. (0 ⁇ x ⁇ 1)
  • a technique for growing a buffer layer is described, and US Patent Publication No. 2006/154454 discloses growing a SiC buffer layer (seed layer) at a temperature of 600 ° C.
  • the undoped GaN layer is grown prior to the growth of the n-type Group III nitride semiconductor layer 300, which may be viewed as part of the buffer layer 200 or as part of the n-type Group III nitride semiconductor layer 300. .
  • n-type contact layer In the n-type group III nitride semiconductor layer 300, at least a region (n-type contact layer) in which the n-side electrode 800 is formed is doped with impurities, and the n-type contact layer is preferably made of GaN and doped with Si. .
  • U. S. Patent No. 5,733, 796 describes a technique for doping an n-type contact layer to a desired doping concentration by controlling the mixing ratio of Si and other source materials.
  • the active layer 400 is a layer that generates photons (light) through recombination of electrons and holes, and is mainly composed of In (x) Ga (1-x) N (0 ⁇ x ⁇ 1), and one quantum well layer (single quantum wells) or multiple quantum wells.
  • the p-type III-nitride semiconductor layer 500 is doped with an appropriate impurity such as Mg, and has an p-type conductivity through an activation process.
  • U.S. Patent No. 5,247,533 describes a technique for activating a p-type group III nitride semiconductor layer by electron beam irradiation, and U.S. Patent No. 5,306,662 annealing the p-type Group III nitride semiconductor layer at a temperature of 400 ⁇ ⁇ or higher. A technique for activating is described, and US Patent Publication No.
  • 2006/157714 discloses a p-type III-nitride semiconductor layer without an activation process by using ammonia and a hydrazine-based source material together as a nitrogen precursor for growth of the p-type III-nitride semiconductor layer. Techniques for having this p-type conductivity have been described.
  • the p-side electrode 600 is provided to supply a good current to the entire p-type group III nitride semiconductor layer 500.
  • US Patent No. 5,563,422 is formed over almost the entire surface of the p-type group III nitride semiconductor layer.
  • a light-transmitting electrode made of Ni and Au in ohmic contact with the p-type III-nitride semiconductor layer 500 is described.
  • US Pat. No. 6,515,306 discloses n on the p-type III-nitride semiconductor layer. A technique is described in which a type superlattice layer is formed and then a translucent electrode made of indium tin oxide (ITO) is formed thereon.
  • ITO indium tin oxide
  • the p-side electrode 600 may be formed to have a thick thickness so as not to transmit light, that is, to reflect the light toward the substrate side, this technique is referred to as flip chip (flip chip) technology.
  • U. S. Patent No. 6,194, 743 describes a technique relating to an electrode structure including an Ag layer having a thickness of 20 nm or more, a diffusion barrier layer covering the Ag layer, and a bonding layer made of Au and Al covering the diffusion barrier layer.
  • the p-side bonding pad 700 and the n-side electrode 800 are for supplying current and wire bonding to the outside, and US Patent No. 5,563,422 describes a technique in which the n-side electrode is composed of Ti and Al.
  • the passivation layer 900 is formed of a material such as silicon dioxide and may be omitted.
  • the n-type III-nitride semiconductor layer 300 or the p-type III-nitride semiconductor layer 500 may be composed of a single layer or a plurality of layers, and recently, the substrate 100 may be formed by laser or wet etching. A technique for manufacturing a vertical light emitting device by separating from group III nitride semiconductor layers has been introduced.
  • FIG. 2 is a view showing an example of a semiconductor light emitting device disclosed in US Patent No. 6,657,236.
  • the external quantum is formed by scattering light by forming a rough surface 310 having different refractive indices in a group III nitride semiconductor layer 300. Techniques for improving efficiency have been described.
  • FIG. 3 is a view showing another example of the semiconductor light emitting device disclosed in US Patent No. 6,657,236, which forms a material layer 120 (SiO 2 or nitride layer) having a different refractive index on the substrate 100 on which the protrusions 110 are formed. Then, a technique of increasing the external quantum efficiency by forming the group III nitride semiconductor layer 300 thereon is described.
  • FIG. 4 is a view showing an example of a method of manufacturing a semiconductor light emitting device disclosed in US Patent Publication No. 2008/121906.
  • a groove is first formed on the substrate 100 using a laser.
  • a technique is described that facilitates separation into individual chips by forming 130 and then further forming grooves 140.
  • the laser is irradiated to the substrate 100 from the opposite side of the substrate 100, that is, the side where the groove 130 is formed, and by matching the focus of the laser to the area where the groove 140 is formed 140 can be formed.
  • FIG. 5 is a view showing an example of a method for manufacturing a semiconductor light emitting device disclosed in Japanese Patent Laid-Open No. 11-163403. A laser is irradiated to form a processing deformed layer 110, and then a groove 130 is formed. To separate the chips into individual chips.
  • an substrate may include: a substrate having a scattering region formed therein; And a first group III nitride semiconductor layer formed on the substrate and having a first conductivity, a second group III nitride semiconductor layer formed on the first group III nitride semiconductor layer and having a second conductivity different from the first conductivity, and And a plurality of Group III nitride semiconductor layers positioned between the Group 1 III nitride semiconductor layer and the second Group III nitride semiconductor layer and having an active layer that generates light by recombination of electrons and holes.
  • a nitride semiconductor light emitting device is provided.
  • one group III nitride semiconductor light emitting device it is possible to improve the light extraction efficiency of the light emitting device.
  • the scattering region can be formed without being limited to the order of the processes.
  • FIG. 1 is a view showing an example of a conventional group III nitride semiconductor light emitting device
  • FIG. 2 is a view showing an example of a semiconductor light emitting device described in US Patent No. 6,657,236
  • FIG. 3 is a view showing another example of the semiconductor light emitting device described in US Patent No. 6,657,236;
  • FIG. 4 is a view showing an example of a method of manufacturing a semiconductor light emitting device disclosed in US Patent Publication No. 2008/121906;
  • FIG. 5 is a view showing an example of a method of manufacturing a semiconductor light emitting device disclosed in Japanese Patent Laid-Open No. 11-163403;
  • FIG. 6 is a view showing an example of a group III nitride semiconductor light emitting device according to the present disclosure
  • FIG. 7 is a view showing an example of a substrate provided in a group III nitride semiconductor light emitting device according to the present disclosure.
  • FIG. 8 is a view showing another example of a substrate provided in the group III nitride semiconductor light emitting device according to the present disclosure.
  • FIG. 9 is a view showing another example of a substrate provided in the group III nitride semiconductor light emitting device according to the present disclosure.
  • FIG. 10 is a view showing an example of a method of manufacturing a group III nitride semiconductor light emitting device according to the present disclosure
  • FIG. 13 is a photograph seen from above of a group III nitride semiconductor light-emitting device comprising a substrate processed according to this Experimental Example.
  • FIG. 13 is a photograph seen from above of a group III nitride semiconductor light-emitting device comprising a substrate processed according to this Experimental Example.
  • FIG. 6 is a diagram illustrating an example of a group III nitride semiconductor light emitting device according to the present disclosure, in which the group III nitride semiconductor light emitting device is epitaxially grown on the substrate 10, the substrate 10, and the buffer layer 20.
  • the n-type group III nitride semiconductor layer 30 epitaxially grown, the n-type group III nitride semiconductor layer 30 epitaxially grown and generating light by recombination of electrons and holes, on the active layer 40
  • the substrate 10 may be made of a sapphire substrate.
  • FIG. 7 is a diagram illustrating an example of a substrate included in a group III nitride semiconductor light emitting device according to the present disclosure.
  • the scattering region 90 is formed by deforming the substrate 10 (eg, sapphire is transformed in the case of a sapphire substrate) inside the substrate 10.
  • the scattering region 90 may vary in size or shape, and one scattering region 90 may provide various scattering angles.
  • the scattering region 90 may be continuously formed transversely or longitudinally between the upper and lower surfaces of the substrate 10.
  • P represents an example of the light path.
  • FIG. 8 is a diagram illustrating another example of a substrate included in a group III nitride semiconductor light emitting device according to the present disclosure.
  • a plurality of scattering regions 90 may be formed, and the distribution of scattering regions 90 may be Distributions of scattering zones may be irregular, or may be made while maintaining a predetermined interval. In order to make the distribution of the scattering regions 90 even, it is preferable that the scattering regions 90 are formed while maintaining a predetermined interval.
  • P represents another example of the light path.
  • FIG. 9 is a view showing another example of a substrate provided in the group III nitride semiconductor light emitting device according to the present disclosure, wherein the scattering region 90 is formed transversely between the upper and lower surfaces of the substrate 10 and is continuously formed. The scattering regions 90 are formed while maintaining a predetermined interval.
  • FIG. 10 is a view showing an example of a method of manufacturing a group III nitride semiconductor light emitting device according to the present disclosure.
  • substrate 10 is prepared (refer FIG. 10 (a)).
  • region 90 is formed by irradiating the laser 88 to the inside A of the board
  • the scattering region 90 may be moved by moving the substrate 10 or the laser 88 while the laser 88 is irradiated. ) May be continuously formed transversely or longitudinally between the upper surface 12 and the lower surface 14 of the substrate 10 (see FIG. 10C). Irradiation conditions of the laser 88 will be described in detail in the following experimental example.
  • the focal point of the laser 88 is located in the interior A of the substrate 10.
  • the light emitting device is divided into individual light emitting devices to reduce the thickness of the substrate 10 to facilitate the separation to the individual light emitting devices, when the lower surface 14 of the substrate 10 is polished, the scattering area 90 ),
  • the focal point of the laser 88 is preferably located on the upper surface 12 side in the interior A of the substrate 10 in order to prevent () from being damaged or lost.
  • the buffer layer 20, the n-type Group III nitride semiconductor layer 30, the active layer 40, and the p-type Group III nitride semiconductor layer 50 are grown on the upper surface 12 of the substrate 10 (Fig. (D) of 10).
  • the scattering region 90 is formed on the upper surface 12 of the substrate 10 by the buffer layer 20, the n-type Group III nitride semiconductor layer 30, the active layer 40, and the p-type Group III nitride semiconductor layer. It may be made after growing (50).
  • FIG. 11 shows a micrograph of the substrate processed according to the present experimental example as seen from above, and the scattering region 90 deformed by the laser can be seen inside the substrate 10. No surface damage of the substrate 10 was found.
  • FIG. 12 illustrates a micrograph of the scattering regions viewed from above according to the present experimental example, wherein the scattering regions 90 are formed on the substrate 10 at intervals of 300 ⁇ m. can see.
  • FIG. 13 is a photograph viewed from above of a group III nitride semiconductor light emitting device including a substrate processed according to the present experimental example, and it is seen that much light is emitted from the scattering region 90 formed inside the substrate 10 (see FIG. 6). Can be.
  • Substrate 10 is a flat substrate made of sapphire, a thickness of 400 ⁇ m and 2inch diameter was used.
  • the laser 88 is a type of UV pulse laser, has a wavelength of 532 nm, has a pulse of 7 ns, and uses a micro spot lens with a focal point of the laser 88 at a depth of 130 ⁇ m from the upper surface 12 of the substrate 10.
  • the substrate 10 was processed.
  • the laser 88 was irradiated so that the interval of the scattering regions 90 became 300 mu m. (See Figures 10-12)
  • a scattering region is a group III nitride semiconductor light emitting element, wherein the substrate is deformed by a laser.
  • a group III nitride semiconductor light emitting element characterized in that a plurality of scattering regions are formed on a substrate.
  • a group III nitride semiconductor light emitting element wherein the substrate is made of sapphire.
  • a group III nitride semiconductor light emitting element wherein the substrate is made of sapphire, and the scattering region is a region where the substrate is deformed by a laser, and is formed above the inside of the substrate.

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Abstract

The present disclosure relates to a Group-III nitride semiconductor light emitting device, more specifically to the Group III nitride semiconductor light emitting device comprising: a substrate that includes a scattering region therein; a Group I, III nitride semiconductor layer that is formed on the substrate and has a first conductivity; a Group II, III nitride semiconductor layer that is formed on the Group I, III nitride semiconductor layer and has a second conductivity different from the first conductivity; and plural Group III nitride semiconductor layers that are placed between the Group I, III and Group II, III nitride semiconductor layers and include an activation layer that generates light through the recombination of electrons with holes.

Description

3족 질화물 반도체 발광소자Group III nitride semiconductor light emitting device
본 개시(Disclosure)는 전체적으로 3족 질화물 반도체 발광소자에 관한 것으로, 특히 기판 내부에 스캐터링 영역을 형성하여 광추출효율을 향상시킨 3족 질화물 반도체 발광소자에 관한 것이다. 여기서, 3족 질화물 반도체 발광소자는 Al(x)Ga(y)In(1-x-y)N (0≤x≤1, 0≤y≤1, 0≤x+y≤1)로 된 화합물 반도체층을 포함하는 발광다이오드와 같은 발광소자를 의미하며, 추가적으로 SiC, SiN, SiCN, CN와 같은 다른 족(group)의 원소들로 이루어진 물질이나 이들 물질로 된 반도체층을 포함하는 것을 배제하는 것은 아니다.The present disclosure relates to a group III nitride semiconductor light emitting device as a whole, and more particularly, to a group III nitride semiconductor light emitting device in which scattering regions are formed inside a substrate to improve light extraction efficiency. Here, the group III nitride semiconductor light emitting device has a compound semiconductor layer of Al (x) Ga (y) In (1-xy) N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). Means a light emitting device, such as a light emitting diode comprising a, and does not exclude the inclusion of a material consisting of elements of other groups such as SiC, SiN, SiCN, CN or a semiconductor layer of these materials.
여기서는, 본 개시에 관한 배경기술이 제공되며, 이들이 반드시 공지기술을 의미하는 것은 아니다(This section provides background information related to the present disclosure which is not necessarily prior art).This section provides background information related to the present disclosure which is not necessarily prior art.
도 1은 종래의 3족 질화물 반도체 발광소자의 일 예를 나타내는 도면으로서, 3족 질화물 반도체 발광소자는 기판(100), 기판(100) 위에 성장되는 버퍼층(200), 버퍼층(200) 위에 성장되는 n형 3족 질화물 반도체층(300), n형 3족 질화물 반도체층(300) 위에 성장되는 활성층(400), 활성층(400) 위에 성장되는 p형 3족 질화물 반도체층(500), p형 3족 질화물 반도체층(500) 위에 형성되는 p측 전극(600), p측 전극(600) 위에 형성되는 p측 본딩 패드(700), p형 3족 질화물 반도체층(500)과 활성층(400)이 메사 식각되어 노출된 n형 3족 질화물 반도체층(300) 위에 형성되는 n측 전극(800), 그리고 보호막(900)을 포함한다.1 is a view illustrating an example of a conventional Group III nitride semiconductor light emitting device, wherein the Group III nitride semiconductor light emitting device is grown on the substrate 100, the buffer layer 200 grown on the substrate 100, and the buffer layer 200. n-type group III nitride semiconductor layer 300, an active layer 400 grown on the n-type group III nitride semiconductor layer 300, p-type group III nitride semiconductor layer 500, p-type 3 grown on the active layer 400 The p-side electrode 600 formed on the group nitride semiconductor layer 500, the p-side bonding pad 700 formed on the p-side electrode 600, the p-type group III nitride semiconductor layer 500 and the active layer 400 are formed. The n-side electrode 800 and the passivation layer 900 are formed on the n-type group III nitride semiconductor layer 300 exposed by mesa etching.
기판(100)은 동종기판으로 GaN계 기판이 이용되며, 이종기판으로 사파이어 기판, SiC 기판 또는 Si 기판 등이 이용되지만, 3족 질화물 반도체층이 성장될 수 있는 기판이라면 어떠한 형태이어도 좋다. SiC 기판이 사용될 경우에 n측 전극(800)은 SiC 기판 측에 형성될 수 있다.As the substrate 100, a GaN-based substrate is used as the homogeneous substrate, and a sapphire substrate, a SiC substrate, or a Si substrate is used as the heterogeneous substrate. Any substrate may be used as long as the group III nitride semiconductor layer can be grown. When a SiC substrate is used, the n-side electrode 800 may be formed on the SiC substrate side.
기판(100) 위에 성장되는 3족 질화물 반도체층들은 주로 MOCVD(유기금속기상성장법)에 의해 성장된다.Group III nitride semiconductor layers grown on the substrate 100 are mainly grown by MOCVD (organic metal vapor growth method).
버퍼층(200)은 이종기판(100)과 3족 질화물 반도체 사이의 격자상수 및 열팽창계수의 차이를 극복하기 위한 것이며, 미국특허 제5,122,845호에는 사파이어 기판 위에 380℃에서 800℃의 온도에서 100Å에서 500Å의 두께를 가지는 AlN 버퍼층을 성장시키는 기술이 기재되어 있으며, 미국특허 제5,290,393호에는 사파이어 기판 위에 200℃에서 900℃의 온도에서 10Å에서 5000Å의 두께를 가지는 Al(x)Ga(1-x)N (0≤x<1) 버퍼층을 성장시키는 기술이 기재되어 있고, 미국공개특허공보 제2006/154454호에는 600℃에서 990℃의 온도에서 SiC 버퍼층(씨앗층)을 성장시킨 다음 그 위에 In(x)Ga(1-x)N (0<x≤1) 층을 성장시키는 기술이 기재되어 있다. 바람직하게는 n형 3족 질화물 반도체층(300)의 성장에 앞서 도핑되지 않는 GaN층이 성장되며, 이는 버퍼층(200)의 일부로 보아도 좋고, n형 3족 질화물 반도체층(300)의 일부로 보아도 좋다.The buffer layer 200 is intended to overcome the difference in lattice constant and thermal expansion coefficient between the dissimilar substrate 100 and the group III nitride semiconductor, and US Pat. A technique for growing an AlN buffer layer having a thickness of US Pat. No. 5,290,393 describes Al (x) Ga (1-x) N having a thickness of 10 kPa to 5000 kPa at a temperature of 200 to 900 C on a sapphire substrate. (0 ≦ x <1) A technique for growing a buffer layer is described, and US Patent Publication No. 2006/154454 discloses growing a SiC buffer layer (seed layer) at a temperature of 600 ° C. to 990 ° C., followed by In (x Techniques for growing a Ga (1-x) N (0 <x≤1) layer are described. Preferably, the undoped GaN layer is grown prior to the growth of the n-type Group III nitride semiconductor layer 300, which may be viewed as part of the buffer layer 200 or as part of the n-type Group III nitride semiconductor layer 300. .
n형 3족 질화물 반도체층(300)은 적어도 n측 전극(800)이 형성된 영역(n형 컨택층)이 불순물로 도핑되며, n형 컨택층은 바람직하게는 GaN로 이루어지고, Si으로 도핑된다. 미국특허 제5,733,796호에는 Si과 다른 소스 물질의 혼합비를 조절함으로써 원하는 도핑농도로 n형 컨택층을 도핑하는 기술이 기재되어 있다.In the n-type group III nitride semiconductor layer 300, at least a region (n-type contact layer) in which the n-side electrode 800 is formed is doped with impurities, and the n-type contact layer is preferably made of GaN and doped with Si. . U. S. Patent No. 5,733, 796 describes a technique for doping an n-type contact layer to a desired doping concentration by controlling the mixing ratio of Si and other source materials.
활성층(400)은 전자와 정공의 재결합을 통해 광자(빛)를 생성하는 층으로서, 주로 In(x)Ga(1-x)N (0<x≤1)로 이루어지고, 하나의 양자우물층(single quantum well)이나 복수개의 양자우물층들(multi quantum wells)로 구성된다.The active layer 400 is a layer that generates photons (light) through recombination of electrons and holes, and is mainly composed of In (x) Ga (1-x) N (0 <x≤1), and one quantum well layer (single quantum wells) or multiple quantum wells.
p형 3족 질화물 반도체층(500)은 Mg과 같은 적절한 불순물을 이용해 도핑되며, 활성화(activation) 공정을 거쳐 p형 전도성을 가진다. 미국특허 제5,247,533호에는 전자빔 조사에 의해 p형 3족 질화물 반도체층을 활성화시키는 기술이 기재되어 있으며, 미국특허 제5,306,662호에는 400℃ 이상의 온도에서 열처리(annealing)함으로써 p형 3족 질화물 반도체층을 활성화시키는 기술이 기재되어 있고, 미국공개특허공보 제2006/157714호에는 p형 3족 질화물 반도체층 성장의 질소전구체로서 암모니아와 하이드라진계 소스 물질을 함께 사용함으로써 활성화 공정없이 p형 3족 질화물 반도체층이 p형 전도성을 가지게 하는 기술이 기재되어 있다.The p-type III-nitride semiconductor layer 500 is doped with an appropriate impurity such as Mg, and has an p-type conductivity through an activation process. U.S. Patent No. 5,247,533 describes a technique for activating a p-type group III nitride semiconductor layer by electron beam irradiation, and U.S. Patent No. 5,306,662 annealing the p-type Group III nitride semiconductor layer at a temperature of 400 占 폚 or higher. A technique for activating is described, and US Patent Publication No. 2006/157714 discloses a p-type III-nitride semiconductor layer without an activation process by using ammonia and a hydrazine-based source material together as a nitrogen precursor for growth of the p-type III-nitride semiconductor layer. Techniques for having this p-type conductivity have been described.
p측 전극(600)은 p형 3족 질화물 반도체층(500) 전체로 전류가 잘 공급되도록 하기 위해 구비되는 것이며, 미국특허 제5,563,422호에는 p형 3족 질화물 반도체층의 거의 전면에 걸쳐서 형성되며 p형 3족 질화물 반도체층(500)과 오믹접촉하고 Ni과 Au로 이루어진 투광성 전극(light-transmitting electrode)에 관한 기술이 기재되어 있으며, 미국특허 제6,515,306호에는 p형 3족 질화물 반도체층 위에 n형 초격자층을 형성한 다음 그 위에 ITO(Indium Tin Oxide)로 이루어진 투광성 전극을 형성한 기술이 기재되어 있다.The p-side electrode 600 is provided to supply a good current to the entire p-type group III nitride semiconductor layer 500. US Patent No. 5,563,422 is formed over almost the entire surface of the p-type group III nitride semiconductor layer. A light-transmitting electrode made of Ni and Au in ohmic contact with the p-type III-nitride semiconductor layer 500 is described. US Pat. No. 6,515,306 discloses n on the p-type III-nitride semiconductor layer. A technique is described in which a type superlattice layer is formed and then a translucent electrode made of indium tin oxide (ITO) is formed thereon.
한편, p측 전극(600)이 빛을 투과시키지 못하도록, 즉 빛을 기판 측으로 반사하도록 두꺼운 두께를 가지게 형성할 수 있는데, 이러한 기술을 플립칩(flip chip) 기술이라 한다. 미국특허 제6,194,743호에는 20nm 이상의 두께를 가지는 Ag 층, Ag 층을 덮는 확산 방지층, 그리고 확산 방지층을 덮는 Au와 Al으로 이루어진 본딩 층을 포함하는 전극 구조에 관한 기술이 기재되어 있다.On the other hand, the p-side electrode 600 may be formed to have a thick thickness so as not to transmit light, that is, to reflect the light toward the substrate side, this technique is referred to as flip chip (flip chip) technology. U. S. Patent No. 6,194, 743 describes a technique relating to an electrode structure including an Ag layer having a thickness of 20 nm or more, a diffusion barrier layer covering the Ag layer, and a bonding layer made of Au and Al covering the diffusion barrier layer.
p측 본딩 패드(700)와 n측 전극(800)은 전류의 공급과 외부로의 와이어 본딩을 위한 것이며, 미국특허 제5,563,422호에는 n측 전극을 Ti과 Al으로 구성한 기술이 기재되어 있다.The p-side bonding pad 700 and the n-side electrode 800 are for supplying current and wire bonding to the outside, and US Patent No. 5,563,422 describes a technique in which the n-side electrode is composed of Ti and Al.
보호막(900)은 이산화규소와 같은 물질로 형성되며, 생략될 수도 있다.The passivation layer 900 is formed of a material such as silicon dioxide and may be omitted.
한편, n형 3족 질화물 반도체층(300)이나 p형 3족 질화물 반도체층(500)은 단일의 층이나 복수개의 층으로 구성될 수 있으며, 최근에는 레이저 또는 습식 식각을 통해 기판(100)을 3족 질화물 반도체층들로부터 분리하여 수직형 발광소자를 제조하는 기술이 도입되고 있다.Meanwhile, the n-type III-nitride semiconductor layer 300 or the p-type III-nitride semiconductor layer 500 may be composed of a single layer or a plurality of layers, and recently, the substrate 100 may be formed by laser or wet etching. A technique for manufacturing a vertical light emitting device by separating from group III nitride semiconductor layers has been introduced.
도 2는 미국특허공보 제6,657,236호에 기재된 반도체 발광소자의 일 예를 나타내는 도면으로서, 3족 질화물 반도체층(300) 내에 굴절률의 달리하는 거친 표면(310)을 형성하여 빛을 스캐터링하여 외부양자효율을 향상시키는 기술이 기재되어 있다.FIG. 2 is a view showing an example of a semiconductor light emitting device disclosed in US Patent No. 6,657,236. The external quantum is formed by scattering light by forming a rough surface 310 having different refractive indices in a group III nitride semiconductor layer 300. Techniques for improving efficiency have been described.
도 3은 미국특허공보 제6,657,236호에 기재된 반도체 발광소자의 다른 예를 나타내는 도면으로서, 돌기(110)가 형성된 기판(100) 위에 굴절률을 달리하는 물질 층(120; SiO2 또는 질화물 층)을 형성하고, 그 위에 3족 질화물 반도체층(300)을 형성함으로써 외부양자효율을 높인 기술이 기재되어 있다.3 is a view showing another example of the semiconductor light emitting device disclosed in US Patent No. 6,657,236, which forms a material layer 120 (SiO 2 or nitride layer) having a different refractive index on the substrate 100 on which the protrusions 110 are formed. Then, a technique of increasing the external quantum efficiency by forming the group III nitride semiconductor layer 300 thereon is described.
도 4는 미국공개특허공보 제2008/121906호에 기재된 반도체 발광소자의 제조 방법의 일 예를 나타내는 도면으로서, 발광소자를 개별의 칩으로 분리함에 있어서, 레이저를 이용하여 먼저 기판(100)에 홈(130)을 형성한 다음, 추가로 홈(140)을 형성함으로써, 개별의 칩으로의 분리를 용이하게 한 기술이 기재되어 있다. 홈(140)의 형성에 있어서, 레이저는 기판(100)의 반대측 즉, 홈(130)이 형성된 측으로부터 기판(100)으로 조사되며, 레이저의 촛점을 홈(140)이 형성된 영역에 맞춤으로써 홈(140)을 형성할 수 있게 된다.FIG. 4 is a view showing an example of a method of manufacturing a semiconductor light emitting device disclosed in US Patent Publication No. 2008/121906. In separating the light emitting devices into individual chips, a groove is first formed on the substrate 100 using a laser. A technique is described that facilitates separation into individual chips by forming 130 and then further forming grooves 140. In the formation of the groove 140, the laser is irradiated to the substrate 100 from the opposite side of the substrate 100, that is, the side where the groove 130 is formed, and by matching the focus of the laser to the area where the groove 140 is formed 140 can be formed.
도 5는 일본공개특허공보 특개평11-163403호에 기재된 반도체 발광소자의 제조 방법의 일 예를 나타내는 도면으로서, 레이저를 조사하여 가공변질층(110)을 형성한 다음, 홈(130)을 형성하여 개별 칩으로 분리하는 기술이 기재되어 있다.FIG. 5 is a view showing an example of a method for manufacturing a semiconductor light emitting device disclosed in Japanese Patent Laid-Open No. 11-163403. A laser is irradiated to form a processing deformed layer 110, and then a groove 130 is formed. To separate the chips into individual chips.
여기서는, 본 개시의 전체적인 요약(Summary)이 제공되며, 이것이 본 개시의 외연을 제한하는 것으로 이해되어서는 아니된다(This section provides a general summary of the disclosure and is not a comprehensive disclosure of its full scope or all of its features).This section provides a general summary of the disclosure and is not a comprehensive disclosure of its full scope or all, provided that this is a summary of the disclosure. of its features).
본 개시에 따른 일 태양에 의하면(According to one aspect of the present disclosure), 내부에 스캐터링 영역이 형성된 기판; 그리고, 기판 위에 형성되며, 제1 도전성을 지니는 제1 3족 질화물 반도체층, 제1 3족 질화물 반도체층 위에 형성되며 제1 도전성과 다른 제2 도전성을 지니는 제2 3족 질화물 반도체층, 그리고 제1 3족 질화물 반도체층과 제2 3족 질화물 반도체층 사이에 위치하여 전자와 정공의 재결합에 의해 빛을 생성하는 활성층을 구비하는 복수개의 3족 질화물 반도체층;을 포함하는 것을 특징으로 하는 3족 질화물 반도체 발광소자가 제공된다.According to one aspect of the present disclosure, an substrate may include: a substrate having a scattering region formed therein; And a first group III nitride semiconductor layer formed on the substrate and having a first conductivity, a second group III nitride semiconductor layer formed on the first group III nitride semiconductor layer and having a second conductivity different from the first conductivity, and And a plurality of Group III nitride semiconductor layers positioned between the Group 1 III nitride semiconductor layer and the second Group III nitride semiconductor layer and having an active layer that generates light by recombination of electrons and holes. A nitride semiconductor light emitting device is provided.
본 개시에 따른 하나의 3족 질화물 반도체 발광소자에 의하면, 발광소자의 광추출효율을 향상시킬 수 있게 된다.According to one group III nitride semiconductor light emitting device according to the present disclosure, it is possible to improve the light extraction efficiency of the light emitting device.
또한 본 개시에 따른 다른 3족 질화물 반도체 발광소자에 의하면, 공정의 순서에 제한받지 않고 스캐터링 영역을 형성할 수 있게 된다.In addition, according to another group III nitride semiconductor light emitting device according to the present disclosure, the scattering region can be formed without being limited to the order of the processes.
또한 본 개시에 따른 또다른 3족 질화물 반도체 발광소자에 의하면, 다양한 스캐터링 각을 통해 발광소자의 광추출효율을 향상시킬 수 있게 된다.In addition, according to another group III nitride semiconductor light emitting device according to the present disclosure, it is possible to improve the light extraction efficiency of the light emitting device through various scattering angles.
도 1은 종래의 3족 질화물 반도체 발광소자의 일 예를 나타내는 도면,1 is a view showing an example of a conventional group III nitride semiconductor light emitting device,
도 2는 미국특허공보 제6,657,236호에 기재된 반도체 발광소자의 일 예를 나타내는 도면2 is a view showing an example of a semiconductor light emitting device described in US Patent No. 6,657,236
도 3은 미국특허공보 제6,657,236호에 기재된 반도체 발광소자의 다른 예를 나타내는 도면,3 is a view showing another example of the semiconductor light emitting device described in US Patent No. 6,657,236;
도 4는 미국공개특허공보 제2008/121906호에 기재된 반도체 발광소자의 제조 방법의 일 예를 나타내는 도면,4 is a view showing an example of a method of manufacturing a semiconductor light emitting device disclosed in US Patent Publication No. 2008/121906;
도 5는 일본공개특허공보 특개평11-163403호에 기재된 반도체 발광소자의 제조 방법의 일 예를 나타내는 도면,5 is a view showing an example of a method of manufacturing a semiconductor light emitting device disclosed in Japanese Patent Laid-Open No. 11-163403;
도 6은 본 개시에 따른 3족 질화물 반도체 발광소자의 일 예를 나타내는 도면,6 is a view showing an example of a group III nitride semiconductor light emitting device according to the present disclosure;
도 7은 본 개시에 따른 3족 질화물 반도체 발광소자에 구비되는 기판의 일 예를 나타내는 도면,7 is a view showing an example of a substrate provided in a group III nitride semiconductor light emitting device according to the present disclosure;
도 8은 본 개시에 따른 3족 질화물 반도체 발광소자에 구비되는 기판의 다른 예를 나타내는 도면,8 is a view showing another example of a substrate provided in the group III nitride semiconductor light emitting device according to the present disclosure;
도 9는 본 개시에 따른 3족 질화물 반도체 발광소자에 구비되는 기판의 또 다른 예를 나타내는 도면,9 is a view showing another example of a substrate provided in the group III nitride semiconductor light emitting device according to the present disclosure;
도 10은 본 개시에 따른 3족 질화물 반도체 발광소자의 제조방법의 일 예를 나타내는 도면,10 is a view showing an example of a method of manufacturing a group III nitride semiconductor light emitting device according to the present disclosure;
도 11은 본 실험예에 따라 가공된 기판을 위에서 바라본 현미경 사진,11 is a micrograph viewed from above of a substrate processed according to this Experimental Example;
도 12는 본 실험예에 따라 스캐터링 영역들이 간격을 이루며 형성된 기판을 위에서 바라본 현미경 사진,12 is a photomicrograph of the substrate from above, in which scattering regions are formed at intervals according to the present experimental example;
도 13은 본 실험예에 따라 가공된 기판을 포함하는 3족 질화물 반도체 발광소자를 위에서 바라본 사진.FIG. 13 is a photograph seen from above of a group III nitride semiconductor light-emitting device comprising a substrate processed according to this Experimental Example. FIG.
이하, 본 개시를 첨부된 도면을 참고로 하여 자세하게 설명한다(The present disclosure will now be described in detail with reference to the accompanying drawing(s)).The present disclosure will now be described in detail with reference to the accompanying drawing (s).
도 6은 본 개시에 따른 3족 질화물 반도체 발광소자의 일 예를 나타내는 도면으로서, 3족 질화물 반도체 발광소자는 기판(10), 기판(10) 위에 에피성장되는 버퍼층(20), 버퍼층(20) 위에 에피성장되는 n형 3족 질화물 반도체층(30), n형 3족 질화물 반도체층(30) 위에 에피성장되고 전자와 정공의 재결합에 의해 빛을 생성하는 활성층(40), 활성층(40) 위에 에피성장되는 p형 3족 질화물 반도체층(50), 그리고 스캐터링 영역(90)을 포함한다.6 is a diagram illustrating an example of a group III nitride semiconductor light emitting device according to the present disclosure, in which the group III nitride semiconductor light emitting device is epitaxially grown on the substrate 10, the substrate 10, and the buffer layer 20. On the n-type group III nitride semiconductor layer 30 epitaxially grown, the n-type group III nitride semiconductor layer 30 epitaxially grown and generating light by recombination of electrons and holes, on the active layer 40 An epitaxially grown p-type group III nitride semiconductor layer 50 and a scattering region 90.
기판(10)은 사파이어 기판으로 이루어질 수 있다.The substrate 10 may be made of a sapphire substrate.
도 7은 본 개시에 따른 3족 질화물 반도체 발광소자에 구비되는 기판의 일 예를 나타내는 도면으로서, 스캐터링 영역(90;a scattering zone)은 기판(10) 내부에 형성되어 활성층(40;도 6에서 도시)에서 생성된 빛을 스캐터링한다. 스캐터링 영역(90)은 기판(10)의 내부에서 기판(10)이 변형(예를 들어, 사파이어 기판일 경우 사파이어가 변형(transformation)되는 것을 의미한다.)되어 형성된다. 따라서, 스캐터링 영역(90)은 그 크기(size) 또는 형태(shape)가 다양할 수 있으며, 하나의 스캐터링 영역(90)이 다양한 스캐터링 각들을 제공할 수 있다. 한편, 스캐터링 영역(90)은 기판(10)의 상하면 사이를 횡으로 또는 종으로 가로지르며 연속적으로 형성될 수도 있다. P는 빛의 경로의 일 예를 나타낸다.FIG. 7 is a diagram illustrating an example of a substrate included in a group III nitride semiconductor light emitting device according to the present disclosure. A scattering zone 90 is formed in the substrate 10 to form an active layer 40. Scatters the light generated by the &lt; RTI ID = 0.0 &gt; The scattering region 90 is formed by deforming the substrate 10 (eg, sapphire is transformed in the case of a sapphire substrate) inside the substrate 10. Thus, the scattering region 90 may vary in size or shape, and one scattering region 90 may provide various scattering angles. On the other hand, the scattering region 90 may be continuously formed transversely or longitudinally between the upper and lower surfaces of the substrate 10. P represents an example of the light path.
도 8은 본 개시에 따른 3족 질화물 반도체 발광소자에 구비되는 기판의 다른 예를 나타내는 도면으로서, 스캐터링 영역(90)은 복수개가 형성될 수 있는데, 스캐터링 영역들(90)의 분포(The distribution of scattering zones)는 불규칙(irregular)하게 이루어질 수 있고, 소정의 간격(interval)를 유지하면서 이루어질 수도 있다. 스캐터링 영역들(90)의 분포가 고르게 이루어질 수 있도록 하기 위해서 스캐터링 영역들(90)은 소정의 간격을 유지하면서 형성되는 것이 바람직하다. P는 빛의 경로의 다른 예를 나타낸다.FIG. 8 is a diagram illustrating another example of a substrate included in a group III nitride semiconductor light emitting device according to the present disclosure. A plurality of scattering regions 90 may be formed, and the distribution of scattering regions 90 may be Distributions of scattering zones may be irregular, or may be made while maintaining a predetermined interval. In order to make the distribution of the scattering regions 90 even, it is preferable that the scattering regions 90 are formed while maintaining a predetermined interval. P represents another example of the light path.
도 9는 본 개시에 따른 3족 질화물 반도체 발광소자에 구비되는 기판의 또 다른 예를 나타내는 도면으로서, 스캐터링 영역(90)이 기판(10)의 상하면 사이를 횡으로 가로지르며 연속적으로 형성됨과 동시에 스캐터링 영역들(90)이 소정의 간격을 유지하면서 형성된 것을 나타낸다.9 is a view showing another example of a substrate provided in the group III nitride semiconductor light emitting device according to the present disclosure, wherein the scattering region 90 is formed transversely between the upper and lower surfaces of the substrate 10 and is continuously formed. The scattering regions 90 are formed while maintaining a predetermined interval.
이하에서, 본 개시에 따른 3족 질화물 반도체 발광소자의 제조방법을 사파이어 기판을 예로 하여 설명한다. Hereinafter, a method of manufacturing a group III nitride semiconductor light emitting device according to the present disclosure will be described using an sapphire substrate as an example.
도 10은 본 개시에 따른 3족 질화물 반도체 발광소자의 제조방법의 일 예를 나타내는 도면이다.10 is a view showing an example of a method of manufacturing a group III nitride semiconductor light emitting device according to the present disclosure.
먼저, 기판(10)을 준비한다(도 10의(a) 참조).First, the board | substrate 10 is prepared (refer FIG. 10 (a)).
다음으로, 기판(10)의 상면(12) 측에서 기판(10)의 내부(A)에 레이저(88)를 조사하여 스캐터링 영역(90)을 형성시킨다(도 10의(b) 참조). 레이저(88)의 조사는 기판(10)의 하면(14) 측에서 이루어질 수도 있다. 스캐터링 영역(90)의 크기, 형태 등은 레이저(88)의 조사조건에 의해 달라질 수 있으며, 레이저(88)가 조사되는 동안 기판(10) 또는 레이저(88)가 움직임으로써 스캐터링 영역(90)이 기판(10)의 상면(12)과 하면(14) 사이를 횡으로 또는 종으로 가로지르며 연속적으로 형성될 수 있다(도 10의(c) 참조). 레이저(88)의 조사조건은 이하의 실험예에서 상세히 설명한다. 이때, 레이저(88)의 초점은 기판(10)의 내부(A)에 위치한다. 한편, 발광소자를 개별 발광소자들로 분리할 때 기판(10)의 두께를 줄여 개별 발광소자들로의 분리가 용이하도록 기판(10)의 하면(14)을 연마할 경우, 스캐터링 영역(90)이 손상 또는 손실되는 것을 방지하기 위하여 레이저(88)의 초점은 기판(10)의 내부(A)에서 상면(12) 측에 위치하는 것이 바람직하다.Next, the scattering area | region 90 is formed by irradiating the laser 88 to the inside A of the board | substrate 10 from the upper surface 12 side of the board | substrate 10 (refer FIG.10 (b)). Irradiation of the laser 88 may be performed on the lower surface 14 side of the substrate 10. The size, shape, and the like of the scattering region 90 may vary depending on the irradiation conditions of the laser 88. The scattering region 90 may be moved by moving the substrate 10 or the laser 88 while the laser 88 is irradiated. ) May be continuously formed transversely or longitudinally between the upper surface 12 and the lower surface 14 of the substrate 10 (see FIG. 10C). Irradiation conditions of the laser 88 will be described in detail in the following experimental example. At this time, the focal point of the laser 88 is located in the interior A of the substrate 10. On the other hand, when the light emitting device is divided into individual light emitting devices to reduce the thickness of the substrate 10 to facilitate the separation to the individual light emitting devices, when the lower surface 14 of the substrate 10 is polished, the scattering area 90 ), The focal point of the laser 88 is preferably located on the upper surface 12 side in the interior A of the substrate 10 in order to prevent () from being damaged or lost.
다음으로, 기판(10)의 상면(12) 위에 버퍼층(20), n형 3족 질화물 반도체층(30), 활성층(40), 그리고 p형 3족 질화물 반도체층(50)을 성장시킨다(도 10의(d) 참조). 여기서, 스캐터링 영역(90)의 형성은 기판(10)의 상면(12) 위에 버퍼층(20), n형 3족 질화물 반도체층(30), 활성층(40), 그리고 p형 3족 질화물 반도체층(50)을 성장시킨 후 이루어져도 좋다.Next, the buffer layer 20, the n-type Group III nitride semiconductor layer 30, the active layer 40, and the p-type Group III nitride semiconductor layer 50 are grown on the upper surface 12 of the substrate 10 (Fig. (D) of 10). Here, the scattering region 90 is formed on the upper surface 12 of the substrate 10 by the buffer layer 20, the n-type Group III nitride semiconductor layer 30, the active layer 40, and the p-type Group III nitride semiconductor layer. It may be made after growing (50).
실험예Experimental Example
도 11은 본 실험예에 따라 가공된 기판을 위에서 바라본 현미경 사진을 나타내는 것으로, 기판(10)의 내부에 레이저에 의해 변형된 스캐터링 영역(90)을 볼 수 있다. 기판(10)의 표면손상은 발견되지 않았다.FIG. 11 shows a micrograph of the substrate processed according to the present experimental example as seen from above, and the scattering region 90 deformed by the laser can be seen inside the substrate 10. No surface damage of the substrate 10 was found.
도 12는 본 실험예에 따라 스캐터링 영역들이 간격을 이루며 형성된 기판을 위에서 바라본 현미경 사진을 나타내는 것으로, 스캐터링 영역들(90)이 300㎛의 간격(I)을 이루며 기판(10)에 형성된 것을 볼 수 있다. FIG. 12 illustrates a micrograph of the scattering regions viewed from above according to the present experimental example, wherein the scattering regions 90 are formed on the substrate 10 at intervals of 300 μm. can see.
도 13은 본 실험예에 따라 가공된 기판을 포함하는 3족 질화물 반도체 발광소자를 위에서 바라본 사진으로서, 기판(10; 도 6 참조) 내부에 형성된 스캐터링 영역(90)에서 빛이 많이 나오는 것을 볼 수 있다.FIG. 13 is a photograph viewed from above of a group III nitride semiconductor light emitting device including a substrate processed according to the present experimental example, and it is seen that much light is emitted from the scattering region 90 formed inside the substrate 10 (see FIG. 6). Can be.
기판(10)은 사파이어로 이루어진 평면기판으로, 두께는 400㎛이고 직경은 2inch인 기판을 사용하였다. Substrate 10 is a flat substrate made of sapphire, a thickness of 400㎛ and 2inch diameter was used.
레이저(88)는 종류가 UV 펄스 레이저이고, 파장이 532nm이고, 펄스가 7ns이고, 레이저(88)의 초점이 기판(10)의 상면(12)으로부터 130㎛의 깊이로, 마이크로 스팟 렌즈를 사용하여 기판(10)을 가공하였다. 한편, 스캐터링 영역들(90)의 간격(interval)이 300㎛이 되도록 레이저(88)를 조사하였다. (도 10 내지 12 참조)The laser 88 is a type of UV pulse laser, has a wavelength of 532 nm, has a pulse of 7 ns, and uses a micro spot lens with a focal point of the laser 88 at a depth of 130 μm from the upper surface 12 of the substrate 10. The substrate 10 was processed. On the other hand, the laser 88 was irradiated so that the interval of the scattering regions 90 became 300 mu m. (See Figures 10-12)
이하 본 개시의 다양한 실시 형태에 대하여 설명한다.Hereinafter, various embodiments of the present disclosure will be described.
(1) 스캐터링 영역은 레이저에 의해 기판이 변형되어 이루어지는 영역인 것을 특징으로 하는 3족 질화물 반도체 발광소자.(1) A scattering region is a group III nitride semiconductor light emitting element, wherein the substrate is deformed by a laser.
(2) 스캐터링 영역은 기판 내부를 가로질러 연속적으로 형성되는 것을 특징으로 하는 3족 질화물 반도체 발광소자.(2) A group III nitride semiconductor light emitting element, wherein the scattering region is formed continuously across the substrate.
(3) 스캐터링 영역은 기판에 복수개가 형성되는 것을 특징으로 하는 3족 질화물 반도체 발광소자. (3) A group III nitride semiconductor light emitting element, characterized in that a plurality of scattering regions are formed on a substrate.
(4) 기판은 사파이어로 이루어지는 것을 특징으로 하는 3족 질화물 반도체 발광소자.(4) A group III nitride semiconductor light emitting element, wherein the substrate is made of sapphire.
(5) 스캐터링 영역은 기판의 내부 상측에 형성되는 것을 특징으로 하는 3족 질화물 반도체 발광소자.(5) A group III nitride semiconductor light emitting element, wherein the scattering region is formed above the inside of the substrate.
(6) 기판은 사파이어로 이루어지고, 스캐터링 영역은 레이저에 의해 기판이 변형되어 이루어지는 영역이며 기판의 내부 상측에 형성되는 것을 특징으로 하는 3족 질화물 반도체 발광소자.(6) A group III nitride semiconductor light emitting element, wherein the substrate is made of sapphire, and the scattering region is a region where the substrate is deformed by a laser, and is formed above the inside of the substrate.

Claims (8)

  1. 내부에 스캐터링 영역이 형성된 기판; 그리고,A substrate having a scattering region formed therein; And,
    기판 위에 형성되며, 제1 도전성을 지니는 제1 3족 질화물 반도체층, 제1 3족 질화물 반도체층 위에 형성되며 제1 도전성과 다른 제2 도전성을 지니는 제2 3족 질화물 반도체층, 그리고 제1 3족 질화물 반도체층과 제2 3족 질화물 반도체층 사이에 위치하여 전자와 정공의 재결합에 의해 빛을 생성하는 활성층을 구비하는 복수개의 3족 질화물 반도체층;을 포함하는 것을 특징으로 하는 3족 질화물 반도체 발광소자.A first group III nitride semiconductor layer formed on the substrate, the first group III nitride semiconductor layer having a first conductivity, a second group III nitride semiconductor layer formed on the first group III nitride semiconductor layer, and having a second conductivity different from the first conductivity, and the first third A group III nitride semiconductor layer comprising a plurality of group III nitride semiconductor layers positioned between the group nitride semiconductor layer and the second group III nitride semiconductor layer and having an active layer that generates light by recombination of electrons and holes; Light emitting element.
  2. 청구항 1에서,In claim 1,
    스캐터링 영역은 레이저에 의해 기판이 변형되어 이루어지는 영역인 것을 특징으로 하는 3족 질화물 반도체 발광소자.The scattering region is a group III nitride semiconductor light emitting device, characterized in that the substrate is deformed by a laser.
  3. 청구항 1에서,In claim 1,
    스캐터링 영역은 기판 내부를 가로질러 연속적으로 형성되는 것을 특징으로 하는 3족 질화물 반도체 발광소자.A scattering region is a group III nitride semiconductor light emitting device, characterized in that formed continuously across the substrate.
  4. 청구항 1에서,In claim 1,
    스캐터링 영역은 기판에 복수개가 형성되는 것을 특징으로 하는 3족 질화물 반도체 발광소자. A group III nitride semiconductor light emitting device, characterized in that a plurality of scattering regions are formed on the substrate.
  5. 청구항 1에서,In claim 1,
    기판은 사파이어로 이루어지는 것을 특징으로 하는 3족 질화물 반도체 발광소자.A group III nitride semiconductor light emitting device, characterized in that the substrate is made of sapphire.
  6. 청구항 1에서,In claim 1,
    스캐터링 영역은 기판의 내부 상측에 형성되는 것을 특징으로 하는 3족 질화물 반도체 발광소자.A scattering region is a group III nitride semiconductor light emitting device, characterized in that formed on the inside of the substrate.
  7. 청구항 1에서,In claim 1,
    기판은 사파이어로 이루어지고,The substrate is made of sapphire,
    스캐터링 영역은 레이저에 의해 기판이 변형되어 이루어지는 영역인 것을 특징으로 하는 3족 질화물 반도체 발광소자.The scattering region is a group III nitride semiconductor light emitting device, characterized in that the substrate is deformed by a laser.
  8. 청구항 7에서,In claim 7,
    스캐터링 영역은 기판의 내부 상측에 형성되는 것을 특징으로 하는 3족 질화물 반도체 발광소자.A scattering region is a group III nitride semiconductor light emitting device, characterized in that formed on the inside of the substrate.
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