WO2011021872A2 - Group iii nitride semiconductor light-emitting element and a production method therefor - Google Patents

Group iii nitride semiconductor light-emitting element and a production method therefor Download PDF

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WO2011021872A2
WO2011021872A2 PCT/KR2010/005510 KR2010005510W WO2011021872A2 WO 2011021872 A2 WO2011021872 A2 WO 2011021872A2 KR 2010005510 W KR2010005510 W KR 2010005510W WO 2011021872 A2 WO2011021872 A2 WO 2011021872A2
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nitride semiconductor
layer
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group iii
iii nitride
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WO2011021872A3 (en
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장문식
김서군
김창태
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주식회사 에피밸리
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • H01L33/325—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen characterised by the doping materials
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
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    • H01L21/02389—Nitrides
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H01L21/02507—Alternating layers, e.g. superlattice
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H01L21/02521—Materials
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/025—Physical imperfections, e.g. particular concentration or distribution of impurities

Definitions

  • the present disclosure relates to a group III nitride semiconductor light emitting device, and more particularly, to a structure of a p-type group III nitride semiconductor layer formed on an active layer and a method of manufacturing the same.
  • the group III nitride semiconductor light emitting device has a compound semiconductor layer of Al (x) Ga (y) In (1-xy) N (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1).
  • FIG. 1 is a view illustrating an example of a conventional Group III nitride semiconductor light emitting device, wherein the Group III nitride semiconductor light emitting device is grown on the substrate 100, the buffer layer 200 grown on the substrate 100, and the buffer layer 200.
  • the p-side electrode 600 formed on the group nitride semiconductor layer 500, the p-side bonding pad 700 formed on the p-side electrode 600, the p-type group III nitride semiconductor layer 500 and the active layer 400 are formed.
  • the n-side electrode 800 and the passivation layer 900 are formed on the n-type group III nitride semiconductor layer 300 exposed by mesa etching.
  • a GaN-based substrate is used as the homogeneous substrate, and a sapphire substrate, a SiC substrate, or a Si substrate is used as the heterogeneous substrate. Any substrate may be used as long as the group III nitride semiconductor layer can be grown.
  • the n-side electrode 800 may be formed on the SiC substrate side.
  • Group III nitride semiconductor layers grown on the substrate 100 are mainly grown by MOCVD (organic metal vapor growth method).
  • the buffer layer 200 is intended to overcome the difference in lattice constant and thermal expansion coefficient between the dissimilar substrate 100 and the group III nitride semiconductor, and US Pat.
  • a technique for growing an AlN buffer layer having a thickness of US Pat. No. 5,290,393 describes Al (x) Ga (1-x) N having a thickness of 10 kPa to 5000 kPa at a temperature of 200 to 900 C on a sapphire substrate. (0 ⁇ x ⁇ 1)
  • a technique for growing a buffer layer is described, and US Patent Publication No. 2006/154454 discloses growing a SiC buffer layer (seed layer) at a temperature of 600 ° C.
  • the undoped GaN layer is grown prior to the growth of the n-type Group III nitride semiconductor layer 300, which may be viewed as part of the buffer layer 200 or as part of the n-type Group III nitride semiconductor layer 300. .
  • n-type contact layer In the n-type group III nitride semiconductor layer 300, at least a region (n-type contact layer) in which the n-side electrode 800 is formed is doped with impurities, and the n-type contact layer is preferably made of GaN and doped with Si. .
  • U. S. Patent No. 5,733, 796 describes a technique for doping an n-type contact layer to a desired doping concentration by controlling the mixing ratio of Si and other source materials.
  • the active layer 400 is a layer that generates photons (light) through recombination of electrons and holes, and is mainly composed of In (x) Ga (1-x) N (0 ⁇ x ⁇ 1), and one quantum well layer (single quantum wells) or multiple quantum wells.
  • the p-type III-nitride semiconductor layer 500 is doped with an appropriate impurity such as Mg, and has an p-type conductivity through an activation process.
  • U.S. Patent No. 5,247,533 describes a technique for activating a p-type group III nitride semiconductor layer by electron beam irradiation, and U.S. Patent No. 5,306,662 annealing at a temperature of 400 DEG C or higher to A technique for activating is described, and US Patent Publication No.
  • 2006/157714 discloses a p-type III-nitride semiconductor layer without an activation process by using ammonia and a hydrazine-based source material together as a nitrogen precursor for growing the p-type III-nitride semiconductor layer. Techniques for having this p-type conductivity have been described.
  • the p-side electrode 600 is provided to supply a good current to the entire p-type group III nitride semiconductor layer 500.
  • US Patent No. 5,563,422 is formed over almost the entire surface of the p-type group III nitride semiconductor layer.
  • a light-transmitting electrode made of Ni and Au in ohmic contact with the p-type III-nitride semiconductor layer 500 is described.
  • US Pat. No. 6,515,306 discloses n on the p-type III-nitride semiconductor layer. A technique is described in which a type superlattice layer is formed and then a translucent electrode made of indium tin oxide (ITO) is formed thereon.
  • ITO indium tin oxide
  • the p-side electrode 600 may be formed to have a thick thickness so as not to transmit light, that is, to reflect the light toward the substrate side, this technique is referred to as flip chip (flip chip) technology.
  • U. S. Patent No. 6,194, 743 describes a technique relating to an electrode structure including an Ag layer having a thickness of 20 nm or more, a diffusion barrier layer covering the Ag layer, and a bonding layer made of Au and Al covering the diffusion barrier layer.
  • the p-side bonding pad 700 and the n-side electrode 800 are for supplying current and wire bonding to the outside, and US Patent No. 5,563,422 describes a technique in which the n-side electrode is composed of Ti and Al.
  • the passivation layer 900 is formed of a material such as silicon dioxide and may be omitted.
  • the n-type III-nitride semiconductor layer 300 or the p-type III-nitride semiconductor layer 500 may be composed of a single layer or a plurality of layers, and recently, the substrate 100 may be formed by laser or wet etching. A technique for manufacturing a vertical light emitting device by separating from group III nitride semiconductor layers has been introduced.
  • FIG. 2 is a view showing an example of a growth method of a p-type nitride semiconductor layer described in US Pat. No. 5,306,662, wherein TMGa (trimethylgallium) and NH 3 (ammonia) are used as raw materials and Cp 2 Mg (cyclepentadier)
  • TMGa trimethylgallium
  • NH 3 ammonia
  • Cp 2 Mg cyclepentadier
  • the present disclosure is to improve the luminous efficiency by improving the p-type doping efficiency of the p-type Group III nitride semiconductor layer.
  • the present disclosure is to provide a structure of the p-type group III nitride semiconductor layer to minimize the absorption of light generated in the active layer by the p-type group III nitride semiconductor layer.
  • an active layer in which light is generated by recombination of electrons and holes;
  • a p-type nitride semiconductor layer provided in the active layer and supplying holes to the active layer;
  • a second p-type layer interposed in the p-type nitride semiconductor layer and doped with MgN.
  • the p-type nitride semiconductor layer may include a first p-type layer provided between the active layer and the second p-type layer; And the third p-type layer provided in the second p-type layer.
  • the first, 2, 3 p-type layer preferably has a different p-type doping concentration.
  • the p-type doping concentration of the first, second, and third p-type layers is preferably smaller in order of the third p-type layer, the first p-type layer, and the second p-type layer.
  • MgN and a group III nitride semiconductor are alternately grown.
  • MgN is preferably formed by infiltrating into the group III nitride semiconductor.
  • MgN and a group III nitride semiconductor are grown alternately 40 times.
  • the group III nitride semiconductor is preferably provided with GaN.
  • a method of manufacturing a group III nitride semiconductor light emitting device comprising: providing a first p-type layer on the active layer; Alternately repeatedly growing MgN and a group III nitride semiconductor on the first p-type layer to provide the second p-type layer; And providing the third p-type layer in the second p-type layer.
  • the group III nitride semiconductor is preferably provided with GaN.
  • the second p-type layer is preferably provided by repeatedly growing MgN and group III nitride semiconductor 20 to 50 times.
  • first, second, and third p-type layers are provided to have different p-type doping concentrations, and it is preferable that the p-type doping concentration is small in order of the third p-type layer, the first p-type layer, and the second p-type layer.
  • MgN is preferably formed by infiltrating into the group III nitride semiconductor.
  • Group III nitride semiconductor light emitting device and a method of manufacturing the same according to the present disclosure, it is possible to form a high quality p type Group III nitride semiconductor thin film having improved p type doping efficiency.
  • group III nitride semiconductor light emitting device and a method of manufacturing the same according to the present disclosure, it is possible to form a group III nitride semiconductor light emitting device having reduced forward voltage and improved output power.
  • FIG. 1 is a view showing an example of a conventional group III nitride semiconductor light emitting device
  • FIG. 2 is a view showing an example of a growth method of a p-type nitride semiconductor layer described in US Patent No. 5,306,662,
  • FIG. 3 is a view showing an example of a method of manufacturing a group III nitride semiconductor light emitting device according to the present disclosure
  • FIG. 4 is a view showing an example of a group III nitride semiconductor light emitting device according to the present disclosure
  • Vf 1 forward voltage
  • Power output power
  • FIG. 3 is a diagram illustrating an example of a group III nitride semiconductor light emitting device and a method of manufacturing the same according to the present disclosure.
  • the first p-type layer 51 is grown on the active layer 40, and then the second p-type layer 52 is formed. A method of growing is shown.
  • MgN 21 processing is performed.
  • the MgN 21 treatment means supplying CP 2 Mg and NH 3 to the first p-type layer 51, in which case MgN is formed to form a layer rather than MgN 21 to form the first p-type layer 51. It is strongly inclined to penetrate into the inside.
  • the primary group III nitride semiconductor layer S 1 is introduced. Then, the second MgN process 21 is performed again. After this process is repeated up to nth order, the third p-type layer 53 is grown.
  • Gag is included in the form of MgN in the form of MgN, thereby eliminating the need for additional substitution, thereby increasing the doping efficiency in the activation process. You can.
  • the reason for processing MgN in the second p-type layer 52 is to minimize the absorption of light generated from p-GaN.
  • the first p-type layer 51 is a layer for supplying holes to the active layer 40, and a large amount of magnesium doping is required. If the first p-type layer 51 is repeatedly treated with MgN and GaN, sufficient holes cannot be obtained. There is a problem that the optical characteristics and output power is lowered.
  • the growth temperature of the second p-type layer is 700 °C to 1000 °C
  • the treatment time of MgN is 1 to 10 seconds
  • CP 2 Mg is injected 200cc to 2000cc at a temperature of 35 °C and 900torr
  • the growth rate of GaN is 4 to It formed in the range of 10 ms / sec.
  • FIG. 4 is a diagram illustrating an example of a group III nitride semiconductor light emitting device according to the present disclosure, wherein the group III nitride semiconductor light emitting device is disposed on a substrate 10, a buffer layer 20, and a buffer layer 20 grown on the substrate 10.
  • FIG. 5 is a view showing measured values of the forward voltage Vf 1 and the output power according to the processing time change of MgN and GaN in the step of forming a group III nitride semiconductor light emitting device according to the present disclosure.
  • Mg is excessively doped in the GaN semiconductor to increase the absorption of light emitted from the active layer 40.
  • the repeated lamination of MgN / GaN is preferably applied to the second p-type layer 52 rather than to the first p-type layer 51 and the third p-type layer 53 having a high doping concentration as a whole layer. Can be.
  • the output power is higher than a certain level, but it can be seen that the forward voltage also increases.
  • MgN is 3 seconds and GaN is 21 seconds, thereby alternately growing for 40 cycles to form the second p-type layer 52, wherein the thickness of each GaN of the second p-type layer is It may be made of 20 to 50 Hz.
  • the Mg content of MgN treatment of the second p-type layer is less than the Mg content of the first p-type layer and the Mg content of the third p-type layer, it is possible to maintain the p-type characteristics even at low Mg content, thereby improving the luminous efficiency. As a result, the dielectric breakdown voltage can be increased due to the improvement of the p-type layer film quality.

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Abstract

The present disclosure relates to a group III nitride semiconductor light-emitting element comprising: an active layer which generates light by the recombination of electrons and electron holes; a p-type nitride semiconductor layer which is provided on the active layer and supplies electron holes to the active layer; and a second p-type layer which is interposed in the p-type nitride semiconductor layer and is doped with MgN. Also, the present disclosure relates to a production method for a group III nitride semiconductor light emitting element comprising the steps of: providing a first p-type layer on the active layer; providing the second p-type layer by repeatedly alternately growing MgN and a group III nitride semiconductor on the first p-type layer; and providing a third p-type layer on the second p-type layer.

Description

3족 질화물 반도체 발광소자 및 그 제조방법Group III nitride semiconductor light emitting device and manufacturing method
본 개시(Disclosure)는 3족 질화물 반도체 발광소자에 관한 것으로, 특히 활성층 상에 형성되는 p형 3족 질화물 반도체층의 구조 및 그 제조방법에 관한 것이다.The present disclosure relates to a group III nitride semiconductor light emitting device, and more particularly, to a structure of a p-type group III nitride semiconductor layer formed on an active layer and a method of manufacturing the same.
여기서, 3족 질화물 반도체 발광소자는 Al(x)Ga(y)In(1-x-y)N (0≤x≤1, 0≤y≤1, 0≤x+y≤1)로 된 화합물 반도체층을 포함하는 발광다이오드와 같은 발광소자를 의미하며, 추가적으로 SiC, SiN, SiCN, CN와 같은 다른 족(group)의 원소들로 이루어진 물질이나 이들 물질로 된 반도체층을 포함하는 것을 배제하는 것은 아니다.Here, the group III nitride semiconductor light emitting device has a compound semiconductor layer of Al (x) Ga (y) In (1-xy) N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). Means a light emitting device, such as a light emitting diode comprising a, and does not exclude the inclusion of a material consisting of elements of other groups such as SiC, SiN, SiCN, CN or a semiconductor layer of these materials.
여기서는, 본 개시에 관한 배경기술이 제공되며, 이들이 반드시 공지기술을 의미하는 것은 아니다(This section provides background information related to the present disclosure which is not necessarily prior art).This section provides background information related to the present disclosure which is not necessarily prior art.
도 1은 종래의 3족 질화물 반도체 발광소자의 일 예를 나타내는 도면으로서, 3족 질화물 반도체 발광소자는 기판(100), 기판(100) 위에 성장되는 버퍼층(200), 버퍼층(200) 위에 성장되는 n형 3족 질화물 반도체층(300), n형 3족 질화물 반도체층(300) 위에 성장되는 활성층(400), 활성층(400) 위에 성장되는 p형 3족 질화물 반도체층(500), p형 3족 질화물 반도체층(500) 위에 형성되는 p측 전극(600), p측 전극(600) 위에 형성되는 p측 본딩 패드(700), p형 3족 질화물 반도체층(500)과 활성층(400)이 메사 식각되어 노출된 n형 3족 질화물 반도체층(300) 위에 형성되는 n측 전극(800), 그리고 보호막(900)을 포함한다.1 is a view illustrating an example of a conventional Group III nitride semiconductor light emitting device, wherein the Group III nitride semiconductor light emitting device is grown on the substrate 100, the buffer layer 200 grown on the substrate 100, and the buffer layer 200. n-type group III nitride semiconductor layer 300, an active layer 400 grown on the n-type group III nitride semiconductor layer 300, p-type group III nitride semiconductor layer 500, p-type 3 grown on the active layer 400 The p-side electrode 600 formed on the group nitride semiconductor layer 500, the p-side bonding pad 700 formed on the p-side electrode 600, the p-type group III nitride semiconductor layer 500 and the active layer 400 are formed. The n-side electrode 800 and the passivation layer 900 are formed on the n-type group III nitride semiconductor layer 300 exposed by mesa etching.
기판(100)은 동종기판으로 GaN계 기판이 이용되며, 이종기판으로 사파이어 기판, SiC 기판 또는 Si 기판 등이 이용되지만, 3족 질화물 반도체층이 성장될 수 있는 기판이라면 어떠한 형태이어도 좋다. SiC 기판이 사용될 경우에 n측 전극(800)은 SiC 기판 측에 형성될 수 있다.As the substrate 100, a GaN-based substrate is used as the homogeneous substrate, and a sapphire substrate, a SiC substrate, or a Si substrate is used as the heterogeneous substrate. Any substrate may be used as long as the group III nitride semiconductor layer can be grown. When a SiC substrate is used, the n-side electrode 800 may be formed on the SiC substrate side.
기판(100) 위에 성장되는 3족 질화물 반도체층들은 주로 MOCVD(유기금속기상성장법)에 의해 성장된다.Group III nitride semiconductor layers grown on the substrate 100 are mainly grown by MOCVD (organic metal vapor growth method).
버퍼층(200)은 이종기판(100)과 3족 질화물 반도체 사이의 격자상수 및 열팽창계수의 차이를 극복하기 위한 것이며, 미국특허 제5,122,845호에는 사파이어 기판 위에 380℃에서 800℃의 온도에서 100Å에서 500Å의 두께를 가지는 AlN 버퍼층을 성장시키는 기술이 기재되어 있으며, 미국특허 제5,290,393호에는 사파이어 기판 위에 200℃에서 900℃의 온도에서 10Å에서 5000Å의 두께를 가지는 Al(x)Ga(1-x)N (0≤x<1) 버퍼층을 성장시키는 기술이 기재되어 있고, 미국공개특허공보 제2006/154454호에는 600℃에서 990℃의 온도에서 SiC 버퍼층(씨앗층)을 성장시킨 다음 그 위에 In(x)Ga(1-x)N (0<x≤1) 층을 성장시키는 기술이 기재되어 있다. 바람직하게는 n형 3족 질화물 반도체층(300)의 성장에 앞서 도핑되지 않는 GaN층이 성장되며, 이는 버퍼층(200)의 일부로 보아도 좋고, n형 3족 질화물 반도체층(300)의 일부로 보아도 좋다.The buffer layer 200 is intended to overcome the difference in lattice constant and thermal expansion coefficient between the dissimilar substrate 100 and the group III nitride semiconductor, and US Pat. A technique for growing an AlN buffer layer having a thickness of US Pat. No. 5,290,393 describes Al (x) Ga (1-x) N having a thickness of 10 kPa to 5000 kPa at a temperature of 200 to 900 C on a sapphire substrate. (0 ≦ x <1) A technique for growing a buffer layer is described, and US Patent Publication No. 2006/154454 discloses growing a SiC buffer layer (seed layer) at a temperature of 600 ° C. to 990 ° C., followed by In (x Techniques for growing a Ga (1-x) N (0 <x≤1) layer are described. Preferably, the undoped GaN layer is grown prior to the growth of the n-type Group III nitride semiconductor layer 300, which may be viewed as part of the buffer layer 200 or as part of the n-type Group III nitride semiconductor layer 300. .
n형 3족 질화물 반도체층(300)은 적어도 n측 전극(800)이 형성된 영역(n형 컨택층)이 불순물로 도핑되며, n형 컨택층은 바람직하게는 GaN로 이루어지고, Si으로 도핑된다. 미국특허 제5,733,796호에는 Si과 다른 소스 물질의 혼합비를 조절함으로써 원하는 도핑농도로 n형 컨택층을 도핑하는 기술이 기재되어 있다.In the n-type group III nitride semiconductor layer 300, at least a region (n-type contact layer) in which the n-side electrode 800 is formed is doped with impurities, and the n-type contact layer is preferably made of GaN and doped with Si. . U. S. Patent No. 5,733, 796 describes a technique for doping an n-type contact layer to a desired doping concentration by controlling the mixing ratio of Si and other source materials.
활성층(400)은 전자와 정공의 재결합을 통해 광자(빛)를 생성하는 층으로서, 주로 In(x)Ga(1-x)N (0<x≤1)로 이루어지고, 하나의 양자우물층(single quantum well)이나 복수개의 양자우물층들(multi quantum wells)로 구성된다.The active layer 400 is a layer that generates photons (light) through recombination of electrons and holes, and is mainly composed of In (x) Ga (1-x) N (0 <x≤1), and one quantum well layer (single quantum wells) or multiple quantum wells.
p형 3족 질화물 반도체층(500)은 Mg과 같은 적절한 불순물을 이용해 도핑되며, 활성화(activation) 공정을 거쳐 p형 전도성을 가진다. 미국특허 제5,247,533호에는 전자빔 조사에 의해 p형 3족 질화물 반도체층을 활성화시키는 기술이 기재되어 있으며, 미국특허 제5,306,662호에는 400℃ 이상의 온도에서 열처리(annealing)함으로써 p형 3족 질화물 반도체층을 활성화시키는 기술이 기재되어 있고, 미국공개특허공보 제2006/157714호에는 p형 3족 질화물 반도체층 성장의 질소전구체로서 암모니아와 하이드라진계 소스 물질을 함께 사용함으로써 활성화 공정없이 p형 3족 질화물 반도체층이 p형 전도성을 가지게 하는 기술이 기재되어 있다.The p-type III-nitride semiconductor layer 500 is doped with an appropriate impurity such as Mg, and has an p-type conductivity through an activation process. U.S. Patent No. 5,247,533 describes a technique for activating a p-type group III nitride semiconductor layer by electron beam irradiation, and U.S. Patent No. 5,306,662 annealing at a temperature of 400 DEG C or higher to A technique for activating is described, and US Patent Publication No. 2006/157714 discloses a p-type III-nitride semiconductor layer without an activation process by using ammonia and a hydrazine-based source material together as a nitrogen precursor for growing the p-type III-nitride semiconductor layer. Techniques for having this p-type conductivity have been described.
p측 전극(600)은 p형 3족 질화물 반도체층(500) 전체로 전류가 잘 공급되도록 하기 위해 구비되는 것이며, 미국특허 제5,563,422호에는 p형 3족 질화물 반도체층의 거의 전면에 걸쳐서 형성되며 p형 3족 질화물 반도체층(500)과 오믹접촉하고 Ni과 Au로 이루어진 투광성 전극(light-transmitting electrode)에 관한 기술이 기재되어 있으며, 미국특허 제6,515,306호에는 p형 3족 질화물 반도체층 위에 n형 초격자층을 형성한 다음 그 위에 ITO(Indium Tin Oxide)로 이루어진 투광성 전극을 형성한 기술이 기재되어 있다.The p-side electrode 600 is provided to supply a good current to the entire p-type group III nitride semiconductor layer 500. US Patent No. 5,563,422 is formed over almost the entire surface of the p-type group III nitride semiconductor layer. A light-transmitting electrode made of Ni and Au in ohmic contact with the p-type III-nitride semiconductor layer 500 is described. US Pat. No. 6,515,306 discloses n on the p-type III-nitride semiconductor layer. A technique is described in which a type superlattice layer is formed and then a translucent electrode made of indium tin oxide (ITO) is formed thereon.
한편, p측 전극(600)이 빛을 투과시키지 못하도록, 즉 빛을 기판 측으로 반사하도록 두꺼운 두께를 가지게 형성할 수 있는데, 이러한 기술을 플립칩(flip chip) 기술이라 한다. 미국특허 제6,194,743호에는 20nm 이상의 두께를 가지는 Ag 층, Ag 층을 덮는 확산 방지층, 그리고 확산 방지층을 덮는 Au와 Al으로 이루어진 본딩 층을 포함하는 전극 구조에 관한 기술이 기재되어 있다.On the other hand, the p-side electrode 600 may be formed to have a thick thickness so as not to transmit light, that is, to reflect the light toward the substrate side, this technique is referred to as flip chip (flip chip) technology. U. S. Patent No. 6,194, 743 describes a technique relating to an electrode structure including an Ag layer having a thickness of 20 nm or more, a diffusion barrier layer covering the Ag layer, and a bonding layer made of Au and Al covering the diffusion barrier layer.
p측 본딩 패드(700)와 n측 전극(800)은 전류의 공급과 외부로의 와이어 본딩을 위한 것이며, 미국특허 제5,563,422호에는 n측 전극을 Ti과 Al으로 구성한 기술이 기재되어 있다.The p-side bonding pad 700 and the n-side electrode 800 are for supplying current and wire bonding to the outside, and US Patent No. 5,563,422 describes a technique in which the n-side electrode is composed of Ti and Al.
보호막(900)은 이산화규소와 같은 물질로 형성되며, 생략될 수도 있다.The passivation layer 900 is formed of a material such as silicon dioxide and may be omitted.
한편, n형 3족 질화물 반도체층(300)이나 p형 3족 질화물 반도체층(500)은 단일의 층이나 복수개의 층으로 구성될 수 있으며, 최근에는 레이저 또는 습식 식각을 통해 기판(100)을 3족 질화물 반도체층들로부터 분리하여 수직형 발광소자를 제조하는 기술이 도입되고 있다.Meanwhile, the n-type III-nitride semiconductor layer 300 or the p-type III-nitride semiconductor layer 500 may be composed of a single layer or a plurality of layers, and recently, the substrate 100 may be formed by laser or wet etching. A technique for manufacturing a vertical light emitting device by separating from group III nitride semiconductor layers has been introduced.
도 2는 미국특허 제5,306,662호에 기재된 p형 질화물 반도체층의 성장 방법의 일 예를 나타내는 도면으로서, TMGa(트리메틸갈륨)과 NH3(암모니아)를 원료가스로 하고, Cp2Mg(싸이클펜타디에닐마그네슘)을 p형 도펀트로 하여 p형 GaN을 성장시킬 때, Mg-H 복합체가 형성되어 Mg이 도펀트로 기능하지 못하는 문제점을 해소하기 위하여, 열처리를 통해 활성화시키는 기술이 기재되어 있으나, 이러한 방법으로도 상당수의 Mg이 본래의 역할을 하지 못하고 있어 도핑효율은 개선의 여지가 있다.FIG. 2 is a view showing an example of a growth method of a p-type nitride semiconductor layer described in US Pat. No. 5,306,662, wherein TMGa (trimethylgallium) and NH 3 (ammonia) are used as raw materials and Cp 2 Mg (cyclepentadier) In order to solve the problem that Mg-H complex is formed when Mg-H complex is grown when p-type GaN is grown with p-type dopant, Mg is activated by heat treatment. Even though a large amount of Mg does not play an original role, the doping efficiency has room for improvement.
본 개시는 p형 3족 질화물 반도체층의 p형 도핑 효율을 개선하여 발광효율을 향상시키는 것을 일 목적으로 한다.The present disclosure is to improve the luminous efficiency by improving the p-type doping efficiency of the p-type Group III nitride semiconductor layer.
또한, 본 개시는 활성층에서 발생된 빛이 p형 3족 질화물 반도체층에 의해 흡수되는 것을 최소화시키는 p형 3족 질화물 반도체층의 구조의 제공을 일 목적으로 한다.In addition, the present disclosure is to provide a structure of the p-type group III nitride semiconductor layer to minimize the absorption of light generated in the active layer by the p-type group III nitride semiconductor layer.
여기서는, 본 개시의 전체적인 요약(Summary)이 제공되며, 이것이 본 개시의 외연을 제한하는 것으로 이해되어서는 아니된다(This section provides a general summary of the disclosure and is not a comprehensive disclosure of its full scope or all of its features).This section provides a general summary of the disclosure and is not a comprehensive disclosure of its full scope or all, provided that this is a summary of the disclosure. of its features).
본 개시의 일 태양에 의하면(According to one aspect of the present disclosure), 전자와 정공의 재결합에 의해 빛이 생성되는 활성층; 상기 활성층에 구비되고, 상기 활성층에 정공을 공급하는 p형 질화물 반도체층; 및 상기 p형 질화물 반도체층에 개재되며, MgN으로 도핑된 제2 p형층;을 포함하는 3족 질화물 반도체 발광소자가 제공된다.According to one aspect of the present disclosure (According to one aspect of the present disclosure), an active layer in which light is generated by recombination of electrons and holes; A p-type nitride semiconductor layer provided in the active layer and supplying holes to the active layer; And a second p-type layer interposed in the p-type nitride semiconductor layer and doped with MgN.
여기서, 상기 p형 질화물 반도체층은, 상기 활성층과 상기 제2 p형층 사이에 구비되는 제1 p형층; 및 상기 제2 p형층에 구비되는 상기 제3 p형층;을 포함하는 것이 바람직하다.The p-type nitride semiconductor layer may include a first p-type layer provided between the active layer and the second p-type layer; And the third p-type layer provided in the second p-type layer.
또한, 상기 제1,2,3 p형층은 서로 다른 p형 도핑농도를 가지는 것이 바람직하다.In addition, the first, 2, 3 p-type layer preferably has a different p-type doping concentration.
또한, 상기 제1,2,3 p형층의 p형 도핑농도는, 제3 p형층, 제1 p형층, 제2 p형층 순으로 작은 것이 바람직하다.The p-type doping concentration of the first, second, and third p-type layers is preferably smaller in order of the third p-type layer, the first p-type layer, and the second p-type layer.
또한, 상기 제2 p형층은, MgN과 3족 질화물 반도체가 교대로 성장되어 구비되는 것이 바람직하다.In the second p-type layer, it is preferable that MgN and a group III nitride semiconductor are alternately grown.
또한, 상기 제2 p형층은, MgN이 3족 질화물 반도체의 내부로 침투되어 형성되는 것이 바람직하다.In the second p-type layer, MgN is preferably formed by infiltrating into the group III nitride semiconductor.
또한, 상기 제2 p형층은, MgN과 3족 질화물 반도체가 40회 교대로 성장되어 구비되는 것이 바람직하다.In the second p-type layer, it is preferable that MgN and a group III nitride semiconductor are grown alternately 40 times.
또한, 상기 3족 질화물 반도체는 GaN으로 구비되는 것이 바람직하다.In addition, the group III nitride semiconductor is preferably provided with GaN.
한편, 본 개시의 다른 일 태양에 의하면(According to one another aspect of the present disclosure), 3족 질화물 반도체 발광소자를 제조방법으로서, 상기 활성층 위에 제1 p형층을 구비하는 단계; 상기 제1 p형층 위에 MgN과 3족 질화물 반도체를 교대로 반복 성장시켜 상기 제2 p형층을 구비하는 단계; 및 상기 제2 p형층에 상기 제3 p형층을 구비하는 단계;을 포함하는 3족 질화물 반도체 발광소자의 제조방법이 제공된다.Meanwhile, according to another aspect of the present disclosure (According to one another aspect of the present disclosure), a method of manufacturing a group III nitride semiconductor light emitting device, comprising: providing a first p-type layer on the active layer; Alternately repeatedly growing MgN and a group III nitride semiconductor on the first p-type layer to provide the second p-type layer; And providing the third p-type layer in the second p-type layer.
여기서, 3족 질화물 반도체는 GaN으로 구비되는 것이 바람직하다.Here, the group III nitride semiconductor is preferably provided with GaN.
또한, 상기 제2 p형층은 MgN과 3족 질화물 반도체를 20~50회 반복 성장시켜 구비되는 것이 바람직하다.In addition, the second p-type layer is preferably provided by repeatedly growing MgN and group III nitride semiconductor 20 to 50 times.
또한, 상기 제1,2,3 p형층은 서로 다른 p형 도핑농도를 갖도록 구비되며, 제3 p형층, 제1 p형층, 제2 p형층 순으로 p형 도핑농도가 작은 것이 바람직하다.In addition, the first, second, and third p-type layers are provided to have different p-type doping concentrations, and it is preferable that the p-type doping concentration is small in order of the third p-type layer, the first p-type layer, and the second p-type layer.
또한, 상기 제2 p형층은, MgN이 3족 질화물 반도체의 내부로 침투되어 형성되는 것이 바람직하다.In the second p-type layer, MgN is preferably formed by infiltrating into the group III nitride semiconductor.
본 개시에 따른 하나의 3족 질화물 반도체 발광소자 및 그 제조방법에 의하면, p형 도핑효율이 개선된 고품질의 p형 3족 질화물 반도체 박막을 형성할 수 있게 된다.According to one Group III nitride semiconductor light emitting device and a method of manufacturing the same according to the present disclosure, it is possible to form a high quality p type Group III nitride semiconductor thin film having improved p type doping efficiency.
또한, 본 개시에 따른 다른 3족 질화물 반도체 발광소자 및 그 제조방법에 의하면, 순방향전압이 감소하고 출력전력이 향상된 3족 질화물 반도체 발광소자를 형성할 수 있게 된다.In addition, according to another group III nitride semiconductor light emitting device and a method of manufacturing the same according to the present disclosure, it is possible to form a group III nitride semiconductor light emitting device having reduced forward voltage and improved output power.
도 1은 종래의 3족 질화물 반도체 발광소자의 일 예를 나타내는 도면,1 is a view showing an example of a conventional group III nitride semiconductor light emitting device,
도 2는 미국특허 제5,306,662호에 기재된 p형 질화물 반도체층의 성장 방법의 일 예를 나타내는 도면,2 is a view showing an example of a growth method of a p-type nitride semiconductor layer described in US Patent No. 5,306,662,
도 3은 본 개시에 따라 3족 질화물 반도체 발광소자를 제조하는 방법의 일 예를 나타내는 도면,3 is a view showing an example of a method of manufacturing a group III nitride semiconductor light emitting device according to the present disclosure;
도 4은 본 개시에 따른 3족 질화물 반도체 발광소자의 일 예를 나타내는 도면,4 is a view showing an example of a group III nitride semiconductor light emitting device according to the present disclosure;
도 5는 본 개시에 따라 3족 질화물 반도체 발광소자를 형성하는 단계에서 MgN와 GaN의 처리시간 변화에 따른 순방향전압(Vf1)과 출력전력(Power)의 측정값을 나타내는 도면.5 is a view showing measured values of the forward voltage (Vf 1 ) and the output power (Power) according to the processing time change of MgN and GaN in the step of forming a group III nitride semiconductor light emitting device according to the present disclosure.
이하, 본 개시를 첨부된 도면을 참고로 하여 자세하게 설명한다(The present disclosure will now be described in detail with reference to the accompanying drawing(s)). The present disclosure will now be described in detail with reference to the accompanying drawing (s).
도 3은 본 개시에 따라 3족 질화물 반도체 발광소자 및 그 제조방법의 일 예를 나타내는 도면으로서, 먼저 활성층(40) 상에 제1 p형층(51)을 성장시킨 후 제2 p형층(52)을 성장시키는 방법이 제시되어 있다. 3 is a diagram illustrating an example of a group III nitride semiconductor light emitting device and a method of manufacturing the same according to the present disclosure. First, the first p-type layer 51 is grown on the active layer 40, and then the second p-type layer 52 is formed. A method of growing is shown.
먼저, MgN(21) 처리가 행해진다. 여기서, MgN(21) 처리는 제1 p형층(51)에 CP2Mg와 NH3를 공급하는 것을 의미하며, 이 경우 MgN(21)이 층을 이루도록 형성되기보다는 MgN이 제1 p형층(51)의 내부로 침투되어 구비되는 경향이 강하다.First, MgN 21 processing is performed. Herein, the MgN 21 treatment means supplying CP 2 Mg and NH 3 to the first p-type layer 51, in which case MgN is formed to form a layer rather than MgN 21 to form the first p-type layer 51. It is strongly inclined to penetrate into the inside.
이런 이유로 'MgN 처리'라는 용어를 사용하였다.For this reason the term 'MgN treatment' is used.
다음으로 1차 3족 질화물 반도체층(S1)이 투입된다. 그리고 다시 2차 MgN 처리(21)가 행해진다. 이후 이러한 과정이 n차까지 반복된 후 제3 p형층(53)이 성장된다. Next, the primary group III nitride semiconductor layer S 1 is introduced. Then, the second MgN process 21 is performed again. After this process is repeated up to nth order, the third p-type layer 53 is grown.
MgN 처리(21)를 중간에 반복하여 3족 질화물 반도체(Sn)를 성장시키는 과정에서 MgN의 결합형태로 GaN에 Mg이 포함되기 때문에 추가적인 치환 과정이 필요없게 되어 활성화 과정에서의 도핑 효율을 증대시킬 수 있다. In the process of growing the group III nitride semiconductor (S n ) by repeating the MgN treatment 21 in the middle, Gag is included in the form of MgN in the form of MgN, thereby eliminating the need for additional substitution, thereby increasing the doping efficiency in the activation process. You can.
이때, 제 2 p형층(52)에 MgN를 처리하는 이유는 p-GaN에서 발생하는 빛의 흡수를 최소화하기 위함이다. At this time, the reason for processing MgN in the second p-type layer 52 is to minimize the absorption of light generated from p-GaN.
일반적으로 GaN에 Mg을 도핑하는 경우, 활성층(40)에서 발광되는 빛이 p-GaN에서 흡수되는데 흡수되는 정도는 마그네슘의 도핑 양에 비례하기 때문이다. In general, when Mg is doped into GaN, light emitted from the active layer 40 is absorbed in p-GaN, because the degree of absorption is proportional to the doping amount of magnesium.
제1 p형층(51)은 활성층(40)에 정공을 공급하는 층으로서 많은 양의 마그네슘 도핑이 필요한데, 이러한 제1 p형층(51)에 MgN 및 GaN를 반복하여 처리하면 충분한 정공을 얻을 수 없어 광특성 및 출력전력이 저하되는 문제점이 있다. The first p-type layer 51 is a layer for supplying holes to the active layer 40, and a large amount of magnesium doping is required. If the first p-type layer 51 is repeatedly treated with MgN and GaN, sufficient holes cannot be obtained. There is a problem that the optical characteristics and output power is lowered.
이러한 점을 고려하여 제2 p형층(52)에 한정하여 MgN 및 GaN를 반복하여 처리하는 것이 바람직하다. In view of this, it is preferable to repeatedly process MgN and GaN only in the second p-type layer 52.
제 2 p형층의 성장온도는 700℃ 내지 1000℃이고, MgN의 처리시간은 1 내지 10초이며, CP2Mg는 35℃의 온도와 900torr의 압력에서 200cc 내지 2000cc 주입하고 GaN의 성장율은 4 내지 10 Å/sec의 범위에서 형성하였다.The growth temperature of the second p-type layer is 700 ℃ to 1000 ℃, the treatment time of MgN is 1 to 10 seconds, CP 2 Mg is injected 200cc to 2000cc at a temperature of 35 ℃ and 900torr and the growth rate of GaN is 4 to It formed in the range of 10 ms / sec.
도 4는 본 개시에 따른 3족 질화물 반도체 발광소자의 일 예를 나타내는 도면으로서, 3족 질화물 반도체 발광소자는 기판(10), 기판(10) 위에 성장되는 버퍼층(20), 버퍼층(20) 위에 성장되는 n형 3족 질화물 반도체층(30), n형 3족 질화물 반도체층(30) 위에 성장되는 활성층(40), 활성층(40) 위에 성장되는 제1 p형층(51), 제1 p형층(51) 위에 형성되는 제2 p형층(52), 제2 p형층(52) 위에 형성되는 제3 p형층(53), 제3 p형층(53) 위에 형성되는 p측 전극(60), p측 전극(60) 위에 형성되는 p측 본딩 패드(70), 제1 p형층(51)및 제2 p형층(52)과 활성층(40)이 메사 식각되어 노출된 n형 3족 질화물 반도체층(30) 위에 형성되는 n측 전극(80), 그리고 보호막(90)을 포함한다.4 is a diagram illustrating an example of a group III nitride semiconductor light emitting device according to the present disclosure, wherein the group III nitride semiconductor light emitting device is disposed on a substrate 10, a buffer layer 20, and a buffer layer 20 grown on the substrate 10. N-type III-nitride semiconductor layer 30 to be grown, active layer 40 to be grown on n-type III-nitride semiconductor layer 30, first p-type layer 51 to be grown on active layer 40, and first p-type layer The second p-type layer 52 formed on the 51, the third p-type layer 53 formed on the second p-type layer 52, the p-side electrode 60 formed on the third p-type layer 53, and p The n-type group III nitride semiconductor layer in which the p-side bonding pad 70, the first p-type layer 51, the second p-type layer 52, and the active layer 40 formed on the side electrode 60 are mesa-etched and exposed. 30, the n-side electrode 80 and the passivation layer 90 are formed.
도 5는 본 개시에 따라 3족 질화물 반도체 발광소자를 형성하는 단계에서 MgN와 GaN의 처리시간 변화에 따른 순방향전압(Vf1)과 출력전력(Power)의 측정값을 나타내는 도면이다. FIG. 5 is a view showing measured values of the forward voltage Vf 1 and the output power according to the processing time change of MgN and GaN in the step of forming a group III nitride semiconductor light emitting device according to the present disclosure.
MgN을 과도하게 처리하는 경우에는 순방향전압은 낮으나, 출력전력도 낮게 측정되는 것을 알 수 있다. When the MgN is excessively processed, it can be seen that the forward voltage is low but the output power is also low.
이는 Mg이 GaN 반도체 내에 과도하게 도핑이 되어 활성층(40)에서 발광하는 광의 흡수가 증가하기 때문인 것으로 생각된다. This is considered to be because Mg is excessively doped in the GaN semiconductor to increase the absorption of light emitted from the active layer 40.
따라서 MgN/GaN의 반복 적층은 층 전체로서 도핑 농도가 높은 제1 p형층(51) 및 제3 p형층(53)에 적용하는 것보다 제2 p형층(52)에 적용하는 것이 바람직하다는 것을 알 수 있다. Therefore, it is understood that the repeated lamination of MgN / GaN is preferably applied to the second p-type layer 52 rather than to the first p-type layer 51 and the third p-type layer 53 having a high doping concentration as a whole layer. Can be.
한편 MgN을 처리하지 않는 경우에는 출력전력은 일정수준 이상이나, 순방향전압도 높아지는 것을 알 수 있다. On the other hand, when the MgN is not processed, the output power is higher than a certain level, but it can be seen that the forward voltage also increases.
이는 제2 p형층의 도핑농도가 낮아 상대적으로 전자와 정공의 재결합이 원활하게 이루어지지 않기 때문인 것으로 생각된다. It is thought that this is because the doping concentration of the second p-type layer is low and relatively the recombination of electrons and holes is not performed smoothly.
이러한 점을 고려하여 예를 들어, MgN은 3초, GaN은 21초로 40주기 동안 교대 성장함으로써 제2 p형층(52)을 형성할 수 있으며, 이때 제2 p형층의 각각의 GaN의 막두께는 20 내지 50Å으로 이루어질 수 있다. In consideration of this, for example, MgN is 3 seconds and GaN is 21 seconds, thereby alternately growing for 40 cycles to form the second p-type layer 52, wherein the thickness of each GaN of the second p-type layer is It may be made of 20 to 50 Hz.
그리고 제2 p형층의 MgN처리에 대한 Mg 함량이 제1 p형층의 Mg 함량과 제3 p형층의 Mg 함량보다 적도록 하면 낮은 Mg 함량에서도 p형 특성을 유지할 수 있어 발광 효율 개선에 도움이 되며, p형층 막질의 개선으로 인해 정전내전압을 높일 수 있다. In addition, if the Mg content of MgN treatment of the second p-type layer is less than the Mg content of the first p-type layer and the Mg content of the third p-type layer, it is possible to maintain the p-type characteristics even at low Mg content, thereby improving the luminous efficiency. As a result, the dielectric breakdown voltage can be increased due to the improvement of the p-type layer film quality.

Claims (13)

  1. 전자와 정공의 재결합에 의해 빛이 생성되는 활성층;An active layer in which light is generated by recombination of electrons and holes;
    상기 활성층에 구비되고, 상기 활성층에 정공을 공급하는 p형 질화물 반도체층; 및A p-type nitride semiconductor layer provided in the active layer and supplying holes to the active layer; And
    상기 p형 질화물 반도체층에 개재되며, MgN으로 도핑된 제2 p형층;을 포함하는 3족 질화물 반도체 발광소자.And a second p-type layer interposed in the p-type nitride semiconductor layer and doped with MgN.
  2. 제 1 항에 있어서,The method of claim 1,
    상기 p형 질화물 반도체층은,The p-type nitride semiconductor layer,
    상기 활성층과 상기 제2 p형층 사이에 구비되는 제1 p형층; 및A first p-type layer provided between the active layer and the second p-type layer; And
    상기 제2 p형층에 구비되는 상기 제3 p형층;을 포함하는 것을 특징으로 하는 3족 질화물 반도체 발광소자.And a third p-type layer provided in the second p-type layer.
  3. 제 2 항에 있어서,The method of claim 2,
    상기 제1,2,3 p형층은 서로 다른 p형 도핑농도를 가지는 것을 특징으로 하는 3족 질화물 반도체 발광소자.The group III nitride semiconductor light emitting device of claim 1, wherein the first, second and third p-type layers have different p-type doping concentrations.
  4. 제 3 항에 있어서,The method of claim 3, wherein
    상기 제1,2,3 p형층의 p형 도핑농도는, 제3 p형층, 제1 p형층, 제2 p형층 순으로 작은 것을 특징으로 하는 3족 질화물 반도체 발광소자.The p-type doping concentration of the first, second, and third p-type layers is small in the order of the third p-type layer, the first p-type layer, and the second p-type layer.
  5. 제 1 항에 있어서,The method of claim 1,
    상기 제2 p형층은, MgN과 3족 질화물 반도체가 교대로 성장되어 구비되는 것을 특징으로 3족 질화물 반도체 발광소자.The second p-type layer is a group III nitride semiconductor light emitting device, characterized in that the MgN and a group III nitride semiconductor are alternately grown.
  6. 제 5 항에 있어서,The method of claim 5,
    상기 제2 p형층은, MgN이 3족 질화물 반도체의 내부로 침투되어 형성되는 것을 특징으로 하는 3족 질화물 반도체 발광소자.The second p-type layer is a group III nitride semiconductor light emitting device, characterized in that MgN is formed to penetrate into the group III nitride semiconductor.
  7. 제 5 항에 있어서,The method of claim 5,
    상기 제2 p형층은, MgN과 3족 질화물 반도체가 40회 교대로 성장되어 구비되는 것을 특징으로 하는 3족 질화물 반도체 발광소자.The second p-type layer is a group III nitride semiconductor light emitting device, characterized in that the MgN and the group III nitride semiconductor is grown alternately 40 times.
  8. 제 5 항에 있어서,The method of claim 5,
    상기 3족 질화물 반도체는 GaN으로 구비되는 것을 특징으로 하는 3족 질화물 반도체 발광소자.The group III nitride semiconductor light emitting device is characterized in that the group III nitride semiconductor.
  9. 제 2 항의 3족 질화물 반도체 발광소자를 제조방법으로서,A method of manufacturing the Group III nitride semiconductor light emitting device of claim 2,
    상기 활성층 위에 제1 p형층을 구비하는 단계;Providing a first p-type layer on the active layer;
    상기 제1 p형층 위에 MgN과 3족 질화물 반도체를 교대로 반복 성장시켜 상기 제2 p형층을 구비하는 단계; 및Alternately repeatedly growing MgN and a group III nitride semiconductor on the first p-type layer to provide the second p-type layer; And
    상기 제2 p형층에 상기 제3 p형층을 구비하는 단계;을 포함하는 3족 질화물 반도체 발광소자의 제조방법. And providing the third p-type layer in the second p-type layer.
  10. 제 9 항에 있어서,The method of claim 9,
    3족 질화물 반도체는 GaN으로 구비되는 것을 특징으로 하는 3족 질화물 반도체 발광소자의 제조방법.The group III nitride semiconductor is GaN manufacturing method of the nitride semiconductor light emitting device, characterized in that provided with.
  11. 제 9 항에 있어서,The method of claim 9,
    상기 제2 p형층은 MgN과 3족 질화물 반도체를 20~50회 반복 성장시켜 구비되는 것을 특징으로 하는 3족 질화물 반도체 발광소자.The second p-type layer is a group III nitride semiconductor light-emitting device, characterized in that provided by repeatedly growing MgN and group III nitride semiconductor 20 to 50 times.
  12. 제 9 항에 있어서,The method of claim 9,
    상기 제1,2,3 p형층은 서로 다른 p형 도핑농도를 갖도록 구비되며, 제3 p형층, 제1 p형층, 제2 p형층 순으로 p형 도핑농도가 작은 것을 특징으로 하는 3족 질화물 반도체 발광소자의 제조방법.The first, second, and third p-type layers are provided to have different p-type doping concentrations, and the Group III nitrides characterized in that the p-type doping concentration is small in the order of the third p-type layer, the first p-type layer, and the second p-type layer. Method of manufacturing a semiconductor light emitting device.
  13. 제 9 항에 있어서,The method of claim 9,
    상기 제2 p형층은, MgN이 3족 질화물 반도체의 내부로 침투되어 형성되는 것을 특징으로 하는 3족 질화물 반도체 발광소자의 제조방법.The second p-type layer is a method of manufacturing a group III nitride semiconductor light emitting device, characterized in that the MgN is formed to penetrate into the group III nitride semiconductor.
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CN113451454B (en) * 2020-09-17 2022-08-05 重庆康佳光电技术研究院有限公司 P-type semiconductor layer growth method, LED epitaxial layer and chip

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