KR20110019161A - Method of forming iii-nitride semiconductor light emitting device - Google Patents

Method of forming iii-nitride semiconductor light emitting device Download PDF

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KR20110019161A
KR20110019161A KR1020090076765A KR20090076765A KR20110019161A KR 20110019161 A KR20110019161 A KR 20110019161A KR 1020090076765 A KR1020090076765 A KR 1020090076765A KR 20090076765 A KR20090076765 A KR 20090076765A KR 20110019161 A KR20110019161 A KR 20110019161A
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nitride semiconductor
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type layer
light emitting
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장문식
김서군
김창태
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주식회사 에피밸리
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    • H—ELECTRICITY
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    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
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    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
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    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
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Abstract

PURPOSE: A method for manufacturing a group III nitride semiconductor light emitting diode is provided to improve doping efficiency and output power through several GaN and MgN processes on one p type layer. CONSTITUTION: A plurality of nitride semiconductor layers include an active layer(40) and at least one p type layer(51). An active layer generates light through the recombination of holes and electrons. A p type layer supplies the holes. An active layer is formed. At least one p type layer is formed on the active layer. GaN and MgN are processed several times.

Description

3족 질화물 반도체 발광소자를 제조하는 방법{METHOD OF FORMING Ⅲ-NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE}Method of manufacturing a group III nitride semiconductor light emitting device {METHOD OF FORMING III-NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE}

본 개시(Disclosure)는 3족 질화물 반도체 발광소자에 관한 것으로, 활성층 상에 형성되는 하나의 p형층에 복수회의 GaN 및 MgN 처리를 거쳐 도핑효율 및 출력전력을 향상시킨 반도체 발광소자에 관한 것이다.The present disclosure relates to a group III nitride semiconductor light emitting device, and more particularly, to a semiconductor light emitting device having improved doping efficiency and output power through a plurality of GaN and MgN treatments in one p-type layer formed on an active layer.

여기서, 3족 질화물 반도체 발광소자는 Al(x)Ga(y)In(1-x-y)N (0≤x≤1, 0≤y≤1, 0≤x+y≤1)로 된 화합물 반도체층을 포함하는 발광다이오드와 같은 발광소자를 의미하며, 추가적으로 SiC, SiN, SiCN, CN와 같은 다른 족(group)의 원소들로 이루어진 물질이나 이들 물질로 된 반도체층을 포함하는 것을 배제하는 것은 아니다.Here, the group III nitride semiconductor light emitting device has a compound semiconductor layer of Al (x) Ga (y) In (1-xy) N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). Means a light emitting device, such as a light emitting diode comprising a, and does not exclude the inclusion of a material consisting of elements of other groups such as SiC, SiN, SiCN, CN or a semiconductor layer of these materials.

여기서는, 본 개시에 관한 배경기술이 제공되며, 이들이 반드시 공지기술을 의미하는 것은 아니다(This section provides background information related to the present disclosure which is not necessarily prior art).This section provides background information related to the present disclosure which is not necessarily prior art.

도 1은 종래의 3족 질화물 반도체 발광소자의 일 예를 나타내는 도면으로서, 3족 질화물 반도체 발광소자는 기판(100), 기판(100) 위에 성장되는 버퍼층(200), 버퍼층(200) 위에 성장되는 n형 3족 질화물 반도체층(300), n형 3족 질화물 반도체층(300) 위에 성장되는 활성층(400), 활성층(400) 위에 성장되는 p형 3족 질화물 반도체층(500), p형 3족 질화물 반도체층(500) 위에 형성되는 p측 전극(600), p측 전극(600) 위에 형성되는 p측 본딩 패드(700), p형 3족 질화물 반도체층(500)과 활성층(400)이 메사 식각되어 노출된 n형 3족 질화물 반도체층(300) 위에 형성되는 n측 전극(800), 그리고 보호막(900)을 포함한다.1 is a view illustrating an example of a conventional Group III nitride semiconductor light emitting device, wherein the Group III nitride semiconductor light emitting device is grown on the substrate 100, the buffer layer 200 grown on the substrate 100, and the buffer layer 200. n-type group III nitride semiconductor layer 300, an active layer 400 grown on the n-type group III nitride semiconductor layer 300, p-type group III nitride semiconductor layer 500, p-type 3 grown on the active layer 400 The p-side electrode 600 formed on the group nitride semiconductor layer 500, the p-side bonding pad 700 formed on the p-side electrode 600, the p-type group III nitride semiconductor layer 500 and the active layer 400 are formed. The n-side electrode 800 and the passivation layer 900 are formed on the n-type group III nitride semiconductor layer 300 exposed by mesa etching.

기판(100)은 동종기판으로 GaN계 기판이 이용되며, 이종기판으로 사파이어 기판, SiC 기판 또는 Si 기판 등이 이용되지만, 3족 질화물 반도체층이 성장될 수 있는 기판이라면 어떠한 형태이어도 좋다. SiC 기판이 사용될 경우에 n측 전극(800)은 SiC 기판 측에 형성될 수 있다.As the substrate 100, a GaN-based substrate is used as the homogeneous substrate, and a sapphire substrate, a SiC substrate, or a Si substrate is used as the heterogeneous substrate. Any substrate may be used as long as the group III nitride semiconductor layer can be grown. When a SiC substrate is used, the n-side electrode 800 may be formed on the SiC substrate side.

기판(100) 위에 성장되는 3족 질화물 반도체층들은 주로 MOCVD(유기금속기상성장법)에 의해 성장된다.Group III nitride semiconductor layers grown on the substrate 100 are mainly grown by MOCVD (organic metal vapor growth method).

버퍼층(200)은 이종기판(100)과 3족 질화물 반도체 사이의 격자상수 및 열팽창계수의 차이를 극복하기 위한 것이며, 미국특허 제5,122,845호에는 사파이어 기판 위에 380℃에서 800℃의 온도에서 100Å에서 500Å의 두께를 가지는 AlN 버퍼층을 성장시키는 기술이 기재되어 있으며, 미국특허 제5,290,393호에는 사파이어 기판 위에 200℃에서 900℃의 온도에서 10Å에서 5000Å의 두께를 가지는 Al(x)Ga(1-x)N (0≤x<1) 버퍼층을 성장시키는 기술이 기재되어 있고, 미국공개특허공보 제2006/154454호에는 600℃에서 990℃의 온도에서 SiC 버퍼층(씨앗층)을 성장시킨 다음 그 위에 In(x)Ga(1-x)N (0<x≤1) 층을 성장시키는 기술이 기재되어 있다. 바람 직하게는 n형 3족 질화물 반도체층(300)의 성장에 앞서 도핑되지 않는 GaN층이 성장되며, 이는 버퍼층(200)의 일부로 보아도 좋고, n형 3족 질화물 반도체층(300)의 일부로 보아도 좋다.The buffer layer 200 is intended to overcome the difference in lattice constant and thermal expansion coefficient between the dissimilar substrate 100 and the group III nitride semiconductor, and US Pat. A technique for growing an AlN buffer layer having a thickness of US Pat. No. 5,290,393 describes Al (x) Ga (1-x) N having a thickness of 10 kPa to 5000 kPa at a temperature of 200 to 900 C on a sapphire substrate. (0 ≦ x <1) A technique for growing a buffer layer is described, and US Patent Publication No. 2006/154454 discloses growing a SiC buffer layer (seed layer) at a temperature of 600 ° C. to 990 ° C., followed by In (x Techniques for growing a Ga (1-x) N (0 <x≤1) layer are described. Preferably, the undoped GaN layer is grown prior to the growth of the n-type group III nitride semiconductor layer 300, which may be viewed as part of the buffer layer 200 or as part of the n-type group III nitride semiconductor layer 300. good.

n형 3족 질화물 반도체층(300)은 적어도 n측 전극(800)이 형성된 영역(n형 컨택층)이 불순물로 도핑되며, n형 컨택층은 바람직하게는 GaN로 이루어지고, Si으로 도핑된다. 미국특허 제5,733,796호에는 Si과 다른 소스 물질의 혼합비를 조절함으로써 원하는 도핑농도로 n형 컨택층을 도핑하는 기술이 기재되어 있다.In the n-type group III nitride semiconductor layer 300, at least a region (n-type contact layer) in which the n-side electrode 800 is formed is doped with impurities, and the n-type contact layer is preferably made of GaN and doped with Si. . U. S. Patent No. 5,733, 796 describes a technique for doping an n-type contact layer to a desired doping concentration by controlling the mixing ratio of Si and other source materials.

활성층(400)은 전자와 정공의 재결합을 통해 광자(빛)를 생성하는 층으로서, 주로 In(x)Ga(1-x)N (0<x≤1)로 이루어지고, 하나의 양자우물층(single quantum well)이나 복수개의 양자우물층들(multi quantum wells)로 구성된다.The active layer 400 is a layer that generates photons (light) through recombination of electrons and holes, and is mainly composed of In (x) Ga (1-x) N (0 <x≤1), and one quantum well layer (single quantum wells) or multiple quantum wells.

p형 3족 질화물 반도체층(500)은 Mg과 같은 적절한 불순물을 이용해 도핑되며, 활성화(activation) 공정을 거쳐 p형 전도성을 가진다. 미국특허 제5,247,533호에는 전자빔 조사에 의해 p형 3족 질화물 반도체층을 활성화시키는 기술이 기재되어 있으며, 미국특허 제5,306,662호에는 400℃ 이상의 온도에서 열처리(annealing)함으로써 p형 3족 질화물 반도체층을 활성화시키는 기술이 기재되어 있고, 미국공개특허공보 제2006/157714호에는 p형 3족 질화물 반도체층 성장의 질소전구체로서 암모니아와 하이드라진계 소스 물질을 함께 사용함으로써 활성화 공정없이 p형 3족 질화물 반도체층이 p형 전도성을 가지게 하는 기술이 기재되어 있다.The p-type III-nitride semiconductor layer 500 is doped with an appropriate impurity such as Mg, and has an p-type conductivity through an activation process. U.S. Patent No. 5,247,533 describes a technique for activating a p-type group III nitride semiconductor layer by electron beam irradiation, and U.S. Patent No. 5,306,662 annealing at a temperature of 400 DEG C or higher to provide a p-type group III nitride semiconductor layer. A technique for activating is described, and US Patent Publication No. 2006/157714 discloses a p-type III-nitride semiconductor layer without an activation process by using ammonia and a hydrazine-based source material together as a nitrogen precursor for growing the p-type III-nitride semiconductor layer. Techniques for having this p-type conductivity have been described.

p측 전극(600)은 p형 3족 질화물 반도체층(500) 전체로 전류가 잘 공급되도 록 하기 위해 구비되는 것이며, 미국특허 제5,563,422호에는 p형 3족 질화물 반도체층의 거의 전면에 걸쳐서 형성되며 p형 3족 질화물 반도체층(500)과 오믹접촉하고 Ni과 Au로 이루어진 투광성 전극(light-transmitting electrode)에 관한 기술이 기재되어 있으며, 미국특허 제6,515,306호에는 p형 3족 질화물 반도체층 위에 n형 초격자층을 형성한 다음 그 위에 ITO(Indium Tin Oxide)로 이루어진 투광성 전극을 형성한 기술이 기재되어 있다.The p-side electrode 600 is provided to provide a good current to the entire p-type group III nitride semiconductor layer 500. US Patent No. 5,563,422 is formed over almost the entire surface of the p-type group III nitride semiconductor layer. And a light-transmitting electrode made of Ni and Au in ohmic contact with the p-type III-nitride semiconductor layer 500 and described in US Patent No. 6,515,306 on the p-type III-nitride semiconductor layer. A technique has been described in which an n-type superlattice layer is formed and then a translucent electrode made of indium tin oxide (ITO) is formed thereon.

한편, p측 전극(600)이 빛을 투과시키지 못하도록, 즉 빛을 기판 측으로 반사하도록 두꺼운 두께를 가지게 형성할 수 있는데, 이러한 기술을 플립칩(flip chip) 기술이라 한다. 미국특허 제6,194,743호에는 20nm 이상의 두께를 가지는 Ag 층, Ag 층을 덮는 확산 방지층, 그리고 확산 방지층을 덮는 Au와 Al으로 이루어진 본딩 층을 포함하는 전극 구조에 관한 기술이 기재되어 있다.On the other hand, the p-side electrode 600 may be formed to have a thick thickness so as not to transmit light, that is, to reflect the light toward the substrate side, this technique is referred to as flip chip (flip chip) technology. U. S. Patent No. 6,194, 743 describes a technique relating to an electrode structure including an Ag layer having a thickness of 20 nm or more, a diffusion barrier layer covering the Ag layer, and a bonding layer made of Au and Al covering the diffusion barrier layer.

p측 본딩 패드(700)와 n측 전극(800)은 전류의 공급과 외부로의 와이어 본딩을 위한 것이며, 미국특허 제5,563,422호에는 n측 전극을 Ti과 Al으로 구성한 기술이 기재되어 있다.The p-side bonding pad 700 and the n-side electrode 800 are for supplying current and wire bonding to the outside, and US Patent No. 5,563,422 describes a technique in which the n-side electrode is composed of Ti and Al.

보호막(900)은 이산화규소와 같은 물질로 형성되며, 생략될 수도 있다.The passivation layer 900 is formed of a material such as silicon dioxide and may be omitted.

한편, n형 3족 질화물 반도체층(300)이나 p형 3족 질화물 반도체층(500)은 단일의 층이나 복수개의 층으로 구성될 수 있으며, 최근에는 레이저 또는 습식 식각을 통해 기판(100)을 3족 질화물 반도체층들로부터 분리하여 수직형 발광소자를 제조하는 기술이 도입되고 있다.Meanwhile, the n-type III-nitride semiconductor layer 300 or the p-type III-nitride semiconductor layer 500 may be composed of a single layer or a plurality of layers, and recently, the substrate 100 may be formed by laser or wet etching. A technique for manufacturing a vertical light emitting device by separating from group III nitride semiconductor layers has been introduced.

도 2는 미국특허 제5,306,662호에 기재된 p형 질화물 반도체층의 성장 방법 의 일 예를 나타내는 도면으로서, TMGa(트리메틸갈륨)과 NH3(암모니아)를 원료가스로 하고, Cp2Mg(싸이클펜타디에닐마그네슘)을 p형 도펀트로 하여 p형 GaN을 성장시킬 때, Mg-H 복합체가 형성되어 Mg이 도펀트로 기능하지 못하는 문제점을 해소하기 위하여, 열처리를 통해 활성화시키는 기술이 기재되어 있으나, 이러한 방법으로도 상당수의 Mg이 본래의 역할을 하지 못하고 있어 도핑효율은 개선의 여지가 있다.FIG. 2 is a view showing an example of a growth method of a p-type nitride semiconductor layer described in US Pat. No. 5,306,662, wherein TMGa (trimethylgallium) and NH 3 (ammonia) are used as raw materials, and Cp 2 Mg (cyclepentadier) is used. In order to solve the problem that Mg-H composite is formed and Mg does not function as a dopant when growing p-type GaN with p-type dopant, a technique of activating through heat treatment is described. Even though a large amount of Mg does not play an original role, the doping efficiency has room for improvement.

이에 대하여 '발명의 실시를 위한 구체적인 내용'의 후단에 기술한다.This will be described later in the Specification for Implementation of the Invention.

여기서는, 본 개시의 전체적인 요약(Summary)이 제공되며, 이것이 본 개시의 외연을 제한하는 것으로 이해되어서는 아니된다(This section provides a general summary of the disclosure and is not a comprehensive disclosure of its full scope or all of its features).SUMMARY OF THE INVENTION Herein, a general summary of the present disclosure is provided, which should not be construed as limiting the scope of the present disclosure. of its features).

본 개시에 따른 일 태양에 의하면(According to one aspect of the present disclosure), 전자와 정공의 재결합을 통해 빛을 생성하는 활성층과 정공을 공급하는 적어도 하나의 p형층을 포함하는 복수개의 질화물 반도체층을 가지는 3족 질화물 반도체 발광소자를 제조하는 방법에 있어서, 활성층을 형성하는 제1 단계; 그리고 적어도 하나의 p형층을 형성하는 제2 단계;로서, GaN 및 MgN를 복수회 처리하는 과정을 가지는 제2 단계;를 포함하는 것을 특징으로 하는 3족 질화물 반도체 발광소자를 제조하는 방법이 제공된다.According to one aspect of the present disclosure, a plurality of nitride semiconductor layers including an active layer that generates light through recombination of electrons and holes and at least one p-type layer that supplies holes are provided. A method of manufacturing a group III nitride semiconductor light emitting device having: a first step of forming an active layer; And a second step of forming at least one p-type layer; a second step having a process of processing GaN and MgN a plurality of times; and a method for manufacturing a Group III nitride semiconductor light emitting device comprising the .

이에 대하여 '발명의 실시를 위한 구체적인 내용'의 후단에 기술한다.This will be described later in the Specification for Implementation of the Invention.

이하, 본 개시를 첨부된 도면을 참고로 하여 자세하게 설명한다(The present disclosure will now be described in detail with reference to the accompanying drawing(s)). The present disclosure will now be described in detail with reference to the accompanying drawing (s).

도 3은 본 개시에 따라 3족 질화물 반도체 발광소자를 제조하는 방법의 일 예를 나타내는 도면으로서, 먼저 활성층(40) 상에 제1 p형층(51)을 성장시킨 후 제2 p형층(52)을 성장시키는 방법이 제시되어 있다. 먼저 MgN(21) 처리가 행해진다. 다음으로 1차 3족 질화물 반도체층(S1)이 투입된다. 그리고 다시 2차 MgN 처리(21)가 행해진다. 이후 이러한 과정이 n차까지 반복된 후 제3 p형층(53)이 성장된다. MgN 처리(21)를 중간에 반복하여 3족 질화물 반도체(Sn)를 성장시키는 과정에서 MgN의 결합형태로 GaN에 Mg이 포함되기 때문에 추가적인 치환 과정이 필요없게 되어 활성화 과정에서의 도핑 효율을 증대시킬 수 있다. 이때, 제 2 p형층(52)에 MgN를 처리하는 이유는 p-GaN에서 발생하는 빛의 흡수를 최소화하기 위함이다. 일반적으로 GaN에 Mg을 도핑하는 경우, 활성층(40)에서 발광되는 빛이 p-GaN에서 흡수되는데 흡수되는 정도는 마그네슘의 도핑 양에 비례하기 때문이다. 제1 p형층(51)은 활성층(40)에 정공을 공급하는 층으로서 많은 양의 마그네슘 도핑이 필요한데, 이러한 제1 p형층(51)에 MgN 및 GaN를 반복하여 처리하면 충분한 정공을 얻을 수 없어 광특성 및 출력전력이 저하되는 문제점이 있다. 이러한 점을 고려하여 제2 p형층(52)에 한정하여 MgN 및 GaN를 반복하여 처리하는 것이 바람직하다. 제 2 p형층의 성장온도는 700℃ 내지 1000℃이고, MgN의 처리시간은 1 내지 10초이며, CP2Mg는 35℃의 온도와 900torr의 압력에서 200cc 내지 2000cc 주입하고 GaN의 성장율은 4 내지 10 Å/sec의 범위에서 형성하였다.3 is a view illustrating an example of a method of manufacturing a group III nitride semiconductor light emitting device according to the present disclosure. First, the first p-type layer 51 is grown on the active layer 40, and then the second p-type layer 52 is formed. A method of growing is shown. First, MgN 21 processing is performed. Next, the primary group III nitride semiconductor layer S 1 is introduced. Then, the second MgN process 21 is performed again. After this process is repeated up to nth order, the third p-type layer 53 is grown. In the process of growing the group III nitride semiconductor (S n ) by repeating the MgN treatment 21 in the middle, Gag is included in the form of MgN in the form of MgN, thereby eliminating the need for additional substitution, thereby increasing the doping efficiency in the activation process. You can. At this time, the reason for processing MgN in the second p-type layer 52 is to minimize the absorption of light generated from p-GaN. In general, when Mg is doped into GaN, light emitted from the active layer 40 is absorbed in p-GaN, because the degree of absorption is proportional to the doping amount of magnesium. The first p-type layer 51 is a layer for supplying holes to the active layer 40, and a large amount of magnesium doping is required. If the first p-type layer 51 is repeatedly treated with MgN and GaN, sufficient holes cannot be obtained. There is a problem that the optical characteristics and output power is lowered. In view of this, it is preferable to repeatedly process MgN and GaN only in the second p-type layer 52. The growth temperature of the second p-type layer is 700 ℃ to 1000 ℃, the treatment time of MgN is 1 to 10 seconds, CP 2 Mg is injected 200cc to 2000cc at a temperature of 35 ℃ and 900torr and the growth rate of GaN is 4 to It formed in the range of 10 ms / sec.

도 4는 본 개시에 따른 3족 질화물 반도체 발광소자의 일 예를 나타내는 도면으로서, 3족 질화물 반도체 발광소자는 기판(10), 기판(10) 위에 성장되는 버퍼층(20), 버퍼층(20) 위에 성장되는 n형 3족 질화물 반도체층(30), n형 3족 질화물 반도체층(30) 위에 성장되는 활성층(40), 활성층(40) 위에 성장되는 제1 p형층(51), 제1 p형층(51) 위에 형성되는 제2 p형층(52), 제2 p형층(52) 위에 형성되는 제3 p형층(53), 제3 p형층(53) 위에 형성되는 p측 전극(60), p측 전극(60) 위에 형성되는 p측 본딩 패드(70), 제1 p형층(51)및 제2 p형층(52)과 활성층(40)이 메사 식각되어 노출된 n형 3족 질화물 반도체층(30) 위에 형성되는 n측 전극(80), 그리고 보호막(90)을 포함한다.4 is a diagram illustrating an example of a group III nitride semiconductor light emitting device according to the present disclosure, wherein the group III nitride semiconductor light emitting device is disposed on a substrate 10, a buffer layer 20, and a buffer layer 20 grown on the substrate 10. N-type III-nitride semiconductor layer 30 to be grown, active layer 40 to be grown on n-type III-nitride semiconductor layer 30, first p-type layer 51 to be grown on active layer 40, and first p-type layer The second p-type layer 52 formed on the 51, the third p-type layer 53 formed on the second p-type layer 52, the p-side electrode 60 formed on the third p-type layer 53, and p The n-type group III nitride semiconductor layer in which the p-side bonding pad 70, the first p-type layer 51, the second p-type layer 52, and the active layer 40 formed on the side electrode 60 are mesa-etched and exposed. 30, the n-side electrode 80 and the passivation layer 90 are formed.

도 5는 본 개시에 따라 3족 질화물 반도체 발광소자를 형성하는 단계에서 MgN와 GaN의 처리시간 변화에 따른 순방향전압(Vf1)과 출력전력(Power)의 측정값을 나타내는 도면이다. MgN을 과도하게 처리하는 경우에는 순방향전압은 낮으나, 출력전력도 낮게 측정되는 것을 알 수 있다. 이는 Mg이 GaN 반도체 내에 과도하게 도핑이 되어 활성층(40)에서 발광하는 광의 흡수가 증가하기 때문인 것으로 생각된다. 따라서 MgN/GaN의 반복 적층은 층 전체로서 도핑 농도가 높은 제1 p형층(51) 및 제3 p형층(53)에 적용하는 것보다 제2 p형층(52)에 적용하는 것이 바람직하다는 것을 알 수 있다. 한편 MgN을 처리하지 않는 경우에는 출력전력은 일정수준 이상이나, 순방향전압도 높아지는 것을 알 수 있다. 이는 p형층의 도핑농도가 낮아 상대적으로 전자와 정공의 재결합이 원활하게 이루어지지 않기 때문인 것으로 생각된다. 이 러한 점을 고려하여 예를 들어, MgN은 3초, GaN은 21초로 40주기 동안 교대 성장함으로써 제2 p형층(52)을 형성할 수 있으며, 이때 제2 p형층의 각각의 GaN의 막두께는 20 내지 50Å으로 이루어질 수 있다. 그리고 제2 p형층의 MgN처리에 대한 Mg 함량이 제1 p형층의 Mg 함량과 제3 p형층의 Mg 함량보다 적도록 하면 낮은 Mg 함량에서도 p형 특성을 유지할 수 있어 발광 효율 개선에 도움이 되며, p형층 막질의 개선으로 인해 정전내전압을 높일 수 있다. FIG. 5 is a view showing measured values of the forward voltage Vf 1 and the output power according to the processing time change of MgN and GaN in the step of forming a group III nitride semiconductor light emitting device according to the present disclosure. When the MgN is excessively processed, it can be seen that the forward voltage is low but the output power is also low. This is considered to be because Mg is excessively doped in the GaN semiconductor to increase the absorption of light emitted from the active layer 40. Therefore, it is understood that the repeated lamination of MgN / GaN is preferably applied to the second p-type layer 52 rather than to the first p-type layer 51 and the third p-type layer 53 having a high doping concentration as a whole layer. Can be. On the other hand, when the MgN is not processed, the output power is higher than a certain level, but it can be seen that the forward voltage also increases. It is thought that this is because the doping concentration of the p-type layer is relatively low and the recombination of electrons and holes is not performed smoothly. In view of this point, for example, the second p-type layer 52 can be formed by alternating growth of MgN for 3 seconds and GaN for 21 seconds for 40 cycles, wherein the thickness of each GaN of the second p-type layer is formed. May be made from 20 to 50 Hz. In addition, if the Mg content of MgN treatment of the second p-type layer is less than the Mg content of the first p-type layer and the Mg content of the third p-type layer, it is possible to maintain the p-type characteristics even at low Mg content, thereby improving the luminous efficiency. As a result, the dielectric breakdown voltage can be increased due to the improvement of the p-type layer film quality.

이하 본 개시의 다양한 실시 형태에 대하여 설명한다.Various embodiments of the present disclosure will be described below.

(1) 전자와 정공의 재결합을 통해 빛을 생성하는 활성층과 정공을 공급하는 적어도 하나의 p형층을 포함하는 복수개의 질화물 반도체층을 가지는 3족 질화물 반도체 발광소자를 제조하는 방법에 있어서, 활성층을 형성하는 제1 단계; 그리고 적어도 하나의 p형층을 형성하는 제2 단계;로서, GaN 및 MgN를 복수회 처리하는 과정을 가지는 제2 단계;를 포함하는 것을 특징으로 하는 3족 질화물 반도체 발광소자를 제조하는 방법.(1) A method of manufacturing a group III nitride semiconductor light emitting device having a plurality of nitride semiconductor layers comprising an active layer for generating light through recombination of electrons and holes and at least one p-type layer for supplying holes, wherein the active layer is Forming a first step; And a second step of forming at least one p-type layer, the second step having a process of processing GaN and MgN a plurality of times.

(2) 적어도 하나의 P형층은 제1 p형층, 제2 p형층 그리고 제3 p형층을 포함하며, 제2 p형층이 GaN 및 MgN를 복수회 처리하는 과정을 통해 형성되는 것을 특징으로 하는 3족 질화물 반도체 발광소자를 제조하는 방법.(2) at least one P-type layer includes a first p-type layer, a second p-type layer, and a third p-type layer, wherein the second p-type layer is formed through a process of treating GaN and MgN a plurality of times. A method of manufacturing a group nitride semiconductor light emitting device.

(3) 제2 p형층의 Mg 도프량이 제1 p형층 및 제3 p형층의 Mg 도프량보다 적은 것을 특징으로 하는 3족 질화물 반도체 발광소자를 제조하는 방법. (3) A method for manufacturing a group III nitride semiconductor light emitting device, characterized in that the amount of Mg dope in the second p-type layer is less than the amount of Mg dope in the first p-type layer and the third p-type layer.

(4) GaN 및 MgN를 복수회 처리하는 과정에서 GaN 처리시 그 막두께가 20 내지 50Å것을 특징으로 하는 3족 질화물 반도체 발광소자를 제조하는 방법.(4) A method of manufacturing a group III nitride semiconductor light emitting device, characterized in that its film thickness is 20 to 50 GPa during GaN treatment in the process of treating GaN and MgN multiple times.

본 개시에 따른 하나의 3족 질화물 반도체 발광소자에 의하면, 도핑효율이 개선된 고품질의 반도체 박막을 형성할 수 있게 된다.According to one group III nitride semiconductor light emitting device according to the present disclosure, it is possible to form a high quality semiconductor thin film having improved doping efficiency.

또한 본 개시에 따른 다른 3족 질화물 반도체 발광소자에 의하면, 순방향전압이 감소하고 출력전력이 향상된 반도체 박막을 형성할 수 있게 된다.In addition, according to another group III nitride semiconductor light emitting device according to the present disclosure, it is possible to form a semiconductor thin film having a reduced forward voltage and improved output power.

도 1은 종래의 3족 질화물 반도체 발광소자의 일 예를 나타내는 도면,1 is a view showing an example of a conventional group III nitride semiconductor light emitting device,

도 2는 미국특허 제5,306,662호에 기재된 p형 질화물 반도체층의 성장 방법의 일 예를 나타내는 도면,2 is a view showing an example of a growth method of a p-type nitride semiconductor layer described in US Patent No. 5,306,662,

도 3은 본 개시에 따라 3족 질화물 반도체 발광소자를 제조하는 방법의 일 예를 나타내는 도면,3 is a view showing an example of a method of manufacturing a group III nitride semiconductor light emitting device according to the present disclosure;

도 4은 본 개시에 따른 3족 질화물 반도체 발광소자의 일 예를 나타내는 도면,4 is a view showing an example of a group III nitride semiconductor light emitting device according to the present disclosure;

도 5는 본 개시에 따라 3족 질화물 반도체 발광소자를 형성하는 단계에서 MgN와 GaN의 처리시간 변화에 따른 순방향전압(Vf1)과 출력전력(Power)의 측정값을 나타내는 도면.5 is a view showing measured values of the forward voltage (Vf 1 ) and the output power (Power) according to the processing time change of MgN and GaN in the step of forming a group III nitride semiconductor light emitting device according to the present disclosure.

Claims (4)

전자와 정공의 재결합을 통해 빛을 생성하는 활성층과 정공을 공급하는 적어도 하나의 p형층을 포함하는 복수개의 질화물 반도체층을 가지는 3족 질화물 반도체 발광소자를 제조하는 방법에 있어서,In the method of manufacturing a Group III nitride semiconductor light emitting device having a plurality of nitride semiconductor layer comprising an active layer for generating light through recombination of electrons and holes and at least one p-type layer for supplying holes, 활성층을 형성하는 제1 단계; 그리고A first step of forming an active layer; And 적어도 하나의 p형층을 형성하는 제2 단계;로서,A second step of forming at least one p-type layer; GaN 및 MgN를 복수회 처리하는 과정을 가지는 제2 단계;를 포함하는 것을 특징으로 하는 3족 질화물 반도체 발광소자를 제조하는 방법.And a second step of treating GaN and MgN a plurality of times. 청구항 1에 있어서,The method according to claim 1, 적어도 하나의 P형층은 제1 p형층, 제2 p형층 그리고 제3 p형층을 포함하며, 제2 p형층이 GaN 및 MgN를 복수회 처리하는 과정을 통해 형성되는 것을 특징으로 하는 3족 질화물 반도체 발광소자를 제조하는 방법.The at least one P-type layer includes a first p-type layer, a second p-type layer, and a third p-type layer, wherein the second p-type layer is formed by a process of treating GaN and MgN a plurality of times. Method of manufacturing a light emitting device. 청구항 2에 있어서,The method according to claim 2, 제2 p형층의 Mg 도프량이 제1 p형층 및 제3 p형층의 Mg 도프량보다 적은 것을 특징으로 하는 3족 질화물 반도체 발광소자를 제조하는 방법. A method of manufacturing a group III nitride semiconductor light emitting device, characterized in that the amount of Mg dope of the second p-type layer is less than the amount of Mg dope of the first p-type layer and the third p-type layer. 청구항 1 내지 청구항 3 중의 어느 한 항에 있어서,The method according to any one of claims 1 to 3, GaN 및 MgN를 복수회 처리하는 과정에서 GaN 처리시 그 막두께가 20 내지 50Å것을 특징으로 하는 3족 질화물 반도체 발광소자를 제조하는 방법.A method of manufacturing a group III nitride semiconductor light emitting device, characterized in that the film thickness is 20 to 50 GPa during the GaN treatment in the course of the GaN and MgN treatment a plurality of times.
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CN105304780A (en) * 2014-06-25 2016-02-03 南通同方半导体有限公司 P-GaN blue light LED epitaxy structure with high hole concentration
CN115295697A (en) * 2022-10-09 2022-11-04 江西兆驰半导体有限公司 Light emitting diode epitaxial wafer, preparation method thereof and light emitting diode

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