WO2010137076A1 - Dispositif de mesure d'impulsions, procédé de mesure d'impulsions et appareil d'essai utilisant le dispositif et le procédé - Google Patents

Dispositif de mesure d'impulsions, procédé de mesure d'impulsions et appareil d'essai utilisant le dispositif et le procédé Download PDF

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Publication number
WO2010137076A1
WO2010137076A1 PCT/JP2009/002365 JP2009002365W WO2010137076A1 WO 2010137076 A1 WO2010137076 A1 WO 2010137076A1 JP 2009002365 W JP2009002365 W JP 2009002365W WO 2010137076 A1 WO2010137076 A1 WO 2010137076A1
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signal
pulse
condition
gate
determination unit
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PCT/JP2009/002365
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English (en)
Japanese (ja)
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田中幸一
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株式会社アドバンテスト
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Priority to JP2010507737A priority Critical patent/JPWO2010137076A1/ja
Priority to PCT/JP2009/002365 priority patent/WO2010137076A1/fr
Publication of WO2010137076A1 publication Critical patent/WO2010137076A1/fr

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
    • G01R29/02—Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration

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  • the present invention relates to a technique for measuring the characteristics of a pulse signal.
  • test equipment semiconductor test equipment
  • the test apparatus can supply an accurate power supply voltage according to the design of the user to the semiconductor device to be measured (hereinafter, referred to as a device under test DUT) and can apply a test pulse at an accurate timing. Is required.
  • system initialization for the test apparatus is performed prior to the test so that the test apparatus can exhibit its planned performance.
  • various adjustments are executed after minimizing the power supply voltage fluctuation in the test apparatus by minimizing the internal operation of the system. Specifically, a method is adopted in which a reference clock that is close to an ideal state is generated in a static state, and the delay amount of a signal to be adjusted is measured and adjusted using this reference clock.
  • the test equipment is equipped with a device that suppresses fluctuations in the power supply environment and temperature environment regardless of the operating state, or the test equipment can be designed to meet the design specifications by estimating the amount of fluctuation that can occur in advance by simulation. It is done.
  • it is difficult to completely model with the current simulation technology, and it is rare that the actual clock jitter coincides with the simulation result. Therefore, the actual evaluation of the clock jitter is indispensable.
  • the clock pulse can pass through and propagate through the LSI because of its short pulse width, but cannot pass through the I / O circuit of the LSI, making it difficult to measure with a measuring instrument. Even if the clock pulse is taken out from the LSI, the pulse width fluctuates due to the waveform distortion in the path to the measuring instrument, which causes measurement error or the pulse disappears and becomes impossible to measure.
  • the present invention has been made in view of such a problem, and one of exemplary purposes of an aspect thereof is to provide a technique capable of appropriately evaluating clock jitter.
  • One embodiment of the present invention relates to a measurement apparatus for a pulse signal such as a clock signal.
  • the pulse measuring device receives the pulse signal, holds the pulse width of the pulse signal in the first state as a reference as a reference pulse width, has a reference pulse width in the second state corresponding to the actual operation state, and measures
  • a replica signal generator for generating a replica signal having a leading edge corresponding to the leading edge of the target pulse signal; and receiving the pulse signal and the replica signal; in the second state, the edge of the pulse signal and the edge of the replica signal
  • a condition determination unit that determines whether or not the phase relationship satisfies a predetermined condition; and a count processing unit that performs a count process according to a determination result in the condition determination unit. According to this aspect, it is possible to evaluate the phase fluctuation and pulse width fluctuation of the pulse signal in the actual operation state.
  • the characteristics of the pulse signal in the actual operation state can be evaluated.
  • FIG. 2 is a circuit diagram illustrating a configuration example of a replica signal generation unit in FIG. 1. It is a circuit diagram which shows the structural example of the condition determination part of FIG.
  • FIGS. 5A to 5E are time charts showing the operation of the condition determining unit in FIG.
  • FIG. 2 is a circuit diagram illustrating a configuration example of a loop measurement circuit in FIG. 1. It is a flowchart which shows an example of operation
  • FIG. 1 is a block diagram showing a configuration of a pulse measuring apparatus 100 according to the embodiment.
  • the pulse generator 102 generates a timing pulse Clock_out having a predetermined frequency and a predetermined pulse width.
  • the timing pulse Clock_out has a pulse width and a phase characteristic according to a design value in an ideal state. However, the characteristics of the timing pulse Clock_out change from moment to moment as the power supply voltage supplied to the pulse generator 102 changes and the temperature changes.
  • the pulse generator 102 is used in the semiconductor test apparatus 1, for example.
  • FIG. 2 is a block diagram illustrating a configuration example of the test apparatus 1.
  • the test apparatus 1 includes a pattern generator PG, a timing generator TG, a waveform shaper (also referred to as a format controller) FC, a driver DR, a timing comparator TC, a logic comparison unit LC, and a power source PS.
  • Test apparatus 1 supplies a test pattern to DUT 2.
  • the DUT 2 outputs a signal corresponding to the given test pattern.
  • the DUT 2 is a memory, for example.
  • the test apparatus 1 receives the signal output from the DUT 2, compares it with an expected value, determines the quality of the DUT 2, or identifies the defective part.
  • the test pattern cycle is also called the test rate.
  • the test apparatus 1 has a function of changing the test rate in real time every moment for each bit of pattern data.
  • the pattern generator PG generates pattern data indicating the value of the test pattern to be supplied to the test apparatus 1 and timing data indicating the transition timing (that is, the test rate) of each data.
  • the timing generator TG receives timing data and generates a timing signal having an edge at a timing corresponding to the value.
  • the waveform shaper FC generates a test pattern to be supplied to the DUT 2 based on the timing signal and pattern data.
  • the driver DR receives the output signal of the waveform shaper FC and supplies it to the DUT 2.
  • Timing comparator TC receives the data output from DUT 2 and determines its logical value.
  • the logic comparator LC compares the output data of the timing comparator TC and the value of the expected value data, and generates a pass / fail signal P / F indicating whether or not they match.
  • the quality of DUT2 is determined based on the pass / fail signal P / F.
  • the power supply PS supplies a stable power supply voltage Vdd to each block of the test apparatus 1.
  • the test apparatus 1 includes a pulse generator 102 that generates a clock signal (corresponding to the timing pulse Clock_out in FIG. 1) to be used as a reference by the timing generator TG.
  • a pulse generator 102 that generates a clock signal (corresponding to the timing pulse Clock_out in FIG. 1) to be used as a reference by the timing generator TG.
  • the operation state of the pulse generator 102 will be examined.
  • the pulse generation unit 102 will generate a timing pulse Clock_out having a pulse width and phase in accordance with the design value in a state where there is no temperature fluctuation and no power supply voltage fluctuation.
  • the characteristics of the timing pulse Clock_out change from moment to moment due to the influence of heat generation caused by the operation of various blocks in the test apparatus 1 and the influence of the output fluctuation of the power supply PS.
  • this state is referred to as an actual operation state (second state).
  • the test apparatus 1 is configured to be able to operate the pulse generator 102 stably by controlling the operation state. For example, by stopping the operation of unnecessary blocks (for example, the pattern generator PG and the timing generator TG) other than the pulse generator 102, fluctuations in the power supply voltage Vdd and temperature fluctuations can be suppressed as much as possible.
  • This state is referred to as a first state.
  • the first state is a state serving as a reference for stabilizing the timing pulse Clock_out as compared with the actual operation state (second state).
  • the pulse measuring apparatus 100 evaluates the characteristics of the timing pulse Clock_out generated by the pulse generator 102. Examples of the characteristics to be evaluated include the pulse width and phase characteristics (jitter amount) of the timing pulse Clock_out.
  • the pulse measuring apparatus 100 includes a replica signal generation unit 10, a condition determination unit 20, a count processing unit 30, and a bias power supply 50. Along with the pulse measuring apparatus 100, a loop measuring circuit 40 is provided.
  • the bias power supply 50 generates a power supply voltage Vdd for each block of the pulse measuring apparatus 100. That is, the power source for the pulse measuring apparatus 100 is independent of the power source PS of the pulse generator 102 that generates the timing pulse Clock_out. That is, the power supply voltage of the pulse measuring device 100 is independent from the surroundings, and can be said to be stable regardless of the first state and the second state.
  • a timing pulse Clock_out is input to the replica signal generator 10.
  • the replica signal generation unit 10 holds the pulse width of the timing pulse Clock_out as the reference pulse width.
  • the replica signal generator 10 In the second state (actual operation state), the replica signal generator 10 generates a replica signal REPLICA.
  • the replica signal REPLICA has a reference pulse width, and the leading edge timing is in accordance with the leading edge timing of the timing pulse Clock_out.
  • FIG. 3 is a circuit diagram showing a configuration example of the replica signal generator 10 of FIG.
  • the replica signal generator 10 includes AND gates 12_A, 12_1 to 12_5, OR gates 14_1 to 14_5, delay elements 15_1 to 15_5, and an output AND gate 16.
  • control signals CTRLA and CTRLB1 to CTRLB5 are input to the replica signal generator 10. Note that the number of control signals CTRLB may be arbitrary.
  • the control signal CTRLA is a control signal for the entire replica signal generator 10, and is active when the replica signal generator 10 is high level (“1”, asserted) and inactive when the replica signal generator 10 is low level (“0”, negated). It becomes.
  • Control signals CTRLB1 to CTRLB5 are used to adjust the pulse width of the replica signal REPLICA.
  • the AND gate 12_A generates a logical product of the timing pulse Clock_out and the control signal CTRLA.
  • the i-th AND gate 12_i (1 ⁇ i ⁇ 5) generates a logical product of the timing pulse Clock_out and the i-th control signal CTRLBi.
  • the i-th (2 ⁇ i ⁇ 5) OR gate 14 — i generates a logical sum of the output signal of the i ⁇ 1-th delay element 15 — (i ⁇ 1) and the output signal of the i-th AND gate 12 — i.
  • the first OR gate 14_1 generates a logical sum of the low level and the output signal of the first AND gate 12_1.
  • the OR gate 14_1 is redundant as an arithmetic process and may be omitted. However, the OR gate 14_1 is significant from the viewpoint of aligning the delay amount of each signal path.
  • the i-th delay element 15_i gives a predetermined delay to the output signal of the i-th OR gate 14_i.
  • the output AND gate 16 generates a logical product of the inversion of the output signal of the final stage (fifth) delay element 15_5 and the output signal of the AND gate 12A, and outputs the logical product as the replica signal REPLICA.
  • the pulse width of the replica signal REPLICA is set according to the values of the control signals CTRLB1 to CTRLB5.
  • the timing of the leading edge of the replica signal REPLICA coincides with that of the timing pulse Clock_out.
  • the condition determination unit 20 receives the replica signal REPLICA generated by the replica signal generation unit 10 and the timing pulse Clock_out. In the second state, the condition determination unit 20 determines whether the phase relationship between the edge of the timing pulse Clock_out and the edge of the replica signal REPLICA satisfies a predetermined condition.
  • the condition determination unit 20 determines at least one of the following four conditions. 1.
  • First condition Is the leading edge of the timing pulse Clock_out delayed from the leading edge of the replica signal REPLICA?
  • Third condition Does the leading edge of the timing pulse Clock_out advance with respect to the leading edge of the replica signal REPLICA?
  • the condition determination unit 20 determines all the first to fourth conditions.
  • FIG. 4 is a circuit diagram illustrating a configuration example of the condition determination unit 20 of FIG.
  • the condition determination unit 20 includes first determination units 21 to 24 and a target signal generation unit 25 that determine the first condition to the fourth condition, respectively.
  • the condition determination unit 20 receives a timing pulse Clock_out to be evaluated and a control signal CTRLC.
  • the control signal CTRLC instructs the condition determination unit 20 to switch between active and inactive.
  • the target signal generation unit 25 includes AND gates 12C and 16C.
  • the AND gate 12C generates a logical product of the timing pulse Clock_out and the control signal CTRLC.
  • the AND gate 16C generates a logical product of the output signal of the AND gate 12C and a fixed level (high level), and outputs the logical product as the target signal Target.
  • the AND gate 16C is redundant in terms of arithmetic processing, but is provided to eliminate a phase shift between the replica signal REPLICA generated by the replica signal generation unit 10 of FIG. 3 and the target signal Target. That is, the AND gate 12C in FIG. 4 corresponds to the AND gate 12A in FIG. 3, and the AND gate 16C in FIG. 4 corresponds to the AND gate 16A in FIG. 3, and the generation path of the target signal Target and the replica signal
  • the delay amount of the generation path of REPLICA is designed to be almost equal.
  • the first determination unit 21 receives the control signal cont1 in addition to the target signal Target corresponding to the determination target timing pulse Clock_out.
  • the first delay element D1 delays the target signal Target by a predetermined time TD1.
  • the AND gate A11 gates (logical product) the output signal of the first delay element D1 in accordance with the control signal cont1.
  • the control signal cont1 is at a low level (negate)
  • the first determination unit 21 is inactive.
  • the control signal cont1 is at a high level (asserted)
  • the first determination unit 21 is active.
  • the AND gate A11 may be provided in another path.
  • the first OR gate O1 generates a logical sum of the output signal of the AND gate A11 (that is, the output signal of the first delay element D1) and the original target signal Target before being delayed.
  • the first negative gate N1 inverts the logic level of the output signal of the first OR gate O1.
  • the first skew adjusting delay element R1 is provided to adjust the skew by giving an adjustable delay to the replica signal REPLICA. The skew adjustment will be described later.
  • the first AND gate A1 generates a logical product of the replica signal REPLICA (SR1) that has passed through the first skew adjustment delay element R1 and the output signal of the first negative gate N1.
  • the output signal of the first AND gate A1 becomes high level (asserted) when the first condition is satisfied.
  • the second determination unit 22 receives the control signal cont2 in addition to the target signal Target corresponding to the timing pulse Clock_out.
  • the second skew adjusting delay element R2 adjusts the timing by giving an adjustable delay to the replica signal REPLICA.
  • the second negative gate N2 inverts the timing-adjusted replica signal REPLICA.
  • the third negative gate N3 inverts the target signal Target.
  • the second delay element D2 gives a second delay TD2 to the output signal of the third negative gate N3.
  • the AND gate A12 gates the output signal of the second delay element D2 by the control signal cont2.
  • the second OR gate O2 generates a logical sum of the output signal of the third negative gate N3 and the output signal of the second delay element D2.
  • the fourth negative gate N4 inverts the output signal of the second OR gate O2.
  • the second AND gate A2 generates a logical product of the output signal SR2 of the second negative gate N2 and the output signal of the fourth negative gate N4.
  • the output signal of the second AND gate A2 becomes high level (asserted) when the second condition is satisfied.
  • the third determination unit 23 receives the control signal cont3 in addition to the target signal Target corresponding to the timing pulse Clock_out.
  • the third delay element D3 delays the replica signal REPLICA by a third delay time TD3.
  • the AND gate A13 gates the output signal of the third delay element D3 according to the control signal cont3.
  • the third OR gate O3 generates a logical sum of the replica signal REPLICA and the output signal of the third delay element D3.
  • the fifth negative gate N5 inverts the output signal of the third OR gate O3.
  • the third skew adjusting delay element R3 gives an adjustable delay to the target signal Target.
  • the third AND gate A3 generates a logical product of the output signal of the fifth negative gate N5 and the target signal Target (SR3) whose timing is adjusted.
  • the output signal of the third AND gate A3 becomes high level (asserted) when the third condition is satisfied.
  • the fourth determination unit 24 receives the control signal cont4 in addition to the target signal Target corresponding to the timing pulse Clock_out.
  • the sixth negative gate N6 inverts the replica signal REPLICA.
  • the fourth delay element D4 delays the output signal of the sixth negative gate N6 by a fourth delay time TD4.
  • the AND gate A14 gates the output signal of the fourth delay element D4 according to the control signal cont4.
  • the fourth OR gate O4 generates a logical sum of the output signal of the sixth negative gate N6 and the output signal of the fourth delay element D4.
  • the seventh negative gate N7 inverts the output signal of the fourth OR gate O4.
  • the fourth skew adjusting delay element R4 gives an adjustable delay to the target signal Target.
  • the eighth negative gate N8 inverts the target signal Target whose timing is adjusted.
  • the fourth AND gate A4 generates a logical product of the output signal of the seventh negative gate N7 and the output signal SR4 of the eighth negative gate N8. When the fourth condition is satisfied, the output signal of the fourth AND gate A4 becomes high level (asserted).
  • the output signals of the first determination unit 21 to the fourth determination unit 24 are input to the clock terminals of the first latch L1 to the fourth latch L4, respectively.
  • the output signal of the i-th latch Li becomes high level.
  • the selector (multiplexer) M3 selects one of the replica signal REPLICA and the target signal Target according to the control signal S3.
  • the delay element D13 adjusts the timing of the output signal of the selector M3.
  • the output signal S13 of the delay element D13 is referred to as a synchronization signal.
  • the output signals of the latches L1 to L4 are retimed using the synchronization signal S13 in the subsequent result latches Lr1 to Lr4.
  • the output signals (result signals) result1 to result4 of the result latches Lr1 to Lr4 are high when the first to fourth conditions are satisfied.
  • the condition determination unit 20 receives a reset signal RESET that is asserted (high level) at every predetermined timing.
  • the negative gate N9 inverts the reset signal RESET.
  • the inverted reset signal RESET is input to reset terminals (inverted logic) of the result latches Lr1 to Lr4. That is, the result latches Lr1 to Lr4 are reset at every predetermined timing, and the output Q is set to the low level (0).
  • the OR gate O6 includes an inverting input and an inverting output. An OR gate O6 is provided for each of the latches L1 to L4. Each OR gate O6 receives the inverted reset signal RESET and the inverted output (#Q) of the corresponding result latch Lr.
  • the output of the OR gate O6 is input to the reset terminal (inverted logic) of the corresponding latch L. That is, the i-th latch Li is reset each time the reset signal RESET is asserted or the output Q of the corresponding result latch Lri becomes high level (1).
  • FIGS. 5A to 5E are time charts showing the operation of the condition determining unit 20 of FIG.
  • FIG. 5A shows the replica signal REPLICA input to the condition determining unit 20 in the second state and the target signals Target 1 to 5 whose phase and pulse width have changed.
  • Target 1 indicates a state in which the phase of the pulse is advanced
  • Target 2 indicates a state in which there is no phase fluctuation
  • Target 3 indicates a state in which the phase is delayed
  • Target 4 indicates a state in which the pulse width is widened
  • Target 5 indicates a state in which the pulse width is narrowed.
  • FIGS. 5B to 5E show operations of the first determination unit 21 to the fourth determination unit 24, respectively.
  • the waveforms shown in FIGS. 5B to 5E are signals X1 and X2 received by the first AND gate A1 to the fourth AND gate A4, respectively.
  • the dot portion of the waveform indicates a delay caused by the delay elements D1 to D4, and the logic level is low.
  • the hatched portion indicates that the output of the AND gate becomes high level. Also from this time chart, it is confirmed that the first determination unit 21 to the fourth determination unit 24 determine the first condition to the fourth condition, respectively.
  • Signals SR1 to SR4 that have passed through the first skew adjustment delay elements R1 to R4 are input to the loop measurement circuit 40 described later.
  • the count processing unit 30 receives the result 1 to result 4 as a result of the condition determination by the condition determination unit 20.
  • the count processing unit 30 performs count processing according to the determination results result1 to result4.
  • the count processing unit 30 counts the number of times each of the determination results result1 to result4 is asserted.
  • the count processing unit 30 is configured as follows.
  • FIG. 6 is a circuit diagram showing a configuration example of the count processing unit 30 in FIG.
  • the count processing unit 30 includes AND gates A31 to A34 and counters CNT1 to CNT4.
  • the first counter CNT1 counts the number of times that both the first condition and the fourth condition are satisfied.
  • the AND gate A31 generates a logical product of the result signals result1 and result4.
  • the output signal of the AND gate A31 is input to the data terminal DT of the first counter CNT1.
  • the first counter CNT1 counts up when the output signal of the AND gate A31 is at a high level at the timing of the synchronization signal S13.
  • Satisfying the first condition and the fourth condition simultaneously means that the pulse width of the timing pulse Clock_out in the second state (actual operation state) is shorter than that in the first state (ideal state). . Therefore, the fluctuation of the pulse width can be detected by the first counter CNT1.
  • the second counter CNT2 counts the number of times that both the second condition and the third condition are satisfied. Accordingly, it can be detected that the pulse width of the timing pulse Clock_out in the second state (actual operation state) is longer than that in the first state (ideal state).
  • the third counter CNT3 counts the number of times that both the first condition and the second condition are satisfied. Thereby, it can be detected that the phase of the timing pulse Clock_out in the second state (actual operation state) is delayed from the first state (ideal state).
  • the fourth counter CNT4 counts the number of times both the third condition and the fourth condition are satisfied. Thereby, it can be detected that the phase of the timing pulse Clock_out in the second state (actual operation state) has advanced from the first state (ideal state).
  • the loop measurement circuit 40 measures the time difference between the leading edge and trailing edge of the input pulse, and measures the pulse width of the input pulse.
  • FIG. 7 is a circuit diagram showing a configuration example of the loop measurement circuit 40 of FIG.
  • the loop measurement circuit 40 includes selectors M1, M2, XOR gates XO1, XO2, OR gate O5, NOR gate NO1, flip-flop FF1, pulsar LP, TP, and counter.
  • the selector M1 receives the replica signal REPLICA and the target signal Target, and selects one according to the control signal S1.
  • the XOR gate XO1 generates an exclusive OR of the output signal of the selector M1 and the control signal conta1.
  • the output signal of the XOR gate XO1 is input to the clock terminal of the flip-flop FF1.
  • the selector M2 receives the output signal of the selector M1 and the output signal of the flip-flop FF1, and selects one according to the control signal S2.
  • the XOR gate XO2 generates an exclusive OR of the output signal of the selector M2 and the control signal conta2.
  • the leading edge pulser LP generates a pulse that becomes high level for a predetermined time from the leading edge of the loop start signal LoopStart.
  • the OR gate O5 generates a logical sum of the output signal of the leading edge pulser LP and the output signal of the XOR gate XO2.
  • the trailing edge pulser TP generates a pulse that becomes high level for a predetermined time from the trailing edge of the output signal of the OR gate O5.
  • the NOR gate NO1 generates a negative logical sum of the loop start signal and the output signal of the trailing edge pulser TP.
  • the output signal of the NOR gate NO1 is input to the reset terminal of the flip-flop FF1.
  • the counter 42 counts a period during which the output signal of the trailing edge pulser TP is at a high level with reference to the clock clock.
  • FIG. 8 is a flowchart showing an example of the operation of the pulse measuring apparatus 100 of FIG. 1.
  • Skew adjustment (S101) The system is set to the first state. In the replica signal generator 10, the control signal CTRLA is set to “1” and all the CTRLBs are set to “0”. In this state, the timing pulse Clock_out is output as it is as the replica signal REPLICA. Further, the control signal CTRLC for the condition determining unit 20 is set to “1”, and the control signals cont1 to cont4 are set to “0”. In this state, the delay amounts of the skew adjusting delay elements R1 to R4 are adjusted so that “1” is not output from the latches L1 to L4.
  • Reset measurement (S104)
  • the condition determination unit 20 sets the control signals CTRLB1 to CTRLB5 to the values obtained in step S102. Further, the control signals cont1 to cont4 are set to “1”. Further, the values of the latches L1 to L4 and Lr1 to Lr4 of the condition determining unit 20 are reset, and the count values of the counters CNT1 to CNT4 of the count processing unit 30 are initialized.
  • the pulse width of the signal SRi that has passed through the skew adjustment delay element Ri corresponding to the noticed result signal result is measured.
  • the signal SRi is selected by the selector M1 of the loop measurement circuit 40.
  • the delay amount of the skew adjusting delay element Ri can be calculated.
  • the difference between the delay amount of the skew adjustment delay element Ri set in step S106 and the delay amount of the skew adjustment delay element Ri set in step S101 is calculated. This difference is nothing but the variation amount of the pulse width, that is, it means that the pulse measuring apparatus 100 can observe the variation amount of the pulse width in the actual operation state.
  • the above is the operation of the pulse measuring apparatus 100.
  • the pulse measuring apparatus 100 according to the embodiment has the following advantages.
  • the pulse measuring apparatus 100 can directly evaluate the pulse (clock_out) during the actual test operation (second state). Conventionally, the pulse in the first state (reference state) is evaluated instead of the pulse in the actual test operation, and the state of the pulse in the actual test operation is estimated by analogy from the evaluation result. On the other hand, according to the pulse measuring apparatus 100, since the pulse of the actual test operation can be more accurately evaluated in real time, the timing accuracy of the test apparatus can be improved.
  • the pulse measuring apparatus 100 can measure the pulse to be evaluated without taking it out of the test apparatus. Therefore, pulse distortion caused by passing through an I / O buffer or a transmission path can be suppressed, and a pure pulse can be evaluated and measured.
  • the pulse measuring apparatus 100 can detect and detect the fluctuation of the pulse width and the fluctuation of the phase, and can measure the occurrence frequency of each. For example, when a pulse is measured using a measuring instrument such as an oscilloscope, a number of overlapping pulses are observed on the oscilloscope, so that it is not possible to distinguish between pulse width variation and phase variation.
  • FIG. 9 is a diagram illustrating a pulse measurement result using an oscilloscope. In contrast, in the embodiment, these can be distinguished and measured.
  • the pulse width variation amount and the phase variation amount can be estimated based on the difference in delay amount of the skew adjusting delay element.
  • the present invention is not limited to this.
  • a determination unit for detecting phase advance may be provided in a system in which only phase advance is predicted.
  • more determination units may be provided in a system in which only phase advance is predicted.
  • more determination units may be provided in a system in which only phase advance is predicted.
  • more determination units may be provided in a system in which only phase advance is predicted.
  • more determination units may be provided in a system in which only phase advance is predicted.
  • more determination units may be provided.
  • a plurality of determination units of the same type may be provided, and different delay amounts may be set for the respective delay elements D. In this case, it is possible to analyze the frequency and amount of fluctuation of phase fluctuations and pulse signal fluctuations at a time.
  • the pulse measuring apparatus 100 is mounted on a test apparatus.
  • the application of the present invention is not limited thereto, and the apparatus is also applicable to equipment for which the characteristics of a clock signal and a pulse signal should be evaluated with high accuracy. Is available.
  • Target signal generation unit R1 ... First skew adjustment delay Element, R2 ... Second skew adjusting delay element, R3 ... Third skew adjusting delay element, R4 ... Fourth skew -Adjustment delay element, 30 ... count processing unit, 32 ... first counter, 34 ... second counter, 36 ... third counter, 38 ... fourth counter, 40 ... loop measurement circuit, D1 ... first delay element, D2 2nd delay element D3 3rd delay element D4 4th delay element N1 1st negative gate N2 2nd negative gate N3 3rd negative gate N4 4th negative gate N5 5th negative gate, N6 ...
  • the present invention can be used for a test apparatus.

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Abstract

L'invention porte sur un générateur (10) de signaux répliques, recevant un signal d'impulsion et maintenant la largeur d'impulsion du signal d'impulsion dans un premier état, qui devient l'état de référence, en tant que largeur d'impulsion de référence. Le générateur (10) de signaux répliques génère le signal réplique (REPLICA), qui a la largeur d'impulsion de référence, et un bord d'attaque correspondant au bord d'attaque d'un signal d'impulsion cible de mesure (Target) dans un deuxième état correspondant à l'état d'exploitation effectif. Une unité (20) de décision d'état reçoit le signal d'impulsion (Target) et le signal réplique (REPLICA) et détermine si la relation entre phases, entre le bord de signal d'impulsion (Target) et le bord de signal réplique (REPLICA) dans le deuxième état satisfait aux conditions spécifiées. Un processeur de comptage (30) exécute le traitement de comptage afin d'obtenir le résultat de décision de l'unité (20) de décision d'état.
PCT/JP2009/002365 2009-05-28 2009-05-28 Dispositif de mesure d'impulsions, procédé de mesure d'impulsions et appareil d'essai utilisant le dispositif et le procédé WO2010137076A1 (fr)

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JP2010507737A JPWO2010137076A1 (ja) 2009-05-28 2009-05-28 パルス測定装置およびパルス測定方法ならびにそれらを用いた試験装置
PCT/JP2009/002365 WO2010137076A1 (fr) 2009-05-28 2009-05-28 Dispositif de mesure d'impulsions, procédé de mesure d'impulsions et appareil d'essai utilisant le dispositif et le procédé

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EP3842281A4 (fr) * 2019-01-14 2021-10-06 LG Chem, Ltd. Appareil de diagnostic

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JPS6196474A (ja) * 1984-10-17 1986-05-15 Matsushita Electric Ind Co Ltd パルス幅検査方法
JP2000214221A (ja) * 1999-01-20 2000-08-04 Sony Corp 半導体装置およびその試験方法
JP2003319015A (ja) * 2002-04-24 2003-11-07 Ando Electric Co Ltd 多機能測定システム及び波形測定方法
JP2003344493A (ja) * 2002-05-24 2003-12-03 Mitsubishi Electric Corp 半導体デバイス評価装置
JP2004125552A (ja) * 2002-10-01 2004-04-22 Advantest Corp ジッタ測定装置、及び試験装置

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JPH0611483Y2 (ja) * 1987-07-03 1994-03-23 横河電機株式会社 パルス信号間引き回路
JP2819127B2 (ja) * 1988-01-20 1998-10-30 東洋通信機株式会社 位相測定回路
JP3813130B2 (ja) * 2003-01-24 2006-08-23 富士通株式会社 半導体集積回路装置およびその制御方法
KR100907928B1 (ko) * 2007-06-13 2009-07-16 주식회사 하이닉스반도체 반도체 메모리 장치

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JPS6196474A (ja) * 1984-10-17 1986-05-15 Matsushita Electric Ind Co Ltd パルス幅検査方法
JP2000214221A (ja) * 1999-01-20 2000-08-04 Sony Corp 半導体装置およびその試験方法
JP2003319015A (ja) * 2002-04-24 2003-11-07 Ando Electric Co Ltd 多機能測定システム及び波形測定方法
JP2003344493A (ja) * 2002-05-24 2003-12-03 Mitsubishi Electric Corp 半導体デバイス評価装置
JP2004125552A (ja) * 2002-10-01 2004-04-22 Advantest Corp ジッタ測定装置、及び試験装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3842281A4 (fr) * 2019-01-14 2021-10-06 LG Chem, Ltd. Appareil de diagnostic
US11999245B2 (en) 2019-01-14 2024-06-04 Lg Energy Solution, Ltd. Diagnosis apparatus for diagnosing a communication state between a vehicle including a battery and a battery management system connected to a vehicle

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