WO2010131901A2 - Dispositif mémoire non volatile - Google Patents

Dispositif mémoire non volatile Download PDF

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Publication number
WO2010131901A2
WO2010131901A2 PCT/KR2010/003000 KR2010003000W WO2010131901A2 WO 2010131901 A2 WO2010131901 A2 WO 2010131901A2 KR 2010003000 W KR2010003000 W KR 2010003000W WO 2010131901 A2 WO2010131901 A2 WO 2010131901A2
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Prior art keywords
memory device
layer
nonvolatile memory
nanocrystal
organic
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PCT/KR2010/003000
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English (en)
Korean (ko)
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WO2010131901A3 (fr
Inventor
박재근
이곤섭
승현민
이종대
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한양대학교 산학협력단
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Publication of WO2010131901A3 publication Critical patent/WO2010131901A3/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0009—RRAM elements whose operation depends upon chemical change
    • G11C13/0014—RRAM elements whose operation depends upon chemical change comprising cells based on organic memory material
    • G11C13/0016—RRAM elements whose operation depends upon chemical change comprising cells based on organic memory material comprising polymers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5664—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using organic memory material storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0009—RRAM elements whose operation depends upon chemical change
    • G11C13/0014—RRAM elements whose operation depends upon chemical change comprising cells based on organic memory material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/50—Bistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
    • H10K19/202—Integrated devices comprising a common active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
    • H10K85/10—Organic polymers or oligomers
    • H10K85/111—Organic polymers or oligomers comprising aromatic, heteroaromatic, or aryl chains, e.g. polyaniline, polyphenylene or polyphenylene vinylene
    • H10K85/113—Heteroaromatic compounds comprising sulfur or selene, e.g. polythiophene
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic

Definitions

  • the present invention relates to a nonvolatile memory device, and to a nonvolatile memory device including an organic material layer having two conductive states at the same voltage.
  • D-RAM Dynamic-Ramdon Access Memory
  • nonvolatile flash memory volatile Dynamic-Ramdon Access Memory
  • the DRAM adjusts the channel width under the gate according to the voltage applied to the gate to form a channel between the source and drain terminals, and charges or discharges electrons in a capacitor connected to the source terminal. Afterwards, the device reads the charge and discharge states of the capacitor and separates the data of 0 and 1.
  • This DRAM has a disadvantage of continuously recharging the capacitor, which is called a volatile memory device, and when power is not applied, there is a problem in that power consumption is lost because data input to the device is lost due to leakage current. .
  • the NAND flash memory generates an F-N tunneling phenomenon due to a voltage applied to the control gate and the channel region, and charges or discharges electrons in the floating gate through the F-N tunneling phenomenon. It is a device that distinguishes data between 0 and 1 by changing the threshold voltage of the channel region according to the state of charge and discharge, and reading the change of the threshold voltage.
  • This flash memory uses FN tunneling, so the voltage used in the device becomes very large. Flash memory requires charging or discharging electrons to the floating gate through FN tunneling made of polysilicon. This results in a slow data processing rate of ⁇ -sec.
  • the memory cell size is rather large (8F 2 ) and at least several tens of steps or more, the integration degree of the device is difficult to be improved, and the unit cost is high and it is difficult to maintain high yield.
  • next-generation memory devices have been separated in various ways according to the materials constituting the cells which are basic units therein. That is, when the material is cooled after applying a current to the phase change material, the data becomes 0 or 1 using the difference of resistance depending on whether the material becomes a solid state with low resistance or a large amorphous state or when voltage is applied to the conductive organic material.
  • planar floating gates replace quantum dots of metal, silicon, or compound semiconductors in planar silicon.
  • the nonvolatile memory using organic materials (ie, organic materials) of the next-generation memory has not been applied to actual mass production, and it is difficult to find accurate process conditions for manufacturing the memory device.
  • organic materials ie, organic materials
  • the present invention provides a non-volatile memory device that can improve the reliability of the device by increasing the charge charging probability of the nanocrystal by manufacturing an organic material layer that can increase the charge transfer efficiency and charge transfer speed.
  • the nonvolatile memory device of the present invention comprises: first and second electrodes; An organic material layer positioned between the first and second electrodes; A nanocrystal layer is disposed between the organic material layers, and the organic material layer includes a donor material and an acceptor material.
  • the donor material or the acceptor material may be a high molecular organic material or a low molecular organic material, respectively.
  • the donor material is P3HT (poly (3-hexylthiophene)), polysiloxane carbazole, polyaniline, polyethylene oxide, (poly (1-methoxy-4- (0-dispersed1) -2,5-phenylene -Vinylene), polyindole, pearlicarbazole, polypyridazine, polyisothianaphthalene, polyphenylene sulfide, polyvinylpyridine, polythiophene, polyfluorene, polypyridine, polystyrene and derivatives thereof It is possible to include more than one.
  • the acceptor material may be fullerene or a derivative thereof.
  • the donor material is P3HT, and the acceptor material may be PCBM ([6,6] -phenyl-C61 butyric acid methyl ester).
  • the nano crystal layer preferably includes a nano crystal and a barrier material surrounding the nano crystal.
  • the nanocrystals may be at least one of Al, Ti, Zn, Fe, Ni, Sn, Pb, Cu, and alloys thereof.
  • the barrier material may be any one selected from oxides of the nanocrystal material, Al 2 O 3, TiO 2, and carbazole terminated thiol (CB).
  • various resistance states may be changed, and a multi-level output current may be generated during a read operation.
  • a plurality of laminates in which the organic layer and the nanocrystal layer are stacked are stacked, and an intermediate electrode is further formed between the stacks.
  • a memory device having a nanocrystal layer formed on an organic material layer including a donor material and an acceptor material may be manufactured to increase the charge charging probability of the nanocrystal, thereby improving reliability of the device.
  • the present invention can repeatedly perform read, write and erase operations through an organic material layer having bistable conductive properties, maintain data stored in a cell even when power is not applied, and manufacture a multilevel memory. .
  • FIG. 1 is a cross-sectional view of a nonvolatile memory device according to an embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of a nonvolatile memory device according to another embodiment of the present invention.
  • 3 to 8 illustrate a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention.
  • FIG. 9 is a conceptual cross-sectional view for explaining a method for manufacturing a nanocrystal layer according to an embodiment of the present invention.
  • FIG. 10 is a graph illustrating current voltage characteristics of a memory device according to an exemplary embodiment of the present invention.
  • 11 and 12 are graphs showing retention and endurance test results of a nonvolatile memory device according to an embodiment of the present invention.
  • FIG. 1 is a cross-sectional view of a nonvolatile memory device according to an embodiment of the present invention
  • FIG. 2 is a cross-sectional view of a nonvolatile memory device according to a modification of the embodiment.
  • a nonvolatile memory device may include a first and second bistable conduction characteristics between upper and lower electrodes 20 and 70 and upper and lower electrodes 20 and 70.
  • the nano organic layer 30 is disposed between the second organic layer 30 and 60 and the first and second organic layer 30 and 60.
  • the nano crystal layer 50 is formed as a single layer, the nano crystal layer 50 may be formed in a plurality of layers.
  • an insulating substrate, a semiconductor substrate, or a conductive substrate may be used, that is, a plastic substrate, a glass substrate, an Al 2 O 3 substrate, a SiC substrate, a ZnO substrate, a Si substrate, a GaAs substrate, or a GaP substrate. At least one of a LiAl 2 O 3 substrate, a BN substrate, an AlN substrate, an SOI substrate, and a GaN substrate may be used. When using a semiconductive substrate and a conductive substrate should be separated by an insulator between the lower electrode (20).
  • the upper and lower electrodes 20 and 70 may use any material having electrical conductivity.
  • the electrode is preferably metal such as Al, Ti, Zn, Fe, Ni, Sn, Pb, Cu, and alloys thereof having low electrical resistance and excellent interfacial properties with conductive organic materials.
  • the first and second organic material layers 30 and 60 may include a donor material and an acceptor material.
  • the donor material refers to a molecule that gives an electron
  • the acceptor material refers to a molecule that receives an electron.
  • the donor material or the acceptor material may be a high molecular material or a low molecular material, respectively. In this embodiment, a high molecular material is used as the donor material and a low molecular material is used as the acceptor material.
  • the donor material is P3HT (poly (3-hexylthiophene)), polysiloxane carbazole, polyaniline, polyethylene oxide, (poly (1-methoxy-4- (0-dispersed1) -2,5-phenyl Ethylene-vinylene), polyindole, pericarbazole, polypyridazine, polyisothianaphthalene, polyphenylene sulfide, polyvinylpyridine, polythiophene, polyfluorene, polypyridine, polystyrene and derivatives thereof Any one or more materials may be used.
  • fullerene or a derivative thereof is used as the acceptor material.
  • PCBM [6,6] -phenyl-C61 butyric acid methyl ester
  • PCBM [6,6] -phenyl-C61 butyric acid methyl ester
  • the organic material memory characteristics may be improved by using the organic material including the donor material and the acceptor material as the first and second organic material layers 30 and 60. This is because the first and second organic material layers 30 and 60 form a charge transfer complex by the donor material and the acceptor material.
  • the charge transfer complex changes to an excited state due to two or more intermolecular attraction, which stabilizes the states of the two molecules while generating charge transfer between them.
  • the organic layer has bistable characteristics, that is, two conductivity at the same voltage.
  • the organic material layer is formed by mixing the donor material and the acceptor material.
  • the organic material layer may be formed to include the donor material layer and the acceptor material layer.
  • the nanocrystal layer 50 includes a plurality of crystalline nanocrystals 50a and a barrier material 50b surrounding the nanocrystals 50a.
  • the nanocrystal layer 50 is formed by depositing a metal layer and plasma or thermal oxidation of the deposited metal layer to include a nanocrystal 50a including a metal layer material and a barrier material 50b including an oxide of a metal layer material. It can be formed to.
  • the oxidation process may be carried out to O 2 plasma oxidation process.
  • nanocrystals may be formed through oxidation of a metal in the deposition chamber.
  • the nanocrystal layer 50 was formed using Ni.
  • the crystalline material ie nano crystal
  • the barrier material is Ni x O y (eg, NiO). This is because the Ni nanocrystal layer is formed by oxidizing the surface of the Ni metal layer.
  • the thickness of the nanocrystal layer 50 is preferably 1 to 40nm.
  • a single nanocrystal layer 50 is shown.
  • the present invention is not limited thereto, and a multilayer nanocrystal layer may be formed.
  • the uniformity of the thickness of the surface oxidized nanocrystal layer 50 refers to the formation of a nanocrystal layer having a thickness in the range of about -30 to + 30% of the target nanocrystal layer thickness.
  • the nanocrystal layer 50 of the present embodiment is formed to have a uniform thickness of 1 to 40 nm or less between the first and second organic material layers 30 and 60 to have energy of the nanocrystals whose surface is oxidized between the organic materials.
  • the gap becomes large, which can improve the device's data retention.
  • the device may have various resistance states and output various levels of current according to voltages applied to the upper and lower electrodes 20 and 70. Therefore, one or more bits of data may be stored in the unit cell.
  • a basic laminated structure can also be formed in multiple times. That is, the lower electrode 20 is positioned on the substrate 10, the first organic layer 30 is positioned on the lower electrode 20, and the first nanocrystal layer 50 is disposed on the first organic layer 30.
  • the second organic material layer 60 is positioned on the first organic material layer 30 including the first nano crystal layer 50, and the intermediate electrode 80 is positioned on the second organic material layer 60.
  • the third organic material layer 90 is positioned on the 80, the second nanocrystal layer 100 is positioned on the third organic material layer 90, and the fourth organic material layer 110 is disposed on the second nanocrystal layer 100.
  • the upper electrode 120 is positioned on the fourth organic material layer 110.
  • FIG. 3 to 8 are diagrams for describing a method of manufacturing a nonvolatile memory device according to the present embodiment.
  • (a) is a plan view for explaining the manufacturing method of the nonvolatile memory device
  • (b) is a cross-sectional view taken along the line A-A of (a).
  • FIG. 9 is a conceptual cross-sectional view for explaining a method for manufacturing a nanocrystal layer according to the present embodiment.
  • the lower electrode 20 is formed on the substrate 10. That is, the lower electrodes 20 arranged in one direction are formed by using evaporation. At this time, a silicon substrate or a glass substrate may be used as the substrate 10.
  • the substrate 10 is loaded into a chamber (not shown) for metal deposition, and then a region where the lower electrode 20 is to be formed is formed by using a first shadow mask (not shown). Expose Subsequently, the exposed area of the substrate 10 by evaporating a metal material at a temperature of 1000 to 1500 degrees Celsius while maintaining a pressure of 10 -6 to 10 -3 Pa and maintaining a deposition rate of 2 to 7 Pa / s.
  • the lower electrode 20 of metal is formed in it.
  • Al is used as the lower electrode 20.
  • the present invention is not limited thereto, and may be manufactured using at least one of Al, Ti, Zn, Fe, Ni, Sn, Pb, Cu, or an alloy thereof.
  • the lower electrode 20 may have a thickness of about 50 nm to about 100 nm. A predetermined washing process may be performed before and after the lower electrode 20 deposition process.
  • the first organic material layer 30 is formed on the substrate 10 on which the lower electrode 20 is formed.
  • an organic raw material for manufacturing the first organic material layer 30 is manufactured.
  • the donor and acceptor materials described above are prepared for the manufacture of organic raw materials.
  • the donor material and the acceptor material are placed in an organic solvent and blended.
  • P3HT was used as a donor material and PCBM was used as an acceptor material.
  • the prepared organic material is coated on the substrate 10 on which the lower electrode 20 is formed to form the first organic material layer 30.
  • the first organic material layer 30 may be coated through various coating methods.
  • the first organic layer 30 is formed through spin coating, and may be annealed in a nitrogen atmosphere after spin coating.
  • the thickness of the first organic material layer 30 coated on the substrate 10 may be 10 to 100 nm.
  • the first organic material layer 30 may be formed on the substrate 10 by various methods in addition to the above-described coating method.
  • it may be formed on a substrate by a printing method such as printing or screen printing.
  • the metal layer 40 is deposited on the first organic material layer 30.
  • the substrate 10 on which the first organic layer 30 is formed is loaded into a chamber (not shown) for metal deposition.
  • the first organic material layer 30 on which the nanocrystal layer 40 is to be formed is exposed using a third shadow mask (not shown). Then, the first organic material layer exposed by evaporating the metal material at a temperature of 800 to 1500 degrees Celsius while maintaining a pressure of 10 -6 to 10 -3 Pa and maintaining a deposition rate of 0.1 to 7.0 Pa / s. 30 to 1 to 40nm to form a metal layer 40 of thickness.
  • the metal layer 40 is not formed in the form of nanocrystals because of the high deposition rate, and is formed of a metal thin film having a grain boundary as shown in FIG.
  • the substrate 10 on which the metal layer 40 is formed is loaded into a chamber for oxidation.
  • RF power of 50 to 300 W is applied to the chamber, an AC bias of 100 to 200 V is applied, and an oxidation process is performed by injecting O 2 gas at a pressure of 0.5 to 3.0 Pa.
  • the process time is preferably carried out for about 50 to 500 seconds.
  • the nanocrystal layer 50 including the nanocrystal 50a and the barrier material 50b surrounding the nanocrystal 50a is formed.
  • the barrier material 50b is formed of an oxide of metal. In one embodiment of the present invention to form a Ni nano crystal layer.
  • the O 2 plasma penetrates along the boundary of the metal layer 40 having the grain boundary and oxidizes along the boundary as shown in FIG. 9B.
  • Ni nanocrystals of size are formed.
  • the nanocrystal layer 50 may be formed in a thickness of 1 to 40 nm according to the thickness of the metal layer 40.
  • the thickness of the metal layer 40 may be formed to be thick, but when the metal layer 40 becomes too thick (50 nm or more), the O 2 plasma does not sufficiently penetrate into the grain boundary of the metal layer 40 so that the nanocrystal layer 50 may be formed. ) May not be effectively formed.
  • the nanocrystal layer 50 after the oxidation process is completed is formed by oxidizing a nanocrystal of a crystalline material of Ni nanocrystal and a nanocrystalline surface of Ni0 amorphous material.
  • the above-described deposition and oxidation processes of the metal layer 40 may be repeated a plurality of times to form a multilayer nanocrystal layer 50.
  • the nano crystal layer 50 may be manufactured through various processes in addition to the oxidation process using the above-described plasma.
  • a first barrier material layer, a metal layer, and a second barrier material layer are sequentially deposited on the first organic material layer 30. Then, the curing process is performed for 0.5 to 4 hours at a temperature of 150 to 300 degrees. This allows the first and second barrier material layers to enclose the nanocrystals of the metal in the metal layer. In this case, Al 2 O 3 or TiO 2 may be used as the barrier material. Through this, the nanocrystal layer 50 including the nanocrystal 50a and the barrier material 50b may be manufactured.
  • the nanocrystals surrounded by the barrier material may be prepared, and then dispersed in an organic material and spin coated to form a nanocrystal dispersed layer in the organic material layer.
  • the barrier material may be CB (carbazole terminated thiol).
  • the second organic material layer 60 is formed on the first organic material layer 30 on which the nanocrystal layer 50 is formed in the same manner as the first organic material layer 30.
  • the upper electrode 70 is formed on the substrate 10 including the second organic layer 60.
  • the upper electrode 70 may be formed in a direction crossing each other with the lower electrode 30.
  • the substrate 10 formed up to the second organic layer 60 is loaded into a chamber for metal deposition, and then a region where the upper electrode 70 is to be formed is exposed using a fourth shadow mask. Thereafter, the pressure inside the chamber is set to 10 ⁇ 6 to 10 ⁇ 3 Pa, and the second organic layer 60 exposed by evaporating the metal material at a temperature of 1000 to 1500 degrees Celsius while maintaining the deposition rate at 2 to 7 ⁇ s / s. ) And a metal electrode in the region of the substrate 10.
  • Al is preferably used as the upper electrode 70, and the thickness of the electrode may be 60 to 100 nm.
  • a separate metal wiring process may be performed to connect each of the upper electrode 70 and the lower electrode 30 to an external electrode.
  • the upper electrode 70 and the lower electrode 30 are electrically connected to separate pads.
  • driving means for applying various input power sources to these pads is connected. Accordingly, various input power sources may be applied to the electrodes to have various output current levels according to the resistance state of the device. Such device characteristics are described below.
  • the manufacturing method is not limited thereto and may be manufactured by various methods.
  • the electrode and the nano crystal layer may be formed through an E-beam deposition process, a sputtering process, a CVD process, an ALD process, and the like in addition to a thermal evaporation process.
  • the electrode may be formed on the entire structure, and then the shape may be manufactured through a patterning process. That is, after forming a conductive material on the substrate, the electrode may be formed by removing the conductive material in the region except the electrode through an etching process using a mask. The oxidation process may also be carried out using wet and dry oxidation methods.
  • FIG. 10 is a graph illustrating current voltage characteristics of a memory device according to an exemplary embodiment.
  • FIG. 10 is a graph illustrating voltage and current characteristics of a nonvolatile memory device having a Ni nanocrystal layer using an organic material in which P3HT and PCBM are mixed as an organic material layer.
  • the current gradually increases exponentially to a certain level of the voltage V th .
  • a voltage of a predetermined level or more that is, a threshold voltage or a threshold voltage V th
  • the current has a low resistance state I on in which the current rapidly rises.
  • NDR negative resistance
  • the nonvolatile memory device Continuously increasing the voltage has a low resistance state in which the current increases again from the constant voltage (V e ). That is, it can be seen that the nonvolatile memory device according to the present embodiment has various resistance states.
  • the maximum current voltage power supply (V p ) refers to the point where the current flow of the device is maximized.
  • the voltage may refer to a voltage at which the negative resistance occurs.
  • the memory device may implement a multi-level cell in a single memory cell by using the negative resistance state.
  • the current flow increases slightly at a predetermined voltage level. do. However, if the voltage across the organic layers 30 and 60 is greater than or equal to the threshold voltage V th , the current flows rapidly as the carrier is charged in the nanocrystals whose surface is oxidized. When the carrier is charged in the nanocrystal, the current flow is tens of times to tens of thousands of times as compared with the case where the carrier is not charged.
  • the carrier When the voltage across the organic layers 30 and 60 is a negative resistance region voltage, the carrier is partially discharged (or partially charged) in the nanocrystal, which is lower than when the carrier is fully charged and is not charged. It is possible to have a high current flow in an intermediate resistance state.
  • V e erasing voltage: V e
  • the carrier charged in the nanocrystal layer is discharged to change to an uncharged state.
  • the organic material layers 30 and 60 of this embodiment are made of an organic material in which a donor material and an acceptor material are mixed.
  • the movement of carriers in the organic layers 30 and 60 is caused by hopping and carrier transfer.
  • carrier mobility can be increased by increasing carrier mobility.
  • the current increases with respect to the voltage up to a certain level of voltage, and when the voltage (threshold voltage: V th ) above the predetermined level is applied, the current rapidly increases. . That is, when a voltage equal to or greater than the threshold voltage V th is applied, the negative resistance state NDR occurs, and then a current increases with respect to the voltage equal to or greater than the erase voltage V e . This is due to the symmetrical structure of the device, which has the same mechanism as in the case of the positive directional voltage described above.
  • 11 and 12 are graphs illustrating retention and endurance test results of a nonvolatile memory device according to example embodiments.
  • a nonvolatile memory device using an organic material layer in which P3HT and PCBM are mixed stores a single resistance state, and reads it several times, thereby stably maintaining each state for 10 5 cycles.
  • both the low resistance state Ion and the high resistance state Ioff remain stable.
  • the difference between the low resistance and high resistance states is also 0.39 ⁇ 10 2 .

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Abstract

La présente invention concerne un dispositif mémoire non volatile comprenant : une première et une seconde électrode; une couche organique disposée entre la première et la seconde électrode et comprenant une substance donneuse et une substance acceptrice; et une couche nanocristalline se composant d'au moins une couche disposée dans la couche organique. De cette manière, l'invention permet la réalisation d'un dispositif mémoire produit avec une couche cristalline formée dans la couche organique et comprenant une substance donneuse et une substance acceptrice, ce qui permet une augmentation de la probabilité de charge électrique des nanocristaux et une amélioration de la fiabilité du dispositif.
PCT/KR2010/003000 2009-05-15 2010-05-12 Dispositif mémoire non volatile WO2010131901A2 (fr)

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KR1020090042370A KR101433273B1 (ko) 2009-05-15 2009-05-15 비휘발성 메모리 소자 및 그 제조 방법

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Cited By (1)

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Publication number Priority date Publication date Assignee Title
WO2014017683A1 (fr) * 2012-07-27 2014-01-30 Iucf-Hyu Dispositif de mémoire non volatile

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KR101460165B1 (ko) * 2011-02-18 2014-11-11 한양대학교 산학협력단 비휘발성 메모리 소자
KR101485507B1 (ko) * 2014-09-25 2015-01-26 한양대학교 산학협력단 비휘발성 메모리 소자

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