WO2010122695A1 - Structure de substrat et dispositif semi-conducteur - Google Patents

Structure de substrat et dispositif semi-conducteur Download PDF

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Publication number
WO2010122695A1
WO2010122695A1 PCT/JP2010/000432 JP2010000432W WO2010122695A1 WO 2010122695 A1 WO2010122695 A1 WO 2010122695A1 JP 2010000432 W JP2010000432 W JP 2010000432W WO 2010122695 A1 WO2010122695 A1 WO 2010122695A1
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Prior art keywords
barrier metal
metal layer
under barrier
bump
electrode
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PCT/JP2010/000432
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English (en)
Japanese (ja)
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仲野純章
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パナソニック株式会社
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Definitions

  • the present disclosure relates to a substrate structure and a semiconductor device, and more particularly to a substrate structure and a semiconductor device including an under barrier metal for forming a bump.
  • bump electrodes are formed on a substrate such as CSP (Chip Size Package or Chip Scale Package) and flip chip.
  • the bump electrode generally includes a passivation film, an under barrier metal (UBM) layer to which the bump is bonded, a protective film for protecting the outermost surface of the substrate, and the like.
  • Typical methods for forming bumps on the under barrier metal layer include a printing method, a plating method, and a bump material mounting method.
  • improving the bonding strength between the bump and the under barrier metal layer is not possible for semiconductor devices. This is important for improving reliability.
  • As means for improving the bonding strength between the bump and the under barrier metal layer there are the following methods.
  • an under barrier metal layer is formed by sequentially laminating a first metal film and a second metal film on a bonding pad. Subsequently, a gold (Au) seed layer is selectively formed on the top and side surfaces of the second metal film. Next, after forming a solder pattern connected to the Au seed layer, heat treatment is performed to react the solder pattern with the Au seed layer. Thereby, the bump electrode in which the connection portion between the solder bump and the under barrier metal layer has an anchor shape can be formed (see, for example, Patent Document 1). Further, a method for improving the bonding strength of solder bumps by forming a groove on the upper surface of the under barrier metal layer is disclosed (for example, see Patent Document 2).
  • connection portion between the bump and the under barrier metal layer has an anchor shape does not directly improve the bonding strength at the interface between the solder bump and the under barrier metal layer. For this reason, peeling may occur at the interface between the solder bump and the under-barrier metal layer. In addition, it cannot be formed without complicated formation steps.
  • the bonding strength can be improved at the portion where the groove is formed, but the effect is in a very limited range.
  • This disclosure is intended to realize a substrate structure in which the bonding strength is improved over the entire interface between the bump and the under-barrier metal layer.
  • the exemplary substrate structure includes a semiconductor substrate, an electrode formed on the semiconductor substrate, and an under barrier metal layer formed on the electrode and having a plurality of minute recesses.
  • the under barrier metal layer has a plurality of minute recesses. For this reason, the surface area of an under barrier metal layer becomes large, and the contact area of an under barrier metal layer and a bump can be enlarged.
  • the propagation of fracture energy at the interface between the two is not linear, so that the energy at the time of fracture can be dissipated. Therefore, the bonding strength between the under barrier metal layer and the bump can be dramatically improved.
  • the exemplary substrate structure further includes a protective film layer formed on a semiconductor substrate and having an opening exposing the electrode, and an under barrier metal layer having a plurality of minute recesses is formed on the electrode and along the side surface of the opening. It may be formed.
  • the exemplary substrate structure further includes a protective film layer formed on a semiconductor substrate and having an opening exposing the electrode, and an under barrier metal layer having a plurality of minute recesses is formed on the electrode and along the side surface of the opening.
  • the diameter of the opening may be smaller at the upper end than at the lower end.
  • the exemplary substrate structure further includes a protective film layer formed on a semiconductor substrate and having an opening exposing the electrode, and an under barrier metal layer having a plurality of minute recesses is formed on the electrode and along the side surface of the opening.
  • the opening may have a recess on the side surface.
  • the plurality of minute recesses may be formed by chemical treatment. With such a configuration, minute concave portions are uniformly formed at all locations that become the bonding interface between the under barrier metal and the solder bump.
  • the minute recess may have a diameter of 0.05 ⁇ m or more and 7 ⁇ m or less. With such a configuration, a large number of minute recesses can be distributed, and the bonding interface surface area between the solder bump and the under barrier metal can be increased.
  • the minute recess may have an aspect ratio of less than 1.
  • the exemplary semiconductor device includes any of the exemplary substrate structures. For this reason, the semiconductor device which has a board structure with high joint strength of a solder bump and under barrier metal is realizable.
  • the substrate structure according to the present invention can realize a substrate structure and a semiconductor device in which the bonding strength is improved over the entire interface between the bump and the under barrier metal.
  • (A) And (b) shows the board
  • (a) is sectional drawing of the part in which the bump was formed,
  • (b) is joining of an under barrier metal layer and a bump It is sectional drawing which shows an interface. It is sectional drawing which shows the modification of the board
  • FIG. 1A and 1B show a substrate structure according to an embodiment, in which FIG. 1A shows a portion where a bump is formed, and FIG. 1B shows a bonding between an under barrier metal (UBM) layer and a bump.
  • the interface is shown enlarged.
  • the substrate structure of the present embodiment includes an electrode 14 formed on the bump forming surface side of the semiconductor substrate 15, and a passivation film 13 and a protective film layer that are sequentially formed on the bump forming surface and have openings that expose the electrodes 14. 11 and an under barrier metal layer 12 covering the electrode 14 and the side surface of the opening.
  • the under barrier metal layer 12 of the present embodiment has a plurality of minute recesses 12a on the surface.
  • Bumps 16 are formed on the under barrier metal layer 12, and the bumps 16 penetrate into the minute recesses 12 a of the under barrier metal layer 12. For this reason, the contact area between the under barrier metal layer 12 and the bump 16 is increased, and the bonding strength between the under barrier metal layer 12 and the bump 16 can be improved.
  • a semiconductor element is formed on the semiconductor substrate 15, and the electrode 14 is electrically connected to the semiconductor element.
  • the substrate structure of this embodiment may be formed as follows.
  • a passivation film 13 made of Si 3 N 4 or the like is formed on the bump forming surface of the semiconductor substrate 15 on which the electrode 14 made of aluminum or the like is formed on the bump forming surface side.
  • the passivation film 13 is selectively removed to form an opening exposing the electrode 14.
  • polyimide is uniformly applied on the bump formation surface using a spinner.
  • pre-baking 70 ° C. ⁇ 50 seconds, 90 ° C. ⁇ 50 seconds, 105 ° C. ⁇ 110 seconds
  • the pattern is exposed so as to have openings similar to those of the electrode 14.
  • pre-development baking 80 ° C.
  • the protective film layer 11 may be made of benzoxazole or a silicone-based resin material instead of polyimide.
  • the under barrier metal layer 12 having a thickness of about 1 ⁇ 10 ⁇ 3 mm to 7 ⁇ 10 ⁇ 3 mm is formed in the opening as follows, for example.
  • a nickel-aluminum alloy layer is formed by sputtering.
  • the thickness of the alloy layer may be about 5 ⁇ m.
  • only aluminum contained in the alloy layer is dissolved and removed using a sodium hydroxide solution.
  • the under-barrier metal layer 12 made of so-called Raney nickel having a small recess 12a and a large surface area is formed.
  • the formation of the under barrier metal layer 12 and the formation of the protective film layer 11 may be switched in order.
  • the method of forming minute recesses in the under-barrier metal layer 12 by chemical treatment is to form fine recesses uniformly on the entire surface of the under-barrier metal layer 12 regardless of the shape of the under-barrier metal layer 12. It has the advantage of being able to. For example, in a substrate structure in which a protective film layer having an opening that exposes an electrode is formed, if an under barrier metal layer is formed on the electrode and along the side surface of the opening, a chemical treatment may be used. Minute concave portions can be uniformly formed on the entire surface of the under barrier metal layer.
  • bumps 16 are formed on the under barrier metal layer 12.
  • the bump 16 may be formed by a method such as ball mounting, plating, or dispensing.
  • a method such as ball mounting, plating, or dispensing.
  • a printing mask made of a metal plate having an opening at a position corresponding to the under barrier metal layer 12 and having a thickness of about 0.02 mm to 0.04 mm is prepared.
  • a flux is printed on the surface of the under barrier metal layer 12 using a rubber or metal squeegee.
  • bump material is arranged on the under barrier metal layer 12 on which the flux is printed, using a mounting mask having an opening at a position corresponding to the under barrier metal layer 12.
  • the semiconductor substrate 15 on which the bump material is disposed is heat-treated, and the bump material is melted to join the bump material to the under barrier metal layer 12.
  • the flux printed on the under barrier metal layer 12 mainly has two functions of holding the bump material and removing the oxide film during remelting (reflow). For this reason, a rosin-based or water-soluble flux may be used, and a halogen-free rosin flux is particularly preferable.
  • the bump material is preferably a solder ball made of a solder material having a tin-silver-copper composition, but a material having another composition may be used.
  • the size of the bump material is preferably about 0.07 mm to 0.125 mm in diameter. When the bump material is not spherical, the average value of the width in the longitudinal direction and the width in the short direction may be set to about 0.07 mm to 0.125 mm.
  • the under barrier metal layer 12 of the present embodiment is a porous material having a plurality of minute recesses 12a on the surface, and has a very large surface area. As shown in FIG. 1B, since the bump material dissolved when the bump material is reflowed penetrates into the minute recesses 12a of the under barrier metal layer 12, the contact area between the bump material and the under barrier metal layer 12 is reduced. As a result, the bonding strength between the under barrier metal layer 12 and the bump material can be drastically improved.
  • the propagation of the fracture energy is not linear when the interface breakage occurs between the under barrier metal layer 12 and the bump material layer, and the energy propagates through a detoured path. This can be expected to dissipate energy. This also becomes a factor for improving the bonding strength between the under barrier metal layer 12 and the bump material.
  • a tin (Sn) -silver (Ag) solder bump having a diameter of about 105 ⁇ m and a height of about 85 ⁇ m is formed on the under barrier metal layer 12 having a minute recess 12a having a diameter of about 0.5 ⁇ m.
  • the failure mode was confirmed by a high-speed shear test. In this case, in all of the 10 tests, not the interfacial failure but internal solder failure occurred. From this result, it can be confirmed that by forming the minute recesses 12 a in the under barrier metal layer 12, a strong bonding interface is formed between the under barrier metal layer 12 and the bumps 16.
  • the fine recess 12a formed in the under barrier metal layer 12 preferably has a diameter of about 0.05 ⁇ m to 7 ⁇ m, and more preferably about 0.1 ⁇ m to 5 ⁇ m because the bump material easily enters. Further, if the depth of the minute recess 12a is excessively large, voids may be formed at the interface between the under barrier metal layer 12 and the bump 16, and therefore the aspect ratio is less than 1, that is, the depth of the minute recess 12a is reduced. It is preferable to make it smaller than the diameter. Further, it is preferable that the minute recess 12a is formed on the entire surface of the under barrier metal layer 12 because the bonding between the under barrier metal layer 12 and the bumps 16 is further strengthened.
  • etching may be used instead of chemical etching.
  • a nickel layer is formed on the electrode 14 using an electroplating method.
  • the surface of the nickel layer may be finely cut to form the minute recess 12a.
  • an under-barrier metal layer 12B whose cross-sectional structure is a reverse taper type may be formed.
  • the opening formed in the protective film layer 11 is such that the diameter of the upper end portion is smaller than the diameter of the lower end portion, and an under barrier having a minute recess on the electrode 14 and along the side surface of the opening.
  • a metal layer may be formed.
  • FIG. 3 if an opening having a recess on the side surface is formed in the protective film layer 11 and an under barrier metal layer having a minute recess is formed along the side surface of the opening, the side surface has a concave structure.
  • the under-barrier metal layer 12C thus formed can be formed.
  • the concave structure can have any shape, and may have various shapes such as a U shape, a U shape, and a V shape. Further, a plurality of concave structures may be formed instead of one. By adopting such a structure of the under barrier metal layer, the bonding strength between the under barrier metal layer and the bump can be further increased.
  • the substrate structure according to the present invention can improve the bonding strength in the entire interface between the bump and the under barrier metal layer, and is useful as a substrate structure, a semiconductor device, and the like provided with the under barrier metal layer for forming the bump.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention porte sur une structure de substrat qui est pourvue d'un substrat semi-conducteur (15), d'une électrode (14) formée sur la partie supérieure du substrat semi-conducteur (15) et d'une couche de métal sous-barrière (12) formée sur la partie supérieure de l'électrode (14). La couche de métal sous-barrière (12) présente une pluralité de concavités minuscules (12a).
PCT/JP2010/000432 2009-04-20 2010-01-26 Structure de substrat et dispositif semi-conducteur WO2010122695A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2009101652A JP2010251631A (ja) 2009-04-20 2009-04-20 基板構造及び半導体装置
JP2009-101652 2009-04-20

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WO2010122695A1 true WO2010122695A1 (fr) 2010-10-28

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014044985A (ja) * 2012-08-24 2014-03-13 Tdk Corp 端子構造、並びにこれを備える半導体素子及びモジュール基板

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5732880B2 (ja) * 2011-02-08 2015-06-10 株式会社デンソー 半導体装置及びその製造方法
JP2013229491A (ja) * 2012-04-26 2013-11-07 Kyocera Corp 電極構造、半導体素子、半導体装置、サーマルヘッドおよびサーマルプリンタ
JP6326723B2 (ja) 2012-08-24 2018-05-23 Tdk株式会社 端子構造及び半導体素子
WO2019111740A1 (fr) 2017-12-06 2019-06-13 株式会社村田製作所 Composant électronique

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005116885A (ja) * 2003-10-09 2005-04-28 Seiko Epson Corp 半導体装置及びその製造方法
WO2008078655A1 (fr) * 2006-12-25 2008-07-03 Rohm Co., Ltd. Dispositif semi-conducteur

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005116885A (ja) * 2003-10-09 2005-04-28 Seiko Epson Corp 半導体装置及びその製造方法
WO2008078655A1 (fr) * 2006-12-25 2008-07-03 Rohm Co., Ltd. Dispositif semi-conducteur

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014044985A (ja) * 2012-08-24 2014-03-13 Tdk Corp 端子構造、並びにこれを備える半導体素子及びモジュール基板

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