WO2010119570A1 - Dispositif à semi-conducteurs multicouche et procédé de fabrication de dispositif à semi-conducteurs multicouche - Google Patents

Dispositif à semi-conducteurs multicouche et procédé de fabrication de dispositif à semi-conducteurs multicouche Download PDF

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WO2010119570A1
WO2010119570A1 PCT/JP2009/057767 JP2009057767W WO2010119570A1 WO 2010119570 A1 WO2010119570 A1 WO 2010119570A1 JP 2009057767 W JP2009057767 W JP 2009057767W WO 2010119570 A1 WO2010119570 A1 WO 2010119570A1
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electrode
semiconductor device
electrical continuity
metal
electrodes
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PCT/JP2009/057767
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English (en)
Japanese (ja)
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一幸 朴澤
武田　健一
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株式会社日立製作所
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Priority to JP2011509163A priority Critical patent/JP5559773B2/ja
Priority to PCT/JP2009/057767 priority patent/WO2010119570A1/fr
Priority to TW099111268A priority patent/TWI416689B/zh
Publication of WO2010119570A1 publication Critical patent/WO2010119570A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
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    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector

Definitions

  • the present invention relates to a laminated semiconductor device obtained by laminating semiconductor devices each having an electrode having no electrical continuity in addition to a through electrode having a gap, and a method for manufacturing the laminated semiconductor device.
  • a first semiconductor chip (device) is connected to a multilayer substrate (printed wiring board) via bumps, and the first semiconductor chip is stacked via an interposer. There is also an example of connecting with.
  • the problem is that the thermal conductivity differs greatly between areas with and without through-electrodes. It becomes. Since the through electrode exists in the Si substrate in the region where the through electrode is present, the thermal conductivity on the front side and the back side of the semiconductor device is high. On the other hand, not only the electrode is not in direct contact with the Si substrate, but also the region without the through electrode has a clearly reduced thermal conductivity because the through electrode is not present in the Si substrate. This not only reduces the heat dissipation (cooling) effect of the heat generated from the stacked semiconductor device, but also causes a temperature difference depending on the location within the semiconductor device surface. It is also the cause that causes.
  • the penetrating electrodes are often not evenly arranged in the semiconductor device, although depending on the purpose and design contents.
  • the region without the through electrode is made of a material different from that of the through electrode, it hardly contributes to the connection of the semiconductor device.
  • An object of the present invention is to provide a highly reliable connection of a semiconductor device and a stacked semiconductor device that provides a high thermal conductivity even when through electrodes having electrical continuity are unevenly arranged at arbitrary positions in the semiconductor device, and
  • An object of the present invention is to provide a method for manufacturing a laminated semiconductor device.
  • the applicant of the present application uses, as a so-called dummy electrode, an electrode having no electrical continuity in addition to a through electrode having electrical continuity, and these electrodes are evenly arranged in the semiconductor device plane. If it is arranged in the semiconductor device, it is found that non-uniform stress is not applied in the surface of the semiconductor device, a highly reliable connection of the semiconductor device is obtained, and a laminated semiconductor device having high thermal conductivity is obtained, and the present invention is completed. It came to do.
  • the feature of the first invention resides in (1) a stacked semiconductor device in which a plurality of semiconductor devices each including a through electrode having electrical continuity and an electrode having no electrical continuity are stacked.
  • a metal pad or a metal bump may be formed on the electrode ends of both electrodes. From the device surface side, the metal pad or the metal bump is electrically connected to the through electrode having electrical conductivity through the extraction electrode and the wiring layer.
  • the through electrode having electrical continuity affects the circuit operation of the device region through the wiring layer. On the other hand, since the electrode without electrical continuity does not reach the wiring layer, it does not affect the circuit operation of the device.
  • the metal pad or metal bump is formed on either the device surface side or the semiconductor device back surface side, or (4) the metal pad or metal bump is formed on the device surface side or the semiconductor device back surface side. The case where it forms in both is considered.
  • the through electrode having electrical continuity and the electrode having no electrical continuity are uniformly arranged in the semiconductor device.
  • the electrically conductive through electrode and the electrically nonconductive electrode are uniformly arranged in a lattice pattern at least in a device region in the semiconductor device.
  • the through electrode having electrical continuity and the electrode having no electrical continuity are uniformly arranged in the semiconductor device.
  • the through electrode having electrical continuity and the electrode having no electrical continuity are uniformly arranged in a lattice shape at least in a device region in the semiconductor device.
  • the through electrode having electrical continuity and the electrode having no electrical continuity are uniformly arranged in the semiconductor device.
  • the through electrode having electrical continuity and the electrode having no electrical continuity are uniformly arranged in a lattice shape at least in a device region in the semiconductor device.
  • the through electrode having electrical conduction and the electrode having no electrical conduction are arranged uniformly in the semiconductor device.
  • the through electrode having electrical continuity and the electrode having no electrical continuity are uniformly arranged in a lattice shape at least in a device region in the semiconductor device.
  • the feature of the second invention is (13) (a) polishing the back surface of the substrate opposite to the device surface side of the semiconductor substrate; (b) a step of machining an electrode hole without electrical conduction from the back surface of the substrate; (c) a step of processing a through-electrode hole having electrical continuity from the back surface of the substrate (d) a step of depositing and processing a sidewall insulating film in both the electrode holes, and further embedding an electrode material to form an electrode; (e) a step of flattening both electrode ends to form a semiconductor device; (f) A method of manufacturing a laminated semiconductor device, including a step of laminating a plurality of semiconductor devices obtained in the steps (a) to (e).
  • the side wall insulating film is preferably processed to the electrode surface on the device side simultaneously with removal of the hole bottom insulating film of the insulating film deposited in the electrode.
  • a feature of the third invention is (16) (a) polishing the back surface of the substrate opposite to the device surface side of the semiconductor substrate; (i) a step of depositing a mask material on the back surface of the substrate; (j) creating and processing a mask for processing an electrode hole without electrical conduction; (k) creating and processing a mask for processing a through-electrode hole with electrical continuity; (d) depositing and processing a sidewall insulating film in both the electrode holes, further embedding an electrode material to form an electrode, (e) a step of flattening both electrode ends to form a semiconductor device; (f) A method of manufacturing a laminated semiconductor device, including a step of laminating a plurality of semiconductor devices obtained in the steps (a) to (e).
  • the method further includes at least one step selected from a step of forming a metal pad or a metal bump on the through electrode side on the semiconductor substrate.
  • the side wall insulating film is preferably processed to the electrode surface on the device side simultaneously with removal of the hole bottom insulating film of the insulating film deposited in the electrode.
  • the feature of the fourth invention is (19) (l) a step of forming an electrically conductive through electrode by embedding an electrode material on one surface of a semiconductor substrate; (m) a step of polishing the other surface of the semiconductor substrate to expose a conductive through electrode, (b ′) a step of machining an electrode hole without electrical conduction from a surface in the same direction as the exposed surface while protecting the exposed surface; (d ′) a step of forming an electrode by embedding an electrode material in the electrode hole without electrical conduction; (e) a step of flattening both electrode ends to form a semiconductor device; (f ′) A method of manufacturing a laminated semiconductor device, including a step of laminating a plurality of semiconductor devices obtained in the steps (l) to (e).
  • the method further includes at least one step selected from a step of forming a metal pad or a metal bump on the through electrode side on the semiconductor substrate.
  • a semiconductor device used when stacking semiconductor devices on which through electrodes are formed has a metal pad or metal bumps 8 and 9 that are convex on the device surface side and the back surface side of the semiconductor device. 2, those in which convex electrodes such as metal pads and metal bumps 8 and 9 are formed on either the device surface side or the semiconductor device rear surface side as shown in FIG. 2, as shown in FIG. In other words, it can be divided into those in which both convex metal pads and metal bumps 8 and 9 are formed on the device surface side and the semiconductor device back surface side.
  • a substrate 1 is usually a Si substrate, and a CMOS circuit, a memory element, etc. are formed in a device region 2 formed on the surface side, and a protective film 3 and a take-out electrode 4 are formed thereon. Is often formed.
  • a method of improving the flatness of the Si substrate while reducing the connection failure between the electrodes by forming a metal pad, a metal bump 10 or the like in the region 7 having no through electrode can be considered.
  • the metal pad or the metal bump 10 formed in the region 7 having no through electrode is in close contact.
  • problems such as poor performance, and the height of the metal pads and metal bumps 8 and 9 formed at the end of the extraction electrode 4 and the end of the through electrode 5 having electrical continuity.
  • the metal pads and metal bumps 10 formed in the region 7 without the through electrode are not in direct contact with the Si substrate 1, so that the thermal conductivity is higher than that of the region 6 with the through electrode. I know it ’s bad.
  • the present invention has been made in view of such problems, and as shown in the uniform arrangement diagram of the electrodes in the surface of the semiconductor device in FIG. It is an object of the present invention to provide a method of increasing the thermal conductivity while suppressing the height deviation due to the metal pads and the metal bumps by arranging 12 uniformly on the semiconductor device 13 (for example, in a lattice shape).
  • a highly reliable semiconductor device connection and a laminated semiconductor device that provides high thermal conductivity even when through electrodes having electrical continuity are unevenly arranged at arbitrary positions in the semiconductor device, and A method for manufacturing a stacked semiconductor device can be provided.
  • FIG. 6 is a stacked view of a semiconductor device having no metal pads or metal bumps on the device surface side and the semiconductor device back surface side.
  • FIG. 6 is a stacked view of a semiconductor device having metal pads or metal bumps on either the device surface side or the semiconductor device back surface side.
  • FIG. 6 is a stacked view of a semiconductor device having metal pads or metal bumps on both the device side and the back side of the semiconductor device.
  • FIG. 6 is a stacked view of a semiconductor device in which metal pads or metal bumps are formed in a region without through electrodes. The uniform arrangement figure of the electrode in a semiconductor device surface.
  • Example of electrode formation by via First Example of electrode formation without electrical continuity by via ⁇ ⁇ ⁇ First.
  • the diameter and shape of the through-electrodes used in the present invention there are no particular restrictions on the diameter and shape of the through-electrodes used in the present invention, but when the electrodes are cylindrical, the diameter (or length) is in the range of 0.3 to 200 ⁇ m, and the distance is the electrode diameter. Is preferably about 5 to 1/5 (for example, if the electrode diameter is 10 ⁇ m, the interval is in the range of 50 ⁇ m to 2 ⁇ m).
  • the electrode diameter is smaller than 0.3 ⁇ m, the electrostatic capacity of the electrode increases and the resistance increases at the same time, so the advantage of using a dummy electrode is reduced.
  • the electrode diameter is larger than 200 ⁇ m, the ratio of the electrode area in the semiconductor device becomes too large, and the area where the semiconductor element can be arranged decreases, so the merit of using the dummy electrode is reduced. End up.
  • the diameter of the electrode without electrical continuity or the distance between the electrodes is not particularly limited, but may be considered to be the same as that of the through electrode with electrical continuity.
  • a metal bump or the like is formed at the electrode end, it is desirable that the through electrode having electrical continuity and the electrode having no electrical continuity have the same shape. This is because the bump height changes when the bump shape is different when forming a metal bump or the like, and this is not the case when the bump height is readjusted by another method.
  • the depth of the electrode is not determined with priority on the shape, but is determined from the viewpoint of circuit design, the final number of stacked layers and the limit value of the thickness thereof, the technical limit on the process, and the like.
  • the electrode depth increases, that is, as the wafer thickness or chip thickness increases, it becomes more difficult to form a hole with a small diameter (high aspect ratio).
  • the resistance value increases and the capacitance also increases, so the advantage of using a dummy electrode tends to decrease.
  • the depth of an electrode used as a signal line is desirably 100 ⁇ m or less, and ideally a range of 5 to 50 ⁇ m is desirable.
  • the through electrode with electrical continuity needs to penetrate the substrate and contact the internal electrode on the device surface side (or the extraction electrode at the top of the device region), but the electrode without electrical continuity does not penetrate the substrate. It is important to stop before that. If an electrode without electrical conduction is stopped too far in front of the device region, there is a disadvantage in terms of thermal conductivity because the electrode is not present in the substrate. On the contrary, if it is penetrated, the circuit on the device surface side is adversely affected. For this reason, it is desirable that the depth (length) of the electrode without electrical conduction be slightly shallower (or shorter) than the depth (length) of the through electrode with electrical conduction. Ideally, it should be at least 1 ⁇ m away from the device area.
  • the through electrode with electrical continuity is several ⁇ m from the device region, Ideally, it should be placed in a place separated by 1 ⁇ m or more.
  • an electrode forming method will be described.
  • the method of forming an electrode is roughly classified into via-First and via-Last.
  • via-First forms a through-electrode hole 15 having electrical continuity before a semiconductor device is completed, here, before the device region 2 is manufactured. Suitable for forming.
  • a sidewall insulating film 16 in the through electrode is deposited in the through electrode hole 15, and then a buried electrode 17 is formed. Finally, the end of the buried electrode 17 is flattened, so that each of the electrically independent electrodes A conductive through electrode 5 is formed.
  • the through electrode hole 15 is formed after the device region 2 is manufactured. In this case, since the subsequent process heat treatment temperature can be kept low, a metal such as Cu is often used.
  • the device region 2, the wiring layer 14, and the extraction electrode 4 are formed to complete the semiconductor device. Then, after forming the device surface side metal pad or metal bump 8 on the extraction electrode 4, the substrate is thinned by substrate polishing to expose the end of the through electrode to obtain the through electrode exposed surface 18. The back surface side of the semiconductor device is protected by the protection film 3 so as not to block the exposed surface 18 of the through electrode, and finally metal pads or metal bumps 9 on the back surface side of the semiconductor device are formed.
  • the substrate is thinned and the through electrode 5 having electrical conduction is exposed from the back surface of the substrate as shown in FIG. It is necessary to form (penetrating electrode exposed surface 18) and electrode 19 having no electrical continuity.
  • the processing of the electrode hole 19 without electrical conduction, the deposition of the sidewall insulating film 16 in the electrode hole 19 and the formation of the embedded electrode 17, and 17 ends are flattened to form an electrode 20 having no electrical continuity.
  • the end of the electrically conductive through electrode 5 is opened by the photolithography process and the dry etching process, and the electrodes are formed at the ends of the electrodes 5 and 20, and then the electrically conductive through electrode 5 is not electrically connected.
  • a planarization process for adjusting the height of the end of the electrode 20 is performed.
  • metal pads or metal bumps 9 are formed on both electrode ends, there are many problems such as not only a long process time but also a high process cost.
  • via-Last forms a through electrode from the back surface of the substrate opposite to the device surface side after the substrate is thinned after completion of the semiconductor device.
  • the heat treatment temperature generally because it is affixed to a hard support substrate or the like by some method such as resin or adhesive.
  • FIG. 8 shows a method of forming the through electrode 5 having electrical conduction and the electrode 20 having no electrical conduction almost simultaneously.
  • metal pads or metal bumps 8 are formed on the device surface side of the completed semiconductor device, and then the substrate is thinned by polishing.
  • the photolithographic process for the electrode without electrical conduction and the processing of the electrode hole 19 are performed, and then the photolithographic process for the through electrode with electrical conduction and the processing of the through electrode hole 15 are performed. Perform (through the substrate to the device side).
  • the sidewall insulating film 16 is simultaneously deposited in both electrode holes of the electrically conductive through electrode hole 15 and the electrically nonconductive electrode hole 19, and then the hole bottom insulating film of the electrically conductive through electrode hole 15 is formed. Remove all. At this time, if there is an element isolation insulating film or an interlayer insulating film at the bottom of the through-electrode hole 15 having electrical conduction, these are also removed together. After all the hole bottom insulating film is removed, the buried electrode 17 is formed and finally the electrode end is flattened.
  • the through electrode 5 having electrical continuity is the same as the height of the end of the electrode 20 having no electrical continuity.
  • a CVD oxide film 21 is deposited as a hard mask.
  • lithography for electrodes having no electrical continuity on the surface of the CVD oxide film 21 and hard mask processing for the electrodes are performed. At this time, the CVD oxide film is not processed, leaving an appropriate thickness and never exposing the Si surface.
  • lithography for through electrodes having electrical continuity is performed on the CVD oxide film 21, and hard mask processing for the through electrodes is performed. At this time, the CVD oxide film 21 is completely removed to expose the Si surface.
  • metal bumps 8 are formed on the device side of the completed semiconductor device.
  • the layout of the metal bumps 8 is the same layout as the back side of the semiconductor device opposite to the device side, and is laid out so as to overlap at the same position when stacked.
  • the substrate is thinned while the device surface on which the metal bumps 8 are formed is protected with a tape or the like.
  • lithography for the electrode 20 having no electrical continuity and processing of the electrode hole 19 are performed on the back surface of the thinned substrate, followed by lithography for the through electrode 5 having electrical continuity and its
  • the through electrode hole 15 is processed (through the substrate to the device side).
  • a sidewall insulating film 16 is deposited with a CVD oxide film in the through-hole 15 having electrical continuity and the electrode hole 19 having no electrical continuity, and the CVD oxide film, element isolation insulating film, interlayer insulating film, etc. existing at the bottom of the hole are dry-etched. To remove all the electrodes and expose the electrodes inside the device.
  • a seed layer (Ta / Cu) was deposited on the inner walls of both electrodes by a sputtering apparatus, and then the entire electrode was embedded by Cu plating as the embedded electrode 17, and finally the ends of both electrodes were flattened by CMP. .
  • a lithography process for forming metal bumps 9 at the ends of both electrodes is performed, and after seed metal is deposited by sputtering, metal plating for the metal bumps 9 is performed. After the metal bumps after plating were planarized by CMP, the resist was removed to form metal bumps 9 on the back side of the semiconductor device. Thereby, a laminated semiconductor device was obtained.
  • the bumps are connected to the extent of temporary fixing.
  • the stacked semiconductors are connected to each other by pressing with a pressure stronger than the temporary connection as the main connection.
  • the obtained laminated semiconductor device was cut by a dicing process to obtain a laminated semiconductor chip.
  • An underfill agent was filled from the side surface of the laminated semiconductor chip, and finally the underfill agent was cured by heat to complete a laminated semiconductor device.
  • the seed metal is deposited by sputtering, and after applying the resist, only the Al electrode region is opened by a photolithography process, and then the metal is grown in the opening by plating.
  • the metal plating material Au, Cu, Ni or the like is generally preferable, but solder material Sn may be used. Further, the metal plating material is not one kind, and a plurality of metal plating materials may be stacked. Thereafter, in order to align the metal bump height, the upper end of the metal bump is flattened. After planarization, the resist was removed, and the seed metal was removed by wet etching to form metal bumps only on the Al metal.
  • the wafer thickness is reduced to 30 ⁇ m with the bump surface protected with a protective tape.
  • the wafer is thinned using a general back grinding apparatus, and the polished surface is subjected to stress relief processing.
  • a method for forming electrodes from the back surface of the semiconductor device Since the thinned semiconductor device cannot hold its own weight, it is attached to the support substrate.
  • a hard mask is formed using an oxide film in order to form a hole for an electrode without electrical conduction on the back surface of the substrate. This hard mask not only prevents conduction between the electrode and the Si substrate and the electrodes, but also serves as a protective film on the back surface.
  • hard mask processing for electrode holes without electrical conduction is performed by dry etching. At this time, the hard mask is not completely removed, but the processing is stopped halfway.
  • the film thickness of the oxide film that remains without being processed is determined by the selection ratio between Si and the oxide film. In this case, the depth of the electrode hole without electrical continuity is adjusted so that it finally becomes 27 to 29 ⁇ m.
  • the hard mask for through electrodes with electrical continuity is processed again in the photolithography process. In this case, all the hard masks in the through electrode regions having electrical continuity are removed and exposed to the Si substrate. Up to this point, two types of hard mask patterns for through electrodes having electrical conduction and hard mask patterns having no electrical conduction can be formed on the same surface.
  • a through electrode hole with electrical continuity is processed by dry etching. At this time, the Si substrate is completely penetrated, but the thickness is set such that the oxide film for the hard mask remains. At this time, the electrode without electrical continuity is processed so that the depth of the electrode hole is shallow by the remaining oxide film thickness that has not been completely processed by the hard mask.
  • a low-temperature CVD oxide film is deposited to form an insulating film on the side surface in the electrode.
  • the insulating film at the bottom of the hole in the electrode is removed by dry etching, the element isolation insulating film in the device region at the bottom of the hole and the interlayer insulating film up to the metal wiring connected to the electrode must be removed together.
  • the insulating film at the bottom of the hole is removed until the metal electrode (wiring layer) on the receiving side formed on the device side is reached. The receiving metal electrode is electrically connected to the circuit.
  • a barrier film and seed Cu are formed by sputtering. After that, if the electrode is filled with Cu by plating and excess Cu is removed by CMP, a through electrode having electrical continuity and an electrode having no electrical continuity are formed simultaneously.
  • a method for forming metal bumps on the electrode ends on the back surface will be described. It is created by the same method as that formed on the device side.
  • a metal to be a seed is formed by sputtering, and after applying a resist, only the electrode region is opened by a photolithography process, and then the metal is grown in the opening by plating. After removing the resist, the seed metal was removed by wet etching, and metal bumps were formed only at the electrode ends.
  • the electrode chip 22 with double-sided bumps was obtained by removing the laminated semiconductor device having bumps formed on both the device surface side and the back side of the semiconductor device from the support substrate and separating each chip by dicing.
  • the chip at the bottom of the stacked layer is an interface chip 23 manufactured exclusively for the interface, unlike the semiconductor device described above.
  • the purpose of the interface chip 23 is to electrically connect or rewiring the stacked double-sided bumped electrode chip 22 and the mounting substrate 25.
  • the thickness of the interface chip 23 is as thick as 200 ⁇ m. This is because the electrode chip 22 with the double-sided bumps is very thin as 30 ⁇ m, and if only the thin chip is stacked, the possibility of the chip being bent or damaged at the time of stacking the chips increases, so that the reliability is high. Lamination is not possible. In order to prevent such a problem, only the bottom interface chip 23 is thickened so that the chip does not warp.
  • the stacked semiconductor device obtained from this is expressed as A.
  • the device operation was repeated by using a certain number of the obtained stacked semiconductor devices A and changing the temperature cycle from -25 ° C. to 125 ° C., and a bump connection reliability test at this temperature cycle was performed.
  • Table 1 shows the relative results with respect to Comparative Examples 1 and 2 and 3 below when the result of the bump connection reliability test is 100%.
  • FIG. 2 An example of a laminated semiconductor device in which through electrodes are formed in via-first will be described.
  • a hole for the through electrode having electrical continuity is opened from above the interlayer film, and a CVD oxide film is formed on the inner wall of the through electrode hole.
  • a sidewall insulating film is deposited.
  • the penetration electrode depth at this time is 31 ⁇ m.
  • a seed layer (Ta / Cu) is formed by sputtering, Cu is embedded in the through-electrode hole by Cu plating, and then excess Cu is removed and planarized by CMP to electrically isolate the through-electrodes. I let you. Thereafter, a metal wiring layer is formed. At this time, since the through electrode and the wiring layer are electrically connected, the through electrode becomes a through electrode having electrical conduction.
  • an Al electrode was formed as an extraction electrode on the uppermost part on the device side.
  • the Al electrodes are uniformly arranged in the semiconductor device surface, and their heights are all the same. According to the circuit design, both an Al electrode having electrical continuity with the internal circuit and an Al electrode having no electrical continuity are formed in advance.
  • a metal to be a seed is deposited by sputtering, and after applying a resist, only the Al electrode region is opened by a photolithography process, and then metal is grown in the opening by plating. Thereafter, in order to align the metal bump height, the upper end of the metal bump is flattened. After planarization, the resist was removed, and the seed metal was removed by wet etching to form metal bumps only on the Al metal.
  • the semiconductor device Since bumps are formed on the device surface side, the semiconductor device is thinned to an average thickness of 32 ⁇ m with the bump surface protected by a protective tape.
  • the semiconductor device is thinned by using a general back grinding apparatus, and the polished surface is subjected to stress relief processing. At this stage, the end of the through electrode is not exposed (18 in FIG. 7 (1)).
  • a method for forming an electrode without electrical conduction from the back surface of the semiconductor device will be described. Since the thinned semiconductor device cannot hold its own weight, it is attached to the support substrate.
  • a hard mask is formed using an oxide film in order to form a hole for an electrode having no electrical continuity on the back surface of the semiconductor device.
  • a CVD oxide film that can be formed at a low temperature of 200 ° C. or lower was used.
  • hard mask processing for electrode holes without electrical conduction is performed by dry etching. After depositing a sidewall insulating film inside the electrode hole without electrical conduction, a seed layer (Ta / Cu) was formed by sputtering. After that, electrode holes without electrical continuity were filled with Cu plating, and excess Cu was removed by CMP to flatten it.
  • the back surface of the semiconductor device was thinned together with the exposed electrode without electrical continuity. With this thinning, the average thickness of the substrate became 30 ⁇ m.
  • a CVD oxide film was formed as a protective film on the back surface of the semiconductor device, and a photolithography process and dry etching were performed to open both the through-electrode end having electrical continuity and the electrode end having no electrical continuity.
  • a seed layer (Ta / Cu) was formed by sputtering, and Cu was grown on both electrode ends by Cu plating. Then, excess Cu was removed by CMP and planarized.
  • a method for forming metal bumps on the electrode ends on the back surface will be described. It is created by the same method as that formed on the device side.
  • a metal to be a seed is formed by sputtering, and after applying a resist, only the region of the through electrode is opened by a photolithography process, and then the metal is grown in the opening by plating. After removing the resist, the seed metal was removed by wet etching, metal bumps were formed only at the end of the through electrode, and a laminated semiconductor device having bumps formed on both the device surface side and the semiconductor device back surface side was obtained.
  • the laminated semiconductor device 22 having bumps formed on both the device surface side and the back surface side of the semiconductor device was removed from the support substrate and separated into each chip by dicing to obtain an electrode chip 22 with double-sided bumps (FIG. 11). ).
  • the method of laminating the electrode chip 22 with double-sided bumps separated into chips is as described above.
  • the multilayer semiconductor device obtained from this is expressed as E.
  • the temperature cycle was changed from -25 ° C. to 125 ° C. and the device operation was repeated, and a bump connection reliability test at this temperature cycle was performed.
  • Table 2 shows the relative results for the following Comparative Examples 4, 5 and 6 when the result of the bump connection reliability test is 100%.
  • the metal pads and metal bumps formed at the electrode ends have the same height and are in-plane. Since it exists uniformly, non-uniform stress is unlikely to occur due to the pressure applied at the time of connection, and connection failure can be reduced. Further, since the electrodes are uniformly distributed, the thermal conductivity of the substrate is high, and the heat generated from the laminated semiconductor device can be efficiently dissipated (cooled).
  • the stacked semiconductor device obtained using the semiconductor device exhibits high reliability.

Abstract

Selon l'invention, par stratification d'une pluralité de dispositifs à semi-conducteurs comprenant chacun une électrode conductrice par conduction traversante et une électrode non conductrice, une connexion hautement fiable de dispositifs à semi-conducteurs peut être obtenue, même lorsque les électrodes conductrices par conduction traversante sont agencées non uniformément dans des positions arbitraires des dispositifs à semi-conducteurs. L'invention porte également sur un dispositif à semi-conducteurs multicouche présentant une conductivité thermique élevée et sur un procédé de fabrication d'un dispositif à semi-conducteurs multicouche.
PCT/JP2009/057767 2009-04-17 2009-04-17 Dispositif à semi-conducteurs multicouche et procédé de fabrication de dispositif à semi-conducteurs multicouche WO2010119570A1 (fr)

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PCT/JP2009/057767 WO2010119570A1 (fr) 2009-04-17 2009-04-17 Dispositif à semi-conducteurs multicouche et procédé de fabrication de dispositif à semi-conducteurs multicouche
TW099111268A TWI416689B (zh) 2009-04-17 2010-04-12 And a method for manufacturing a laminated semiconductor device and a multilayer semiconductor device

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Cited By (2)

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JP5561811B1 (ja) * 2013-09-02 2014-07-30 国立大学法人東北大学 エッチング方法及びｌｓｉデバイスの製造方法、並びに３ｄ集積化ｌｓｉデバイス製造方法
JP2017041558A (ja) * 2015-08-20 2017-02-23 大日本印刷株式会社 貫通電極基板及びその製造方法

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Publication number Priority date Publication date Assignee Title
JP2004152811A (ja) * 2002-10-28 2004-05-27 Sharp Corp 積層型半導体装置及びその製造方法
JP2006253587A (ja) * 2005-03-14 2006-09-21 Toshiba Corp 半導体装置及びその組立方法
JP2007250561A (ja) * 2004-04-12 2007-09-27 Japan Science & Technology Agency 半導体素子および半導体システム

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JP2004152811A (ja) * 2002-10-28 2004-05-27 Sharp Corp 積層型半導体装置及びその製造方法
JP2007250561A (ja) * 2004-04-12 2007-09-27 Japan Science & Technology Agency 半導体素子および半導体システム
JP2006253587A (ja) * 2005-03-14 2006-09-21 Toshiba Corp 半導体装置及びその組立方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5561811B1 (ja) * 2013-09-02 2014-07-30 国立大学法人東北大学 エッチング方法及びｌｓｉデバイスの製造方法、並びに３ｄ集積化ｌｓｉデバイス製造方法
WO2015029092A1 (fr) * 2013-09-02 2015-03-05 国立大学法人東北大学 Procédé de gravure, procédé de fabrication de dispositif lsi, et procédé de fabrication de dispositif lsi intégré 3d
JP2017041558A (ja) * 2015-08-20 2017-02-23 大日本印刷株式会社 貫通電極基板及びその製造方法

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