WO2010116587A1 - Dispositif semi-conducteur et son procédé de production - Google Patents

Dispositif semi-conducteur et son procédé de production Download PDF

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Publication number
WO2010116587A1
WO2010116587A1 PCT/JP2010/000754 JP2010000754W WO2010116587A1 WO 2010116587 A1 WO2010116587 A1 WO 2010116587A1 JP 2010000754 W JP2010000754 W JP 2010000754W WO 2010116587 A1 WO2010116587 A1 WO 2010116587A1
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film
metal
metal film
semiconductor device
forming
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PCT/JP2010/000754
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English (en)
Japanese (ja)
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佐藤好弘
藤本裕雅
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パナソニック株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo

Definitions

  • the present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, a semiconductor device including a MISFET (MetalsInsulator Semiconductor Field Effect Transistor) having a gate electrode including a metal film on a semiconductor substrate having a (110) plane as a main surface, and the semiconductor device It relates to a manufacturing method.
  • MISFET MetalInsulator Semiconductor Field Effect Transistor
  • alumina Al 2 O 3
  • hafnia HfO 2
  • hafnium silicate HfSiO
  • a gate insulating film made of a high dielectric material represented by x ) has been put into practical use.
  • a full metal gate electrode made of a metal film, or MIPS (Metal-inserted Poly-silicon) in which a metal film is inserted between the polysilicon film and the gate insulating film. The use of a gate electrode with a Stack structure is underway.
  • p-type MIS transistor As a technique for improving the performance of a p-type MISFET (hereinafter referred to as “p-type MIS transistor”), for example, a technique for providing a SiGe layer in a p-type source / drain region has been proposed. Thereby, compressive stress is applied in the gate length direction of the channel region, and the performance of the p-type MIS transistor is improved.
  • a semiconductor substrate having a (110) plane as a main surface (hereinafter referred to as “(100) plane substrate”)
  • a semiconductor substrate having a (110) plane as a main surface (hereinafter referred to as “A technique of providing a p-type MIS transistor on a (110) plane substrate has been proposed (refer to Non-Patent Documents 1 to 3, for example). This increases the hole mobility and improves the performance of the p-type MIS transistor.
  • an object of the present invention is to further improve the performance of a p-type MIS transistor in a semiconductor device including a p-type MIS transistor formed on a semiconductor substrate having a (110) plane as a main surface.
  • FIG. 1A is a graph showing the relationship between effective electric field and hole mobility in a p-type MIS transistor formed on a (100) plane substrate.
  • the solid line shown in FIG. 1A represents the case where the thickness of the metal film of the gate electrode is 5 nm, and the solid line represents the case where the thickness of the metal film of the gate electrode is 15 nm.
  • FIG. 1B is a graph showing the relationship between effective electric field and hole mobility in a p-type MIS transistor formed on a (110) plane substrate.
  • the solid line indicates the case where the thickness of the metal film of the gate electrode is 5 nm
  • the ⁇ line indicates the case where the thickness of the metal film of the gate electrode is 15 nm.
  • FIGS. 1A and 1B are universal lines when a silicon oxide film is used as the gate insulating film in the p-type MIS transistor formed on the (100) plane substrate.
  • the p-type MIS transistor includes a gate insulating film and a gate electrode having a MIPS structure (that is, a gate electrode made of a metal film formed on the gate insulating film and a silicon film formed on the metal film).
  • the gate insulating film is made of a high dielectric constant film containing hafnium (Hf).
  • the metal film of the gate electrode is a titanium nitride (TiN) film having a thickness of 5 nm (or a thickness of 15 nm).
  • the silicon film of the gate electrode is made of a polysilicon film having a thickness of 100 nm.
  • the configuration of the p-type MIS transistor of the universal line is as follows.
  • the p-type MIS transistor includes a gate insulating film and a gate electrode.
  • the gate insulating film is made of a SiO 2 film.
  • the gate electrode is made of a polysilicon film having a thickness of 100 nm.
  • the effective electric field is positive in the actual use region, that is, in the range of the electric field actually generated in the transistor operation.
  • the hole mobility (see the ⁇ line) is higher than the hole mobility (see the ⁇ line) when the thickness of the metal film is large.
  • the effective electric field is positive in the actual use region, that is, in the range of the electric field actually generated in the transistor operation, when the metal film thickness is small.
  • the hole mobility (see the ⁇ line) is higher than the hole mobility (see the ⁇ line) when the thickness of the metal film is large.
  • the (100) plane substrate and (110) plane substrate When compared with the case, as can be seen from FIGS. 1A and 1B, the degree in the case of the (110) plane substrate is larger than the degree in the case of the (100) plane substrate.
  • the present inventors have found the following knowledge.
  • the hole mobility is effectively increased by reducing the film thickness of the metal film of the gate electrode, thereby further improving the performance of the p-type MIS transistor. Can be improved.
  • a semiconductor device includes (110) A semiconductor device including a p-type MIS transistor formed on a semiconductor substrate having a main surface as a main surface, wherein the p-type MIS transistor is formed on a first active region in the semiconductor substrate. And a first gate film formed on the first gate insulating film and made of a first metal film and a first silicon film formed on the first metal film, the first metal film comprising: The film thickness is 1 nm or more and 10 nm or less.
  • the thickness of the first metal film of the first gate electrode is 1 nm or more and 10 nm or less.
  • the thickness of the first metal film is 10 nm or less, an increase in EOT can be suppressed.
  • the first metal film preferably has a thickness of 1 nm or more and 5 nm or less.
  • the first gate insulating film preferably includes a high dielectric constant film made of a metal oxide.
  • a first offset spacer having an I-shaped cross section formed on the side surface of the first gate electrode, and a first offset on the side surface of the first gate electrode
  • a first sidewall having an L-shaped cross section formed through a spacer, and an upper surface of a region located on the side of the first sidewall in the first active region from the surface of the first sidewall
  • the semiconductor device further includes an n-type MIS transistor formed on the semiconductor substrate, and the n-type MIS transistor is formed on the second active region in the semiconductor substrate. And a second gate electrode having a second metal film formed on the second gate insulating film.
  • the second gate electrode includes a second metal film formed over the second gate insulating film and a second silicon formed over the second metal film. It is preferable that the first metal film and the second metal film have the same film thickness and are made of the same metal material.
  • the second gate electrode includes a second metal film formed over the second gate insulating film and a third metal formed over the second metal film. And a second silicon film formed on the third metal film, and the first metal film and the second metal film are made of different metal materials, and the first metal film and the second metal film.
  • the three metal films preferably have the same film thickness and are made of the same metal material.
  • the metal material of the second metal film in contact with the second gate insulating film that is, work suitable for the p-type MIS transistor.
  • a metal material having a work function suitable for an n-type MIS transistor can be used without using the same metal material as that having a function. Therefore, the performance of the n-type MIS transistor can be improved.
  • the second gate electrode includes a second metal film formed over the second gate insulating film, and the first metal film and the second metal film are
  • the second metal film is made of a metal material different from each other, and the film thickness of the second metal film is equal to the total film thickness obtained by adding up the film thickness of the first metal film and the film thickness of the first silicon film, or the total film It is preferable that the thickness is larger than the thickness.
  • the metal material of the second metal film in contact with the second gate insulating film that is, work suitable for the p-type MIS transistor.
  • a metal material having a work function suitable for an n-type MIS transistor can be used without using the same metal material as that having a function. Therefore, the performance of the n-type MIS transistor can be improved.
  • the first metal film and the second metal film have different work functions.
  • the first gate insulating film and the second gate insulating film include high dielectric constant films made of the same metal oxide.
  • a second offset spacer having an I-shaped cross section formed on the side surface of the second gate electrode and a second offset on the side surface of the second gate electrode
  • a second sidewall having an L-shaped cross section formed through a spacer, and an upper surface of a region located on the side of the second sidewall in the second active region from the surface of the second sidewall It is preferable to further include a second insulating film formed over the top.
  • the second insulating film is preferably a stress insulating film that generates tensile stress in the gate length direction of the channel region in the second active region.
  • the tensile stress can be applied in the gate length direction of the channel region in the second active region by the stress insulating film, the performance of the n-type MIS transistor can be improved.
  • a method for manufacturing a semiconductor device includes: A method of manufacturing a semiconductor device including a p-type MIS transistor formed in a first active region in a semiconductor substrate having a (110) plane as a main surface, wherein gate insulation is provided on the first active region in the semiconductor substrate.
  • Gate insulation film and first metal film formation film And a step (d) of forming a first metal film and a first gate electrode comprising a first silicon film comprising a silicon film formation film, wherein the first metal film formation film has a thickness of 1 nm. It is above and is 10 nm or less.
  • the thickness of the first metal film of the first gate electrode is 1 nm or more and 10 nm or less.
  • the thickness of the first metal film is 10 nm or less, an increase in EOT can be suppressed.
  • the first metal film forming film preferably has a thickness of 1 nm or more and 5 nm or less.
  • the semiconductor device further includes an n-type MIS transistor formed in the second active region of the semiconductor substrate, and the step (a) includes the second step of the semiconductor substrate.
  • the step (d) includes a step of forming a gate insulating film forming film on the active region, and the step (d) includes forming a second film by sequentially patterning the silicon film forming film, the first metal film forming film, and the gate insulating film forming film.
  • the method includes a step of forming the second gate electrode.
  • the semiconductor device further includes an n-type MIS transistor formed in the second active region of the semiconductor substrate, and the step (a) includes the second step of the semiconductor substrate.
  • the method further includes a step (e) of forming a metal film forming film, wherein the step (b) includes forming a first metal on the gate insulating film forming film on the first active region and on the second metal film forming film.
  • the step (d) includes a step of forming a film formation film.
  • the step (d) includes sequentially patterning the silicon film formation film, the first metal film formation film, the second metal film formation film, and the gate insulating film formation film, thereby A second insulating film formed on the active region of the gate insulating film; A gate insulating film, a second metal film made of a second metal film forming film, a third metal film made of a first metal film forming film, and a second silicon film made of a silicon film forming film It is preferable to include a step of forming the second gate electrode.
  • the metal material having a work function suitable for the n-type MIS transistor can be used as the metal material of the second metal film, the performance of the n-type MIS transistor can be improved.
  • the semiconductor device further includes an n-type MIS transistor formed in the second active region of the semiconductor substrate, and the step (a) includes the second step of the semiconductor substrate.
  • the step (d) includes a step of forming a gate insulating film forming film on the active region, and the step (d) includes forming a second film by sequentially patterning the silicon film forming film, the first metal film forming film, and the gate insulating film forming film. Forming a second gate insulating film made of a gate insulating film forming film, a dummy metal film made of the first metal film forming film, and a dummy silicon film made of a silicon film forming film on the active region.
  • Gate power Preferably further comprising a step (f) forming a.
  • the metal material having a work function suitable for the n-type MIS transistor can be used as the metal material of the second metal film, the performance of the n-type MIS transistor can be improved.
  • the dummy metal film and the dummy silicon film formed with high precision can be replaced with the second metal film. Therefore, the second gate electrode made of the second metal film can be formed with high accuracy.
  • the film of the first metal film of the first gate electrode is 1 nm or more and 10 nm or less.
  • the hole mobility can be effectively increased and the performance of the p-type MIS transistor can be further improved.
  • the thickness of the first metal film is 10 nm or less, an increase in EOT can be suppressed.
  • FIG. 1 (a) is a graph showing the relationship between the effective electric field and the hole mobility in the p-type MIS transistor formed on the (100) plane substrate when the metal film thickness is small and large. It is.
  • FIG. 1B shows the relationship between the effective electric field and the hole mobility in the p-type MIS transistor formed on the (110) plane substrate when the metal film thickness is small and large. It is a graph to show.
  • FIGS. 2A to 2C are cross-sectional views of relevant steps in the gate length direction showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps. FIGS.
  • FIGS. 3A to 3C are cross-sectional views of relevant steps in the gate length direction showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps.
  • FIGS. 4A to 4C are cross-sectional views of relevant steps in the gate length direction showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps.
  • FIG. 5 is a graph showing the relationship between the thickness of the metal film and the hole mobility, and the relationship between the thickness of the metal film and EOT.
  • FIGS. 6 (a) to 6 (c) are cross-sectional views of main steps in the gate length direction showing the method of manufacturing the semiconductor device according to the second embodiment of the present invention in the order of steps.
  • FIGS. 7A to 7C are cross-sectional views of relevant steps in the gate length direction showing the method of manufacturing the semiconductor device according to the second embodiment of the present invention in the order of steps.
  • FIGS. 8A to 8C are cross-sectional views of relevant steps in the gate length direction showing the method of manufacturing the semiconductor device according to the third embodiment of the present invention in the order of steps.
  • FIGS. 9A to 9C are cross-sectional views of relevant steps in the gate length direction showing the method of manufacturing the semiconductor device according to the third embodiment of the present invention in the order of steps.
  • FIGS. 10A to 10C are cross-sectional views of relevant steps in the gate length direction showing the method of manufacturing the semiconductor device according to the third embodiment of the present invention in the order of steps.
  • FIGS. 2A to 4C are cross-sectional views of essential steps in the gate length direction showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps. 2A to FIG. 4C, FIG. 6A to FIG. 7C to be described later, and FIG. 8A to FIG. 10C to be described later.
  • an embedded element isolation (Shallow) Trench ⁇ Isolation: STI) method an upper portion of a semiconductor substrate 10 made of, for example, p-type silicon and having a (110) plane as a main surface is formed.
  • An element isolation region 11 in which an insulating film is embedded in the trench is selectively formed.
  • a first active region 10 a made of the semiconductor substrate 10 surrounded by the element isolation region 11 is formed in the pMIS region.
  • a second active region 10b made of the semiconductor substrate 10 surrounded by the element isolation region 11 is formed in the nMIS region.
  • an n-type impurity such as P (phosphorus) is implanted into the pMIS region in the semiconductor substrate 10 by lithography and ion implantation.
  • a p-type impurity such as B (boron) is implanted into the nMIS region in the semiconductor substrate 10.
  • the semiconductor substrate 10 is heat-treated at, for example, 850 ° C. for 30 seconds.
  • an n-type well region 12 a is formed in the pMIS region in the semiconductor substrate 10.
  • a p-type well region 12 b is formed in the nMIS region in the semiconductor substrate 10.
  • the first active region 10a and the first active region 10a and by, for example, ISSG (In-Situ Steam Generation) oxidation method is cleaned by, for example, dilute hydrofluoric acid treatment, the first active region 10a and the first active region 10a and by, for example, ISSG (In-Situ Steam Generation) oxidation method.
  • a base film (not shown) made of a silicon oxide film having a film thickness of, for example, 0.8 nm to 1 nm is formed.
  • a gate insulating film made of a high dielectric constant film having a thickness of, for example, 2 nm is formed on the base film by, for example, metal organic chemical vapor deposition (MOCVD) method or ALD (Atomic Layer Deposition) method.
  • MOCVD metal organic chemical vapor deposition
  • ALD Atomic Layer Deposition
  • a first metal film forming film 14 made of, for example, titanium nitride (TiN) is deposited on the gate insulating film forming film 13 by, eg, CVD (Chemical Vapor Deposition), ALD, or sputtering.
  • the first metal film forming film 14 has a film thickness of, for example, 1 nm or more and 10 nm or less (preferably, for example, 1 nm or more and 5 nm or less).
  • a silicon film forming film 15 made of, for example, a polysilicon film having a thickness of 100 nm is deposited on the first metal film forming film 14 by, eg, CVD.
  • a resist pattern (not shown) having a gate pattern shape is formed on the silicon film forming film 15 by photolithography. Thereafter, using the resist pattern as a mask, the silicon film forming film 15, the first metal film forming film 14, and the gate insulating film forming film 13 are sequentially patterned by dry etching. Thus, the first gate insulating film 13a, the first metal film 14a, and the first silicon film 15a are sequentially formed on the first active region 10a. At the same time, a second gate insulating film 13b, a second metal film 14b, and a second silicon film 15b are sequentially formed on the second active region 10b. Thereafter, the resist pattern is removed.
  • first gate insulating film 13a and the first gate electrode 14A made of the first metal film 14a and the first silicon film 15a are formed on the first active region 10a.
  • a second gate insulating film 13b and a second gate electrode 14B made of the second metal film 14b and the second silicon film 15b are formed on the second active region 10b.
  • an offset spacer insulating film made of a silicon oxide film having a thickness of, for example, 8 nm is deposited on the entire surface of the semiconductor substrate 10 by, eg, CVD. Thereafter, anisotropic etching is performed on the insulating film for offset spacer.
  • a first offset spacer 16a having an I-shaped cross section is formed on the side surfaces of the first gate insulating film 13a and the first gate electrode 14A.
  • a second offset spacer 16b having an I-shaped cross section is formed on the side surfaces of the second gate insulating film 13b and the second gate electrode 14B.
  • a p-type impurity such as BF 2 is implanted into the first active region 10a using the first gate electrode 14A as a mask by lithography and ion implantation.
  • a p-type source / drain region (LDD region or extension region) 17a having a relatively shallow junction depth is formed in a self-aligned manner below the side of the first gate electrode 14A in the first active region 10a.
  • an n-type impurity such as As (arsenic) is implanted into the second active region 10b using the second gate electrode 14B as a mask.
  • an n-type source / drain region (LDD region or extension region) 17b having a relatively shallow junction depth is formed in a self-aligned manner below the side of the second gate electrode 14B in the second active region 10b.
  • the inner sidewall insulating film made of, for example, a silicon oxide film having a thickness of 10 nm and the film thickness of 30 nm are formed on the entire surface of the semiconductor substrate 10 by, eg, CVD.
  • An insulating film for the outer side wall made of a silicon nitride film is sequentially deposited. Thereafter, anisotropic etching is performed on the inner sidewall insulating film and the outer sidewall insulating film.
  • the first inner sidewall 18a having the L-shaped cross section and the first side wall are formed on the side surfaces of the first gate insulating film 13a and the first gate electrode 14A via the first offset spacer 16a.
  • a first sidewall 19A composed of the outer sidewall 19a is formed.
  • a second inner side wall 18b having a L-shaped cross section and a second shape are provided via a second offset spacer 16b.
  • a second sidewall 19B composed of the outer sidewall 19b is formed.
  • the first active region 10a is masked with the first gate electrode 14A, the first offset spacer 16a, and the first sidewall 19A, for example, B (boron) or the like.
  • a p-type impurity is implanted.
  • the p-type source / drain having a junction depth deeper than the shallow p-type source / drain region 17a and relatively deep in the first active region 10a outside the first sidewall 19A.
  • the region 20a is formed in a self-aligning manner.
  • an n-type impurity such as As (arsenic) is implanted into the second active region 10b using the second gate electrode 14B, the second offset spacer 16b, and the second sidewall 19B as a mask.
  • the n-type source / drain having a junction depth deeper than the shallow n-type source / drain region 17b and relatively deep in the second active region 10b outside the second sidewall 19B.
  • the region 20b is formed in a self-aligning manner. Thereafter, the conductive impurities contained in the deep p-type and n-type source / drain regions 20a and 20b are activated by heat treatment.
  • the first and second inner sidewalls (silicon oxide films) 18a and 18b are selectively used for the first and second etching methods using a dry etching method or a wet etching method.
  • the second outer side walls (silicon nitride films) 19a and 19b are removed.
  • a natural oxide film (not shown) formed on the surface of the deep p-type and n-type source / drain regions 20a and 20b, and the first and second silicon films 15a. , 15b, a natural oxide film (not shown) formed on the upper surface is removed.
  • a metal film for silicide (not shown) made of nickel (Ni) having a thickness of 10 nm, for example, is deposited on the entire surface of the semiconductor substrate 10 by, for example, sputtering.
  • the Si in the deep p-type and n-type source / drain regions 20a and 20b is reacted with Ni in the metal film for silicide by, for example, a first RTA (Rapid Thermal Annealing) process at 320 ° C. in a nitrogen atmosphere.
  • First and second metal silicide films 21a and 21b made of nickel silicide are formed on the deep p-type and n-type source / drain regions 20a and 20b.
  • the Si of the first and second silicon films 15a and 15b and Ni of the metal film for silicide are reacted to form a third of nickel silicide on the first and second silicon films 15a and 15b.
  • Fourth metal silicide films 22a and 22b are formed.
  • the semiconductor substrate 10 is immersed in an etching solution made of a mixed solution of sulfuric acid and hydrogen peroxide.
  • an etching solution made of a mixed solution of sulfuric acid and hydrogen peroxide.
  • first and second insulating films 23a and 23b made of a silicon nitride film of, eg, a 50 nm-thickness are deposited on the entire surface of the semiconductor substrate 10 by, eg, plasma CVD. (Note that the first insulating film 23a and the second insulating film 23b are integrally formed).
  • a first interlayer insulating film 24 made of a silicon oxide film is deposited on the first and second insulating films 23a and 23b by, for example, CVD, and then the first interlayer insulating film 24 by, for example, CMP (Chemical-Mechanical-Polishing) is used.
  • CMP Chemical-Mechanical-Polishing
  • the first insulating film 23a and the first interlayer insulating film 24 are formed on the first insulating film 23a and the first interlayer insulating film 24 by the dry etching method, as in the method of manufacturing the semiconductor device having a normal MIS transistor.
  • a first contact hole 25a exposing the upper surface of one metal silicide film 21a is formed.
  • a second contact hole 25 b exposing the upper surface of the second metal silicide film 21 b is formed in the second insulating film 23 b and the first interlayer insulating film 24.
  • the etching is stopped once when the first and second insulating films 23a and 23b are exposed, and the first and second metal silicide films 21a and 21b are used by using a two-step etching method in which etching is performed again.
  • the amount of overetching can be reduced.
  • a barrier metal formed by sequentially depositing titanium and titanium nitride on the bottom and side walls of the first and second contact holes 25a and 25b and the first interlayer insulating film 24 by sputtering or CVD.
  • a film is formed.
  • a conductive film made of tungsten is deposited on the barrier metal film by CVD so as to fill the first and second contact holes 25a and 25b.
  • portions of the conductive film and the barrier metal film formed outside the first and second contact holes 25a and 25b are removed by CMP.
  • first and second contact plugs 26a and 26b are formed in which the conductive film is buried in the first and second contact holes 25a and 25b via the barrier metal film.
  • metal wiring (not shown) that is electrically connected to the first and second contact plugs 26 a and 26 b is formed on the first interlayer insulating film 24.
  • the semiconductor device according to the present embodiment that is, the p-type MIS transistor PTr having the first gate electrode 14A composed of the first metal film 14a and the first silicon film 15a, and the second metal A semiconductor device including the n-type MIS transistor NTr having the second gate electrode 14B made of the film 14b and the second silicon film 15b can be manufactured.
  • a p-type MIS transistor PTr is provided in the pMIS region of the semiconductor substrate 10 having the (110) plane as a main surface, and the n-type MIS is provided in the nMIS region of the semiconductor substrate 10.
  • a transistor NTr is provided.
  • the p-type MIS transistor PTr includes a first gate insulating film 13a formed on the first active region 10a and a first gate insulating film 13a formed on the first gate insulating film 13a.
  • a first gate electrode 14A composed of one metal film 14a and a first silicon film 15a, a first offset spacer 16a having an I-shaped cross section formed on the side surface of the first gate electrode 14A, A shallow p-type source / drain region 17a formed laterally below the first gate electrode 14A in the first active region 10a and a first offset spacer 16a formed on the side surface of the first gate electrode 14A.
  • the n-type MIS transistor NTr includes a second gate insulating film 13b formed on the second active region 10b and a second gate insulating film 13b formed on the second gate insulating film 13b.
  • a second gate electrode 14B composed of two metal films 14b and a second silicon film 15b, a second offset spacer 16b having an I-shaped cross section formed on the side surface of the second gate electrode 14B, A shallow n-type source / drain region 17b formed laterally below the second gate electrode 14B in the second active region 10b, and a second offset spacer 16b formed on a side surface of the second gate electrode 14B.
  • a first interlayer insulating film 24 is formed on the integrally formed first and second insulating films 23a and 23b.
  • a first contact plug 26a having a lower end connected to the first metal silicide film 21a is formed in the first insulating film 23a and the first interlayer insulating film 24.
  • a second contact plug 26b whose lower end is connected to the second metal silicide film 21b is formed.
  • the thickness of the first metal film 14a is 1 nm or more and 10 nm or more (preferably 1 nm or more and 5 nm or less).
  • the first metal film 14a and the second metal film 14b have the same film thickness and are made of the same metal material (for example, TiN).
  • the first metal film 14a and the second metal film 14b have the same work function.
  • the first gate insulating film 13a and the second gate insulating film 13b include high dielectric constant films made of the same metal oxide.
  • the inventors of the present invention made extensive studies and found the following knowledge.
  • the hole mobility is effectively increased by reducing the film thickness of the metal film of the gate electrode, thereby further improving the performance of the p-type MIS transistor. be able to.
  • FIG. 5 is a graph showing the relationship between the thickness of the metal film and the hole mobility, and the relationship between the thickness of the metal film and EOT.
  • FIG. 5 indicates the relationship between the thickness of the metal film and the hole mobility in the p-type MIS transistor formed on the (110) plane substrate. For comparison, the relationship between the thickness of the metal film and the hole mobility in a p-type MIS transistor formed on a (100) plane substrate is shown (see FIG. 5: line ⁇ ).
  • FIG. 5 indicates the relationship between the thickness of the metal film and the EOT in the p-type MIS transistor formed on the (110) plane substrate. For comparison, the relationship between the thickness of the metal film and the EOT in a p-type MIS transistor formed on a (100) plane substrate is shown (see FIG. 5: ⁇ line).
  • the configuration of the p-type MIS transistors of the ⁇ line, ⁇ line, ⁇ line, and ⁇ line is as follows.
  • the p-type MIS transistor includes a gate insulating film and a gate electrode having a MIPS structure.
  • the gate insulating film is made of a high dielectric constant film containing Hf.
  • the metal film of the gate electrode is a TiN film having a film thickness of 4 nm, 10 nm, or 15 nm.
  • the silicon film of the gate electrode is made of a polysilicon film having a thickness of 100 nm.
  • the hole mobility can be effectively increased if the thickness of the metal film is 10 nm or less, and preferably the thickness of the metal film is 5 nm or less.
  • the hole mobility can be increased more effectively.
  • the EOT is substantially constant when the thickness of the metal film is 4 nm or more and 10 nm or less.
  • EOT increases as the thickness of the metal film increases.
  • the thickness of the metal film is preferably 10 nm or less as can be seen from the ⁇ line in FIG.
  • EOT increases as the thickness of the metal film increases.
  • the amount of oxygen contained in the metal film increases. Oxygen contained in the metal film diffuses into the gate insulating film during heat treatment (specifically, for example, RTA treatment) performed after the metal film is formed. Therefore, as the thickness of the metal film increases, the amount of oxygen that diffuses into the gate insulating film increases, so that EOT increases.
  • the thickness of the metal film As described above, by setting the thickness of the metal film to 10 nm or less, the hole mobility can be effectively increased and the performance of the p-type MIS transistor can be further improved. In addition, an increase in EOT can be suppressed by setting the thickness of the metal film to 10 nm or less. Furthermore, the hole mobility can be more effectively increased by setting the thickness of the metal film to 5 nm or less. Therefore, the upper limit of the thickness of the metal film is preferably 10 nm (preferably 5 nm).
  • the lower limit of the thickness of the metal film is preferably 1 nm.
  • the film thickness of the metal film is 1 nm or more.
  • the thickness of the metal film is preferably 1 nm or more.
  • the thickness of the metal film is less than 1 nm, the gate electrode is easily depleted, and the effective thickness of the gate insulating film increases due to the depletion of the gate electrode. Therefore, the lower limit of the film thickness of the metal film is preferably 1 nm from the viewpoint of film formation uniformity and depletion suppression.
  • the thickness of the first metal film 14a of the first gate electrode 14A is 1 nm or more. And 10 nm or less (preferably 1 nm or more and 5 nm or less). Thereby, the hole mobility can be effectively increased and the performance of the p-type MIS transistor can be further improved.
  • the thickness of the first metal film 14a is 10 nm or less, an increase in EOT can be suppressed.
  • first and second outer side walls 19a and 19b are removed, they are formed integrally with each other as shown in FIG. 4B.
  • first and second insulating films 23a and 23b a case where a base insulating film made of a silicon nitride film is formed by plasma CVD, for example, has been described as a specific example.
  • the present invention is not limited to this. is not.
  • a base insulating film is formed as the first insulating film, while the gate of the channel region in the second active region is used as the second insulating film.
  • a stress insulating film that generates tensile stress in the long direction may be formed.
  • a silicon nitride film containing a large amount of hydrogen is deposited by, for example, a plasma CVD method, and then the hydrogen contained in the silicon nitride film is blown off by ultraviolet irradiation, thereby causing stress.
  • a method of forming an insulating film is given.
  • the tensile stress can be applied in the gate length direction of the channel region in the second active region by the stress insulating film, the performance of the n-type MIS transistor can be improved.
  • the stress insulating film is formed after the removal of the second outer side wall, the stress insulating film can be formed as thick as the second outer side wall is removed. A tensile stress can be effectively applied in the gate length direction of the channel region.
  • the stress insulating film is formed after the removal of the second outer side wall, the stress insulating film is formed as close to the channel region in the second active region as the second outer side wall is removed. Therefore, tensile stress can be effectively applied in the gate length direction of the channel region in the second active region.
  • a first stress insulating film that generates compressive stress in the gate length direction of the channel region in the first active region is used as the first insulating film.
  • a second stress insulating film that generates a tensile stress in the gate length direction of the channel region in the second active region may be formed as the second insulating film.
  • the compressive stress can be applied in the gate length direction of the channel region in the first active region by the first stress insulating film, the performance of the p-type MIS transistor can be improved.
  • the first stress insulating film is formed after the removal of the first outer side wall, the first stress insulating film can be formed thicker by the amount removed of the first outer side wall. A compressive stress can be effectively applied in the gate length direction of the channel region in the first active region.
  • the first stress insulating film is formed after the removal of the first outer side wall, the first stress insulating film is removed from the channel region in the first active region by the amount removed of the first outer side wall. Therefore, compressive stress can be effectively applied in the gate length direction of the channel region in the first active region.
  • the metal oxide of the high dielectric constant film included in the gate insulating film forming film 13 in this embodiment for example, hafnium oxide (HfO 2 ), hafnium silicate (HfSiO), nitrided hafnium silicate (HfSiON), etc. And oxides containing tantalum (Ta), zirconium (Zr), titanium (Ti), aluminum (Al), scandium (Sc), yttrium (Y), lanthanum (La), and the like.
  • a polysilicon film is used as the silicon film forming film 15, but an amorphous silicon film, a silicon film, or the like may be used instead.
  • Ni is used as the material for the silicide metal film, but a metal for silicide such as platinum, cobalt, titanium, and tungsten may be used instead.
  • a semiconductor device and a manufacturing method thereof according to a second embodiment of the present invention will be described with reference to the drawings.
  • the semiconductor device and the manufacturing method thereof according to the second embodiment will be described mainly with respect to the differences from the semiconductor device according to the first embodiment and the manufacturing method thereof, and common points will be omitted as appropriate. I will explain.
  • FIG. 6A to FIG. 7C are cross-sectional views of relevant steps in the gate length direction showing the method of manufacturing the semiconductor device according to the second embodiment of the present invention in the order of steps. 6 (a) to 7 (c), the same components as those in the first embodiment are shown in FIGS. 2 (a) to 4 (c) in the first embodiment.
  • the first active region 10a and the second active region 10b are formed by, for example, ISSG oxidation.
  • a base film (not shown) made of a silicon oxide film having a thickness of 0.8 nm to 1 nm, for example, is formed.
  • a gate insulating film forming film 13 made of a high dielectric constant film having a film thickness of, for example, 2 nm is deposited on the base film by, eg, MOCVD or ALD.
  • a second metal film forming film 27 made of, for example, tantalum nitride (TaN) having a film thickness of 5 nm is deposited on the gate insulating film forming film 13 by, eg, CVD, ALD, or sputtering.
  • a resist pattern 28 that opens the pMIS region and covers the nMIS region is formed on the second metal film forming film 27 by photolithography.
  • the portion formed in the pMIS region in the second metal film formation film 27 is removed by dry etching or wet etching. As a result, the upper surface of the portion formed in the pMIS region in the gate insulating film forming film 13 is exposed, while the second metal film forming film 27 is formed on the portion formed in the nMIS region in the gate insulating film forming film 13. To remain. Thereafter, the resist pattern 28 is removed.
  • the second metal is formed on the gate insulating film forming film 13 on the second active region 10b (that is, the portion formed on the second active region 10b in the gate insulating film forming film 13).
  • a film forming film 27 is formed.
  • the first metal made of, for example, TiN is formed on the portion of the gate insulating film forming film 13 formed in the pMIS region and the second metal film forming film 27 by, for example, CVD, ALD, or sputtering.
  • a film forming film 14 is deposited.
  • the first metal film forming film 14 has a film thickness of, for example, 1 nm or more and 10 nm or less (preferably, for example, 1 nm or more and 5 nm or less).
  • the gate insulating film forming film 13 on the first active region 10a that is, the portion formed on the first active region 10a in the gate insulating film forming film 13
  • the second metal film formation are formed.
  • a first metal film formation film 14 is formed on the film 27.
  • a silicon film forming film 15 made of, for example, a polysilicon film having a thickness of 100 nm is deposited on the first metal film forming film 14 by, eg, CVD.
  • a resist pattern (not shown) having a gate pattern shape is formed on the silicon film forming film 15 by photolithography.
  • the silicon film formation film 15, the first metal film formation film 14, the second metal film formation film 27, and the gate insulating film formation film 13 are sequentially patterned by dry etching using the resist pattern as a mask.
  • the first gate insulating film 13a, the first metal film 14a, and the first silicon film 15a are sequentially formed on the first active region 10a.
  • a second gate insulating film 13b, a second metal film 27b, a third metal film 14bx, and a second silicon film 15b are sequentially formed on the second active region 10b.
  • the resist pattern is removed.
  • the first gate insulating film 13a and the first gate electrode 14A made of the first metal film 14a and the first silicon film 15a are formed on the first active region 10a.
  • a second gate insulating film 13b, a second gate electrode 27B made of the second metal film 27b, the third metal film 14bx, and the second silicon film 15b Form.
  • a first offset spacer 16a is formed on the side surfaces of the first gate insulating film 13a and the first gate electrode 14A.
  • a second offset spacer 16b is formed on the side surfaces of the second gate insulating film 13b and the second gate electrode 27B.
  • a p-type source / drain region 17a having a relatively shallow junction depth is formed below the side of the first gate electrode 14A in the first active region 10a.
  • an n-type source / drain region 17b having a relatively shallow junction depth is formed below the side of the second gate electrode 27B in the second active region 10b.
  • steps similar to those shown in FIGS. 3 (b) to (c) and FIGS. 4 (a) to (c) in the first embodiment are sequentially performed to obtain the configuration shown in FIG. 7 (c).
  • the semiconductor device according to the present embodiment that is, the p-type MIS transistor PTr having the first gate electrode 14A composed of the first metal film 14a and the first silicon film 15a, and the second metal A semiconductor device including the n-type MIS transistor NTr having the second gate electrode 27B made of the film 27b, the third metal film 14bx, and the second silicon film 15b can be manufactured.
  • the second gate electrode 14B includes a second metal film 14b made of, for example, TiN, and a second silicon film 15b made of, for example, a polysilicon film. Consists of.
  • the second metal film 14b in contact with the second gate insulating film 13b has the same film thickness as the first metal film 14a in contact with the first gate insulating film 13a, and the same metal as the first metal film 14a. Made of material.
  • the second gate electrode 27B includes a second metal film 27b made of TaN, for example, and a third metal film 14bx made of TiN, for example.
  • a second silicon film 15b made of a polysilicon film for example, a metal material different from the first metal film 14a in contact with the first gate insulating film 13a (in other words, the second metal film 27b is The work function is different from that of the first metal film 14a).
  • the third metal film 14bx has the same film thickness as the first metal film 14a and is made of the same metal material as the first metal film 14a.
  • the metal material of the metal film in contact with the second gate insulating film 13b is different between the present embodiment and the first embodiment (first embodiment: TiN, second embodiment: TaN).
  • the work function of TaN has a work function suitable for an n-type MIS transistor compared to the work function of TiN. Therefore, in this embodiment, the performance of the n-type MIS transistor NTr can be improved as compared with the first embodiment.
  • a metal material for example, TaN
  • a work function suitable for the n-type MIS transistor can be used as the metal material of the second metal film 27b, the performance of the n-type MIS transistor can be improved.
  • a semiconductor device and a manufacturing method thereof according to a third embodiment of the present invention will be described with reference to the drawings.
  • the semiconductor device and the manufacturing method thereof according to the third embodiment will be described mainly with respect to differences from the semiconductor device according to the first embodiment and the manufacturing method thereof, and common points will be omitted as appropriate. I will explain.
  • FIGS. 8A to 8C are cross-sectional views of relevant steps in the gate length direction showing the method of manufacturing the semiconductor device according to the third embodiment of the present invention in the order of steps.
  • FIGS. 8 (a) to 10 (c) the same components as those in the first embodiment are shown in FIGS. 2 (a) to 4 (c) in the first embodiment.
  • a resist pattern (not shown) having a gate pattern shape is formed on the silicon film formation film by photolithography. Thereafter, using the resist pattern as a mask, the silicon film forming film, the first metal film forming film, and the gate insulating film forming film are sequentially patterned by dry etching. Thus, the first gate insulating film 13a, the first metal film 14a, and the first silicon film 15a are sequentially formed on the first active region 10a. At the same time, a second gate insulating film 13b, a dummy metal film 14by, and a dummy silicon film 15by are sequentially formed on the second active region 10b. Thereafter, the resist pattern is removed.
  • the first gate insulating film 13a and the first gate electrode 14A made of the first metal film 14a and the first silicon film 15a are formed on the first active region 10a.
  • a second gate insulating film 13b and a dummy gate electrode 14BY composed of a dummy metal film 14by and a dummy silicon film 15by are formed on the second active region 10b.
  • First and second insulating films 23a and 23b made of, for example, a 50 nm-thickness silicon nitride film are deposited on the entire surface of the substrate 10 (note that the first insulating film 23a and the second insulating film 23b are integrated with each other). Formed).
  • a first interlayer insulating film 24 made of a silicon oxide film is deposited on the first and second insulating films 23a and 23b by, eg, CVD. Thereafter, for example, by CMP, the first interlayer insulating film is exposed until the upper surfaces of the portions formed on the third and fourth metal silicide films 22a and 22b in the first and second insulating films 23a and 23b are exposed. 24 is removed by polishing. After that, the first interlayer insulating film 24, the first and second insulating films 23a and 23b, the third and the third are continuously processed by CMP until the upper surfaces of the first silicon film 15a and the dummy silicon film 15by are exposed. The fourth metal silicide films 22a and 22b, the first and second offset spacers 16a and 16b, and the first and second inner sidewalls 18a and 18b are removed by polishing.
  • a resist pattern 29 that covers the pMIS region and opens the nMIS region is formed on the semiconductor substrate 10. Thereafter, using the resist pattern 29 as a mask, the dummy metal film 14by, the second offset spacer 16b, the second inner sidewall 18b, the second insulating film 23b, and the first interlayer insulating film 24 are selectively dried.
  • the dummy silicon film 15by in the dummy gate electrode 14BY is removed using an etching method or a wet etching method.
  • the dummy silicon film 15by and the dummy metal film 14by in the dummy gate electrode 14BY are sequentially removed to form a recess 30 in which the second gate insulating film 13b is exposed on the bottom surface.
  • a second metal film made of, for example, TaN so as to fill the recess 30 in the entire surface of the semiconductor substrate 10 by, for example, CVD, ALD, or sputtering.
  • a formation film 31 is deposited.
  • the second metal film forming film 31 is removed by, for example, a CMP method or an etch back method until the upper surface of the first interlayer insulating film 24 is exposed. Thereby, the second metal film 31 b is formed in the recess 30.
  • the second gate electrode 31B made of the second metal film 31b is formed on the second gate insulating film 13b.
  • the entire surface of the semiconductor substrate 10 is formed by sputtering, for example.
  • a metal film for silicide (not shown) made of Ni having a thickness of 10 nm is deposited.
  • the Si of the first silicon film 15a and Ni of the metal film for silicide are reacted by, for example, the first RTA process under a nitrogen atmosphere at 320 ° C., and the upper part of the first silicon film 15a
  • a metal silicide film 32 made of nickel silicide is formed.
  • the semiconductor substrate 10 is immersed in an etching solution made of a mixed solution of sulfuric acid and hydrogen peroxide.
  • an etching solution made of a mixed solution of sulfuric acid and hydrogen peroxide.
  • the first interlayer insulating film 24, the first and second insulating films 23a and 23b, the first and second inner sidewalls 18a and 18b, and the first and second offset spacers 16a in the metal film for silicide. , 16b and the like that is, unreacted portions in the silicide metal film
  • the silicide composition ratio of the metal silicide film 32 is stabilized by the second RTA process under a temperature (for example, 550 ° C.) higher than the temperature in the first RTA process.
  • the second interlayer insulating film is formed on the first interlayer insulating film 24 so as to cover the first and second gate electrodes 14A and 31B by, for example, the CVD method.
  • the surface of the second interlayer insulating film 33 is planarized by, eg, CMP.
  • the first metal film 23a, the first interlayer insulating film 24, and the second interlayer insulating film 33 are formed on the first metal film 23a, the first interlayer insulating film 24, and the second metal film by dry etching in the same manner as in the method of manufacturing a semiconductor device having a normal MIS transistor.
  • a first contact hole 25a exposing the upper surface of the silicide film 21a is formed.
  • a second contact hole 25b exposing the upper surface of the second metal silicide film 21b is formed in the second insulating film 23b, the first interlayer insulating film 24, and the second interlayer insulating film 33.
  • first and second contact plugs 26a and 26b are formed in the first and second contact holes 25a and 25b, in which a conductive film is buried via a barrier metal film. Thereafter, metal wiring (not shown) that is electrically connected to the first and second contact plugs 26 a and 26 b is formed on the second interlayer insulating film 33.
  • the semiconductor device according to the present embodiment that is, the p-type MIS transistor PTr having the first gate electrode 14A composed of the first metal film 14a and the first silicon film 15a, and the second metal A semiconductor device including the n-type MIS transistor NTr having the second gate electrode 31B made of the film 31b can be manufactured.
  • the first insulating film 23a is formed on the first inner side wall 18a in the first active region 10a from the upper surface of the first gate electrode 14A. It is formed over the upper surface of the region located on the side of.
  • the second insulating film 23b is formed so as to extend from the upper surface of the second gate electrode 14B to the upper surface of the region located on the side of the second inner sidewall 18b in the second active region 10b. Has been.
  • the first insulating film 23a is formed on the first inner side wall 18a from the first inner side in the first active region 10a. It is formed across the upper surface of the region located on the side of the sidewall 18a.
  • the second insulating film 23b extends from the surface of the second inner side wall 18b to the upper surface of the region located on the side of the second inner side wall 18b in the second active region 10b. Is formed.
  • the second gate electrode 14B includes a second metal film 14b made of, for example, TiN, and a second silicon film 15b made of, for example, a polysilicon film. Consists of.
  • the second metal film 14b in contact with the second gate insulating film 13b has the same film thickness as the first metal film 14a in contact with the first gate insulating film 13a, and the same metal as the first metal film 14a. Made of material.
  • the second gate electrode 31B is made of the second metal film 31b made of TaN, for example.
  • the second metal film 31b in contact with the second gate insulating film 13b is made of a metal material different from the first metal film 14a in contact with the first gate insulating film 13a (in other words, the second metal film 31b is The work function is different from that of the first metal film 14a).
  • the film thickness T31b of the second metal film 31b is larger than the total film thickness obtained by adding the film thickness T14a of the first metal film 14a and the film thickness T15a of the first silicon film 15a (T31b> T14a + T15a).
  • the metal material of the metal film in contact with the second gate insulating film 13b is different between the present embodiment and the first embodiment (first embodiment: TiN, third embodiment: TaN).
  • the second gate electrode 31B in the present embodiment is made of only a metal film
  • the second gate electrode 14B in the first embodiment is made of a metal film and a silicon film.
  • the second gate electrode 31B made of only the second metal film 31b is formed as follows. As shown in FIG. 8A, the silicon film forming film, the first metal film forming film, and the gate insulating film forming film are sequentially patterned to form the second gate insulating film 13b, the dummy metal film 14by, and the dummy silicon. A dummy gate electrode 14BY made of the film 15by is formed. Thereafter, as shown in FIG. 9B, the dummy silicon film 15by and the dummy metal film 14by in the dummy gate electrode 14BY are sequentially removed to form the recesses 30. Thereafter, as shown in FIG. 10A, a second metal film 31b is formed in the recess 30 to form a second gate electrode 31B made of only the second metal film 31b.
  • the following method may be mentioned.
  • the metal film forming film and the gate insulating film forming film are sequentially patterned to form a gate insulating film and a gate electrode made of only the metal film.
  • this method has the following problems. In general, it is difficult to pattern a metal film forming film with higher accuracy than a silicon film forming film. Therefore, in this method, since the metal film forming film is relatively thick, the gate electrode cannot be formed with high accuracy.
  • the dummy gate electrode 14BY can be formed with high accuracy.
  • the second metal film is formed in the concave portion (that is, the concave portion formed with high precision) 30 formed by sequentially removing the dummy silicon film 15by and the dummy metal film 14by in the dummy gate electrode 14BY formed with high precision. 31b can be formed. Therefore, the second gate electrode 31B made of the second metal film 31b can be formed with high accuracy.
  • the metal material for example, TaN
  • the metal material of the second metal film 31b since the metal material (for example, TaN) having a work function suitable for the n-type MIS transistor can be used as the metal material of the second metal film 31b, the performance of the n-type MIS transistor can be improved. (That is, the same effect as in the second embodiment can be obtained).
  • the dummy gate electrode 14BY can be formed with high accuracy.
  • the dummy metal film 14by and the dummy silicon film 15by in the dummy gate electrode 14BY formed with high precision can be replaced with the second metal film 31b. Therefore, the second gate electrode 31B made of the second metal film 31b can be formed with high accuracy.
  • the metal silicide film is formed on the upper portion of the first silicon film 15a as shown in FIG. 10B. 32, and then, as shown in FIG. 10C, the case where the second interlayer insulating film 33 and the first and second contact plugs 26a and 26b are formed has been described as a specific example.
  • the present invention is not limited to this.
  • the second interlayer insulating film and the first and second contact plugs may be formed without forming the metal silicide film on the first silicon film.
  • the thickness of the second metal film is equal to the total thickness obtained by adding the thickness of the first metal film and the thickness of the first silicon film.
  • the present invention can further improve the performance of a p-type MIS transistor in a p-type MIS transistor formed on a semiconductor substrate having a (110) plane as a main surface. It is useful for the manufacturing method.

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Abstract

L'invention concerne un dispositif semi-conducteur comportant un transistor MIS de type p (PTr) formé sur un substrat semi-conducteur (10) présentant une (110) surface comme surface principale. Le transistor MIS de type p (PTr) comporte une première pellicule d'isolation de gâchette (13a) formée sur la première zone active (10) au niveau du substrat semi-conducteur (10) et une première électrode de gâchette (14A) formée sur la première pellicule d'isolation de gâchette (13a) et constituée d'une première pellicule de métal (14a) et une première pellicule de silicium (15a) formée sur la première pellicule de métal (14a). L'épaisseur de la première pellicule de métal (14a) est comprise entre 1 nm et 10 nm.
PCT/JP2010/000754 2009-04-09 2010-02-08 Dispositif semi-conducteur et son procédé de production WO2010116587A1 (fr)

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JP2008518487A (ja) * 2004-11-02 2008-05-29 インテル コーポレイション 高誘電率ゲート誘電体層及びシリサイドゲート電極を有する半導体デバイスの製造方法
JP2006237372A (ja) * 2005-02-25 2006-09-07 Toshiba Corp 半導体装置
JP2007049166A (ja) * 2005-08-10 2007-02-22 Toshiba Corp 近接した応力ライナー膜を有する半導体装置及びその製造方法
JP2007088122A (ja) * 2005-09-21 2007-04-05 Renesas Technology Corp 半導体装置
JP2007208260A (ja) * 2006-01-31 2007-08-16 Samsung Electronics Co Ltd 二重仕事関数金属ゲートスタックを備えるｃｍｏｓ半導体装置
JP2007318015A (ja) * 2006-05-29 2007-12-06 Renesas Technology Corp 半導体装置およびその製造方法
JP2008205012A (ja) * 2007-02-16 2008-09-04 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JP2009043760A (ja) * 2007-08-06 2009-02-26 Toshiba Corp 半導体装置

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