WO2010082239A1 - Comparateur et convertisseur analogique/numérique - Google Patents

Comparateur et convertisseur analogique/numérique Download PDF

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Publication number
WO2010082239A1
WO2010082239A1 PCT/JP2009/003476 JP2009003476W WO2010082239A1 WO 2010082239 A1 WO2010082239 A1 WO 2010082239A1 JP 2009003476 W JP2009003476 W JP 2009003476W WO 2010082239 A1 WO2010082239 A1 WO 2010082239A1
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Prior art keywords
substrate bias
comparator
voltage
unit
current
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PCT/JP2009/003476
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English (en)
Japanese (ja)
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佐塚友彦
中順一
須志原公治
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パナソニック株式会社
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Publication of WO2010082239A1 publication Critical patent/WO2010082239A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/249—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors using clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
    • H03K3/0233—Bistable circuits
    • H03K3/02335—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0018—Special modifications or use of the back gate voltage of a FET

Definitions

  • the present disclosure relates to a comparator that receives a differential input signal pair and performs a comparison operation on a differential voltage of the differential input signal pair in synchronization with a clock signal.
  • FIG. 6 shows an example of the configuration of the dynamic comparator 1 used in the comparator constituting the A / D converter with high speed and low power consumption.
  • a dynamic comparator 1 shown in FIG. 6 includes an input transistor unit 10 composed of NMOS transistors m0a and m0b, and a positive feedback unit (cross-coupled inverter latch unit) 20 including NMOS transistors m1a and m1b and PMOS transistors m3a and m3b.
  • the output terminal q is connected to the gate terminals of the transistors m1a and m3a and the drain terminal of the transistor m3b, and the output terminal qb is connected to the gate terminals of the transistors m1b and m3b and the drain terminal of the transistor m3a.
  • the NMOS transistor m2a is connected between the drain terminal of the NMOS transistor m1a and the drain terminal of the PMOS transistor m3a, and the NMOS transistor m2a acts as a switch in synchronization with the clock signal CLK.
  • An NMOS transistor m2b is connected between the drain terminal of the NMOS transistor m1b and the drain terminal of the PMOS transistor m3b, and the NMOS transistor m2b acts as a switch in synchronization with the clock signal CLK.
  • the source terminals of the PMOS transistors m3a and m3b are connected to the power supply VDD.
  • a PMOS transistor m4a is connected between the drain terminal of the PMOS transistor m3a and the power supply VDD, and the PMOS transistor m4a acts as a switch in synchronization with the clock signal CLK.
  • a PMOS transistor m4b is connected between the drain terminal of the PMOS transistor m3b and the power supply VDD, and the PMOS transistor m4b acts as a switch in synchronization with the clock signal CLK.
  • the gate terminal of the NMOS transistor m0a is connected to the positive electrode ia of the differential input signal pair, the source terminal is connected to the reference potential VSS, and the drain terminal is connected to the source terminal of the NMOS transistor m1a.
  • the gate terminal of the NMOS transistor m0b is connected to the negative electrode ib of the differential input signal pair, the source terminal is connected to the reference potential VSS, and the drain terminal is connected to the source terminal of the NMOS transistor m1b.
  • the gate terminals of the NMOS transistors m2a and m2b and the gate terminals of the PMOS transistors m4a and m4b are connected to the clock signal CLK.
  • the input transistor unit 10 outputs a comparison result obtained by comparing the positive electrode ia and the negative electrode ib of the differential input signal pair to the positive feedback unit 20.
  • the positive feedback unit 20 turns off the PMOS transistors m4a and m4b and turns off the NMOS transistors m2a and m2b. ),
  • the comparison result output from the input transistor unit 10 is amplified, the amplified comparison result is held, and the amplified comparison result is output as a digital signal to the output terminals q and qb.
  • the PMOS transistors m4a and m4b are turned on and the output terminals q and qb are reset to the power supply voltage VDD, that is, “High”. . Further, the NMOS transistors m2a and m2b are in an open state (OFF), the current path is cut off, and the power consumption is almost 0 (zero). As a result, the dynamic comparator 1 has the advantage of saving power.
  • the gate-source voltage of the PMOS transistors m3a and m3b of the positive feedback section 20 is Vgs (p)
  • the gate-source voltage of the NMOS transistors m1a and m1b is Vgs (n )
  • the voltage at the output node a of the input unit 10 is Va
  • the gate-source voltage Vgs (p) of the PMOS transistors m3a and m3b is expressed by the following equation (1.1).
  • Vgs (p) VDD- [Va + Vgs (n)] ... (1.1)
  • the power supply voltage VDD has been decreasing along with the reduction in power consumption of CMOS integrated circuits.
  • the gate-source voltage Vgs (p) expressed by the above equation (1.1) decreases. Since the current flowing through the MOS transistor is expressed as a positive function of (Vgs ⁇ Vt), the differential current flowing through the comparator 1 is decreased by the decrease in Vgs (p), and the delay time of the comparator 1 is increased.
  • the differential current flowing through the dynamic comparator 1 is small due to the above cause, it takes time until a voltage difference is generated between the output terminals q and qb, so that the delay time until the positive feedback starts is increased. Since the differential current generated by the positive feedback voltage at the output terminals q and qb has decreased even after the positive feedback has started, it takes time for the potential difference between the output terminals q and qb to increase due to the positive feedback. Accordingly, the delay time until the “Low” and “High” digital values are output increases.
  • the current flowing through the power source-GND current path of the dynamic comparator 1 is one of the MOS transistors (m3a, m2a, m1a, m0a), (m3b, m2b, m1b, m0b) that form the power source-GND current path. This is expressed by a positive function of (Vgs ⁇ Vt) obtained from the gate-source voltage Vgs and the threshold voltage Vt.
  • One method for increasing the current flowing through the comparator 1 is to reduce the threshold voltage Vt of the transistors constituting the comparator 1.
  • the substrate bias control is generally known as a means for reducing the threshold voltage Vt.
  • the substrate bias control is a method of controlling the current value by utilizing the fact that the absolute value of the threshold voltage is reduced by supplying the forward bias voltage to the substrate potential.
  • the threshold voltage Vt can be lowered to increase the value of (Vgs ⁇ Vt), and the operating current can be increased to prevent an increase in delay time.
  • a means for detecting the current drop factor of the comparator 1 is provided in order to increase the comparator current using substrate bias control. From the above equation (1.1), the current flowing through the comparator 1 at the time of comparison decreases when the power supply voltage VDD decreases, when the potential Va of the node a increases, or when Vgs (n) increases. Therefore, a means for detecting the current reduction factor is proposed below.
  • a comparator includes a dynamic comparison unit (1), a current reduction factor detection unit (2), and a substrate bias control unit (3), and the dynamic comparison unit (1) , A MOS transistor, and a comparison unit (10) that outputs a comparison result between one voltage (ia) and the other voltage (ib) of a differential signal that is input, and a MOS transistor that includes a clock signal ( CLK)), and a positive feedback section (20) that amplifies the comparison result from the comparison section (10) and outputs it to the output node pair (q, qb), and the current decrease factor detection section (2) detects a decrease factor of the current flowing through the dynamic comparison unit (1), and the substrate bias control unit (3) detects a decrease factor by the current decrease factor detection unit (2).
  • the current decrease factor detection unit (2a) detects a decrease in the power supply voltage (VDD) of the dynamic comparison unit (1)
  • the substrate bias control unit (3a) detects the current decrease factor detection unit
  • the substrate bias voltage (VBIAS3) of the MOS transistors (m0a, m0b) constituting the comparison unit (10) and / or the positive feedback unit When a decrease in the power supply voltage (VDD) is detected by 2a), the substrate bias voltage (VBIAS3) of the MOS transistors (m0a, m0b) constituting the comparison unit (10) and / or the positive feedback unit (
  • the substrate bias voltages (VBIAS1, VBIAS2) of the MOS transistors (m2a, m2b, m3a, m3b) constituting 20) are controlled so as to decrease the threshold voltage of the MOS transistors.
  • the current drop factor detection unit (2b) is configured to include a threshold voltage of the MOS transistors (m0a, m0b) constituting the comparison unit (10) and / or a MOS transistor (m) constituting the positive feedback unit (20) ( m2a, m2b, m3a, m3b) detects that the threshold voltage is higher than a predetermined reference, and the substrate bias control unit (3b) detects the threshold voltage from the reference by the current decrease factor detection unit (2b).
  • the substrate bias voltages (VBIAS1, VBIAS2) of m2a, m2b, m3a, m3b) are controlled in a direction in which the threshold voltage of the MOS transistor becomes smaller.
  • the current decrease factor detection unit (2d) includes a replica circuit (401) having a circuit configuration similar to that of the dynamic comparison unit (1), and an output (q) of the replica circuit (401) is the replica circuit ( 401) and an output monitor (402) for determining whether or not the input (VREF ⁇ ⁇ X) is being followed, and the substrate bias control unit (3d) follows the current drop factor detection unit (2d).
  • the threshold voltage is controlled so as to decrease.
  • the conventional comparator used in the A / D converter reduces the differential current and slows down the conversion time when the power supply voltage decreases or the threshold voltage of the constituent transistors is high. According to the comparator, when the power supply voltage drops or the threshold voltage of the constituent transistors is high, the comparison time does not increase due to the current decrease, and the A / D converter is faster than the A / D converter using the conventional comparator. Conversion is possible.
  • FIG. 1 is a diagram showing a configuration of a comparator according to the first embodiment.
  • FIG. 2 is a diagram showing a configuration of a comparator according to the second embodiment.
  • FIG. 3 is a diagram showing a configuration of a comparator according to the third embodiment.
  • FIG. 4 is a diagram showing a configuration of a comparator according to the fourth embodiment.
  • FIG. 5 is a diagram showing a configuration of an A / D converter according to the fifth embodiment.
  • FIG. 6 is a diagram showing an example of the configuration of a conventional dynamic comparator.
  • This comparator includes a dynamic comparator 1, a current drop factor detection unit 2a, and a substrate bias control unit 3a.
  • the dynamic comparator 1 has the same configuration as that shown in FIG. However, in this embodiment, the substrate bias voltage VBIAS3 is supplied to the NMOS transistors m0a and m0b of the input unit 10, and the substrate bias voltage VBIAS2 from the substrate bias control unit 3a is supplied to the NMOS transistors m1a and m1b of the positive feedback unit 20. Then, the substrate bias voltage VBIAS1 from the substrate bias control unit 3a is supplied to the PMOS transistors m3a and m3b of the positive feedback unit 20.
  • the current drop factor detection unit 2a includes a band gap reference (BGR) circuit 101, an amplifier 102, a reference voltage generation circuit 106, and a comparator 107 for determination.
  • BGR band gap reference
  • the output voltage VBGR + of the BGR circuit 101 and the voltage VBGR ⁇ of the interconnection node of the resistors 104 and 105 are input to the amplifier 102.
  • the amplifier 102 supplies a voltage corresponding to the difference between the input voltages VBGR + and VBGR ⁇ to the gate of the PMOS transistor 103.
  • a current flows through the reference voltage generation circuit 106 by the PMOS transistor 103. This current value is stabilized at a value at which the voltage VBGR ⁇ at the interconnection node of the resistors 104 and 105 becomes the same as the output voltage VBGR + of the BGR circuit 101.
  • the reference voltage generation circuit 106 outputs the voltage at the interconnection node between the PMOS transistor 103 and the resistor 104 as the reference voltage VDDREF.
  • the comparator 107 for determination is when the power supply voltage VDD of the dynamic comparator 1 is equal to or higher than the reference voltage VDDREF from the reference voltage generation circuit 106 (VDDREF ⁇ VDD), that is, the decrease width of the power supply voltage VDD of the dynamic comparator 1 Is less than ⁇ , the L level substrate bias control signal VBCTL is output, and when the reference voltage VDDREF from the reference voltage generation circuit 106 is larger than the power supply voltage VDD of the dynamic comparator 1 (VDDREF> VDD), that is, When the decrease width of the power supply voltage VDD of the dynamic comparator 1 exceeds ⁇ , the H level substrate bias control signal VBCTL is output.
  • the output VBCTL of the judgment comparator 107 is the dynamic comparator 1
  • the drop of power supply voltage VDD exceeds 50mV, it switches from L level to H level.
  • the substrate bias control unit 3a supplies the substrate bias voltage VBIAS1 to the PMOS transistors m3a and m3b of the positive feedback unit 20 of the dynamic comparator 1.
  • the substrate bias control unit 3a supplies the substrate bias voltage VBIAS2 to the NMOS transistors m1a and m1b of the positive feedback unit 20 of the dynamic comparator 1.
  • the substrate bias control unit 3a supplies the substrate bias voltage VBIAS3 to the NMOS transistors m0a and m0b of the input unit 10 of the dynamic comparator 1.
  • the substrate bias controller 3a controls the substrate bias voltages VBIAS1, VBIAS2, and VBIAS3 supplied to the MOS transistors (m3a, m3b), (m1a, m1b), (m0a, m0b) of the dynamic comparator 1 as follows. .
  • the L level substrate vise control signal VBCTL is given to the substrate vise control unit 3a.
  • the substrate vise control unit 3a supplies the VDD level substrate bias voltage VBIAS1 to the PMOS transistors m3a, m3b of the positive feedback unit 20, and the NMOS transistors m1a, A VSS level substrate bias voltage VBIAS2 is supplied to m1b, and a VSS level substrate bias voltage VBIAS3 is supplied to the NMOS transistors m0a and m0b of the input unit 10.
  • the substrate bias control signal VBCTL switches from L level to H level.
  • the substrate vise controller 3a executes the following [Controls 1 to 3]. Note that only one of the following [controls 1 to 3] may be executed, only two of them may be executed, or all may be executed.
  • the substrate bias control unit 3a In response to the substrate bias control signal VBCTL at the H level, the substrate bias control unit 3a lowers the level of the substrate bias voltage VBIAS1 supplied to the PMOS transistors m3a and m3b of the positive feedback unit 20 below VDD. This increases the current flowing through the PMOS transistors m3a and m3b during the positive feedback operation of the dynamic comparator 1, and decreases the delay time during the positive feedback operation.
  • the substrate vise controller 3a raises the level of the substrate bias voltage VBIAS2 supplied to the NMOS transistors m1a and m1b of the positive feedback unit 20 to be higher than VSS. This increases the current flowing through the NMOS transistors m1a and m1b during the positive feedback operation of the dynamic comparator 1, and decreases the delay time during the positive feedback operation.
  • the substrate vise control unit 3a raises the level of the substrate bias voltage VBIAS3 supplied to the NMOS transistors m0a and m0b of the input unit 10 higher than VSS. As a result, the current generated in the input unit 10 is increased, and the delay time until the potential difference necessary for starting positive feedback to occur between the output nodes a and b of the input unit 10 is reduced.
  • the first embodiment it is possible to reduce the delay time generated at the time of positive feedback due to the current reduction that has been a problem in the prior art.
  • the dynamic comparator 1 shown in FIG. 1 is merely an example, and the configuration thereof is not limited as long as it is a dynamic comparator that operates in synchronization with a clock signal.
  • the dynamic comparator disclosed in FIG. 2 of Patent Document 2 Japanese Patent Laid-Open No. 2003-158456 may be used.
  • the configuration of the comparator according to the second embodiment is shown in FIG.
  • This comparator includes a dynamic comparator 1, a current drop factor detection unit 2b, and a substrate bias control unit 3b.
  • the dynamic comparator 1 has the same configuration as that shown in FIG.
  • the current decrease factor detection unit 2b includes Vt detection units 201 to 203 and determination comparators 204 to 206.
  • the Vt detection unit 201 detects the threshold voltage Vt of the PMOS transistors m3a and m3b of the positive feedback unit 20 of the comparator 1 and outputs the absolute value
  • the Vt detector 202 detects the threshold voltage Vt of the NMOS transistors m1a and m1b of the positive feedback unit 20 of the comparator 1 and outputs the absolute value
  • the Vt detection unit 203 detects the threshold voltage Vt of the NMOS transistors m0a and m0b of the input unit 10 of the comparator 1 and outputs the absolute value
  • the Vt detectors 201 to 203 can be realized based on the disclosure of [Non-Patent Document 1], for example.
  • the determination comparator 204 When the absolute value
  • the determination comparator 205 When the absolute value
  • the comparator 206 for determination When the absolute value
  • the substrate bias control unit 3b supplies the substrate bias voltage VBIAS1 to the PMOS transistors m3a and m3b of the positive feedback unit 20 of the dynamic comparator 1.
  • the substrate bias control unit 3b supplies the substrate bias voltage VBIAS2 to the NMOS transistors m1a and m1b of the positive feedback unit 20 of the dynamic comparator 1.
  • the substrate bias controller 3b supplies a substrate bias voltage VBIAS3 to the NMOS transistors m0a and m0b of the input unit 10 of the dynamic comparator 1.
  • the substrate bias controller 3b controls the substrate bias voltages VBIAS1, VBIAS2, and VBIAS3 supplied to the MOS transistors (m3a, m3b), (m1a, m1b), (m0a, m0b) of the dynamic comparator 1 as follows. .
  • the substrate bias control unit 3b applies the substrate bias voltage VBIAS1 at the VDD level to the PMOS transistors m3a and m3b of the positive feedback unit 20.
  • the VSS level substrate bias voltage VBIAS2 is supplied to the NMOS transistors m1a and m1b of the positive feedback unit 20, and the VSS level substrate bias voltage VBIAS3 is supplied to the NMOS transistors m0a and m0b of the input unit 10.
  • the substrate vise controller 3b executes the following [Controls 1 to 3]. Note that only one of the following [controls 1 to 3] may be executed, only two of them may be executed, or all may be executed. Further, the substrate bias control signals VBCTL1, VBCTL2, and VBCTL3 may be executed in association with the following [Controls 1 to 3].
  • the following [Control 1] is executed when the substrate bias control signal VBCTL1 from the judgment comparator 204 is at the H level, and when the substrate bias control signal VBCTL2 from the judgment comparator 205 is at the H level, the following [Control 2] may be executed, and the following [Control 3] may be executed when the substrate bias control signal VBCTL3 from the determination comparator 206 is at the H level.
  • the substrate vise control unit 3b sets the level of the substrate bias voltage VBIAS1 supplied to the PMOS transistors m3a and m3b of the positive feedback unit 20 to be lower than VDD. This increases the current flowing through the PMOS transistors m3a and m3b during the positive feedback operation of the dynamic comparator 1, and decreases the delay time during the positive feedback operation.
  • the substrate vise control unit 3b makes the level of the substrate bias voltage VBIAS2 supplied to the NMOS transistors m1a and m1b of the positive feedback unit 20 higher than VSS. This increases the current flowing through the NMOS transistors m1a and m1b during the positive feedback operation of the dynamic comparator 1, and decreases the delay time during the positive feedback operation.
  • the substrate vise control unit 3b makes the level of the substrate bias voltage VBIAS3 supplied to the NMOS transistors m0a and m0b of the input unit 10 higher than VSS. As a result, the current generated in the input unit 10 is increased, and the delay time until the potential difference necessary for starting positive feedback to occur between the output nodes a and b of the input unit 10 is reduced.
  • the threshold voltage Vt of the MOS transistors (m3a, m3b), (m1a, m1b), (m0a, m0b) constituting the comparator 1 is detected, and the absolute value of the threshold voltage Vt is detected.
  • is higher than the reference voltage VREFvt
  • the dynamic comparator 1 shown in FIG. 1 is merely an example, and the configuration thereof is not limited as long as it is a dynamic comparator that operates in synchronization with a clock signal.
  • the dynamic comparator disclosed in FIG. 2 of Patent Document 2 Japanese Patent Laid-Open No. 2003-158456 may be used.
  • Vt detection units 201 to 203 of the current decrease factor detection unit 2b may be only one or only two. The same applies to the comparators 204 to 206 for determination corresponding to the Vt detectors 201 to 203.
  • FIG. 1 The configuration of the comparator according to the third embodiment is shown in FIG.
  • This comparator includes a dynamic comparator 1, current reduction factor detectors 2a and 2b, and a substrate bias controller 3c.
  • the dynamic comparator 1 has the same configuration as that shown in FIG.
  • the current decrease factor detection unit 2a has the same configuration as that shown in FIG.
  • the current decrease factor detection unit 2b has the same configuration as that shown in FIG.
  • the substrate bias control unit 3c supplies the substrate bias voltage VBIAS1 to the PMOS transistors m3a and m3b of the positive feedback unit 20 of the dynamic comparator 1.
  • the substrate bias control unit 3c supplies the substrate bias voltage VBIAS2 to the NMOS transistors m1a and m1b of the positive feedback unit 20 of the dynamic comparator 1.
  • the substrate bias control unit 3c supplies the substrate bias voltage VBIAS3 to the NMOS transistors m0a and m0b of the input unit 10 of the dynamic comparator 1.
  • the substrate bias controller 3c controls the substrate bias voltages VBIAS1, VBIAS2, and VBIAS3 supplied to the MOS transistors (m3a, m3b), (m1a, m1b), (m0a, m0b) of the dynamic comparator 1 as follows. .
  • the substrate vise control unit 3c The substrate bias voltage VBIAS1 of VDD level is supplied to the PMOS transistors m3a and m3b of the first transistor, the substrate bias voltage VBIAS2 of VSS level is supplied to the NMOS transistors m1a and m1b of the positive feedback unit 20, and the NMOS transistors m0a and m0b of the input unit 10 Supply VSS level substrate bias voltage VBIAS3.
  • the substrate vise control unit 3c Execute ⁇ 3]. Note that only one of the following [controls 1 to 3] may be executed, only two of them may be executed, or all may be executed. Further, the substrate bias control signals VBCTL1, VBCTL2, and VBCTL3 may be executed in association with the following [Controls 1 to 3]. For example, when the substrate bias control signal VBCTL1 is at H level, the following [Control 1] is executed. When the substrate bias control signal VBCTL2 is at H level, the following [Control 2] is executed, and the substrate bias control signal VBCTL3 is at H level. In this case, the following [Control 3] may be executed.
  • the substrate vise control unit 3b sets the level of the substrate bias voltage VBIAS1 supplied to the PMOS transistors m3a and m3b of the positive feedback unit 20 to be lower than VDD. This increases the current flowing through the PMOS transistors m3a and m3b during the positive feedback operation of the dynamic comparator 1, and decreases the delay time during the positive feedback operation.
  • the substrate vise control unit 3b makes the level of the substrate bias voltage VBIAS2 supplied to the NMOS transistors m1a and m1b of the positive feedback unit 20 higher than VSS. This increases the current flowing through the NMOS transistors m1a and m1b during the positive feedback operation of the dynamic comparator 1, and decreases the delay time during the positive feedback operation.
  • the substrate vise control unit 3b makes the level of the substrate bias voltage VBIAS3 supplied to the NMOS transistors m0a and m0b of the input unit 10 higher than VSS. As a result, the current generated in the input unit 10 is increased, and the delay time until the potential difference necessary for starting positive feedback to occur between the output nodes a and b of the input unit 10 is reduced.
  • the current decrease factor detection unit 2a of FIG. 1 and the current decrease factor detection unit 2b of FIG. 2 are combined. It becomes easier to detect the current reduction factor (the probability of detection increases).
  • the dynamic comparator 1 shown in FIG. 3 is merely an example, and the configuration thereof is not limited as long as it is a dynamic comparator that operates in synchronization with a clock signal.
  • the dynamic comparator disclosed in FIG. 2 of Patent Document 2 Japanese Patent Laid-Open No. 2003-158456 may be used.
  • FIG. 4 shows the configuration of the comparator according to the fourth embodiment.
  • This comparator includes a dynamic comparator 1, a current drop factor detection unit 2c, and a substrate bias control unit 3d.
  • the dynamic comparator 1 has the same configuration as that shown in FIG.
  • the current decrease factor detection unit 2c includes a comparator replica circuit 401 and an output monitor logic 402.
  • the comparator replica circuit 401 is a replica circuit of the dynamic comparator 1.
  • the reference voltage VREF is input to the input ib of the comparator replica circuit 401, and the reference voltage ⁇ comparison minimum voltage (VREF ⁇ ⁇ X) is input to the input ia.
  • the comparator replica circuit 401 receives a clock signal CLK similar to the signal input to the dynamic comparator 1.
  • the substrate bias control unit 3d supplies the substrate bias voltage VBIAS1 to the PMOS transistors m3a and m3b of the positive feedback unit 20 of the dynamic comparator 1 and the comparator replica circuit 401.
  • the substrate bias control unit 3d supplies the substrate bias voltage VBIAS2 to the NMOS transistors m1a and m1b of the positive feedback unit 20 of the dynamic comparator 1 and the comparator replica circuit 401.
  • the substrate bias control unit 3d supplies the substrate bias voltage VBIAS3 to the NMOS transistors m0a and m0b of the input unit 10 of the dynamic comparator 1 and the comparator replica circuit 401.
  • the output monitor logic 402 monitors the output q of the comparator replica circuit 401.
  • the comparator replica circuit 401 operates normally, and the output q of the comparator replica circuit 401 follows the input signal VREF ⁇ ⁇ X and is synchronized with the clock signal CLK. It becomes.
  • the output monitor logic 402 outputs an L level substrate bias control signal VBCTL.
  • the substrate bias control unit 3d applies the VDD level to the PMOS transistors m3a and m3b of the positive feedback unit 20 of the dynamic comparator 1 and the comparator replica circuit 401.
  • the substrate bias voltage VBIAS1 is supplied
  • the VSS bias substrate bias voltage VBIAS2 is supplied to the NMOS transistors m1a and m1b of the positive feedback section 20 of the dynamic comparator 1 and the comparator replica circuit 401
  • the dynamic comparator 1 and the comparator A VSS level substrate bias voltage VBIAS3 is supplied to the NMOS transistors m0a and m0b of the input unit 10 of the replica circuit 401.
  • the substrate vise control unit 3d executes the following [Controls 1 to 3]. Note that only one of the following [controls 1 to 3] may be executed, only two of them may be executed, or all may be executed.
  • the substrate vise control unit 3d sets the level of the substrate bias voltage VBIAS1 supplied to the PMOS transistors m3a and m3b of the positive feedback unit 20 of the dynamic comparator 1 and the comparator replica circuit 401 to be lower than VDD. This increases the current flowing through the PMOS transistors m3a and m3b during the positive feedback operation and decreases the delay time during the positive feedback operation.
  • the substrate vise control unit 3d makes the level of the substrate bias voltage VBIAS2 supplied to the NMOS transistors m1a and m1b of the positive feedback unit 20 of the dynamic comparator 1 and the comparator replica circuit 401 higher than VSS. This increases the current flowing through the NMOS transistors m1a and m1b during the positive feedback operation and decreases the delay time during the positive feedback operation.
  • the substrate vise control unit 3d makes the level of the substrate bias voltage VBIAS3 supplied to the NMOS transistors m0a and m0b of the input unit 10 of the dynamic comparator 1 and the comparator replica circuit 401 higher than VSS. As a result, the current generated in the input unit 10 is increased, and the delay time until the potential difference necessary for starting positive feedback to occur between the output nodes a and b of the input unit 10 is reduced.
  • the dynamic comparator 1 shown in FIG. 4 is merely an example, and the configuration thereof is not limited as long as it is a dynamic comparator that operates in synchronization with a clock signal.
  • the dynamic comparator disclosed in FIG. 2 of Patent Document 2 Japanese Patent Laid-Open No. 2003-158456 may be used.
  • the comparators according to the first to fourth embodiments can be applied to, for example, a parallel A / D converter.
  • FIG. FIG. 5 shows an example in which the comparator (FIG. 1) according to the first embodiment is applied to the parallel A / D converter 800 disclosed in [FIG. 10] of Patent Document 2 (Japanese Patent Laid-Open No. 2003-158456). Indicates.
  • the comparator according to the first embodiment is applied to each of the comparison circuits Cr1 to Crn + 1 of the comparison circuit array 803 of the A / D converter 800.
  • FIG. 5 representatively shows a configuration when applied to the comparison circuit Cr1.
  • the comparator according to the first embodiment to the A / D converter 800, the operation speed of the A / D converter 800 can be improved.
  • the comparators according to the second to fourth embodiments are applied.
  • the comparator increases the amount of current flowing through the comparator even when the current decreases due to a decrease in power supply voltage or when the threshold voltage of the transistors constituting the comparator increases and the current decreases. In order to reduce the delay time of the comparator, it is useful if applied to an analog front end A / D converter of a digital read channel.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)

Abstract

Un module de détection de facteur de réduction de courant (2a) détecte une réduction d'une tension d'alimentation (VDD) d'un comparateur dynamique (1). Dès la détection d'une réduction de la tension d'alimentation (VDD) par le module de détection de facteur de réduction de courant (2a), un module de commande de polarisation de substrat (3a) commande une tension de polarisation de substrat (VBIAS3) de transistors MOS (m0a, m0b) constituant un module de comparaison (10) et/ou des tensions de polarisation de substrat (VBIAS1, VBIAS2) de transistors MOS (m2a, m2b, m3a, m3b) constituant un module de rétroaction positive (20) dans un sens de réduction de la tension de seuil des transistors MOS.
PCT/JP2009/003476 2009-01-13 2009-07-23 Comparateur et convertisseur analogique/numérique WO2010082239A1 (fr)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013207895A (ja) * 2012-03-28 2013-10-07 Fujitsu Ltd 昇降圧型ｄｃ−ｄｃコンバータおよび携帯機器
WO2021038349A1 (fr) * 2019-08-23 2021-03-04 株式会社半導体エネルギー研究所 Dispositif à semi-conducteur et procédé de fonctionnement de dispositif à semi-conducteur

Citations (4)

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Publication number Priority date Publication date Assignee Title
JP2001156261A (ja) * 1999-09-13 2001-06-08 Hitachi Ltd 半導体集積回路装置
JP2005123677A (ja) * 2003-10-14 2005-05-12 Renesas Technology Corp 半導体集積回路
JP2007184845A (ja) * 2006-01-10 2007-07-19 Sharp Corp 半導体装置
JP2007318457A (ja) * 2006-05-25 2007-12-06 Sony Corp コンパレータ並びにａ／ｄ変換器

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001156261A (ja) * 1999-09-13 2001-06-08 Hitachi Ltd 半導体集積回路装置
JP2005123677A (ja) * 2003-10-14 2005-05-12 Renesas Technology Corp 半導体集積回路
JP2007184845A (ja) * 2006-01-10 2007-07-19 Sharp Corp 半導体装置
JP2007318457A (ja) * 2006-05-25 2007-12-06 Sony Corp コンパレータ並びにａ／ｄ変換器

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013207895A (ja) * 2012-03-28 2013-10-07 Fujitsu Ltd 昇降圧型ｄｃ−ｄｃコンバータおよび携帯機器
WO2021038349A1 (fr) * 2019-08-23 2021-03-04 株式会社半導体エネルギー研究所 Dispositif à semi-conducteur et procédé de fonctionnement de dispositif à semi-conducteur
US11799430B2 (en) 2019-08-23 2023-10-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for operating semiconductor device

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