WO2010058441A1 - Équipement de test, procédé de test et programme - Google Patents

Équipement de test, procédé de test et programme Download PDF

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Publication number
WO2010058441A1
WO2010058441A1 PCT/JP2008/003395 JP2008003395W WO2010058441A1 WO 2010058441 A1 WO2010058441 A1 WO 2010058441A1 JP 2008003395 W JP2008003395 W JP 2008003395W WO 2010058441 A1 WO2010058441 A1 WO 2010058441A1
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Prior art keywords
phase
device under
test
under test
relative phase
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PCT/JP2008/003395
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English (en)
Japanese (ja)
Inventor
坂井満
Original Assignee
株式会社アドバンテスト
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Application filed by 株式会社アドバンテスト filed Critical 株式会社アドバンテスト
Priority to KR1020117008127A priority Critical patent/KR101221080B1/ko
Priority to PCT/JP2008/003395 priority patent/WO2010058441A1/fr
Priority to JP2010539052A priority patent/JPWO2010058441A1/ja
Priority to TW098138993A priority patent/TW201028707A/zh
Publication of WO2010058441A1 publication Critical patent/WO2010058441A1/fr
Priority to US13/084,561 priority patent/US20120123726A1/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C29/56012—Timing aspects, clock generation, synchronisation

Definitions

  • the present invention relates to a test apparatus, a test method, and a program.
  • the semiconductor test apparatus When testing a semiconductor device, the semiconductor test apparatus transmits / receives data synchronized with the clock to / from the device under test. In order to reliably transfer the data, it is preferable to sample the data at the center position of the data. However, when the frequency of data is high, the influence of wiring length skew and jitter increases with respect to UI (Unit Interval) which is a unit length of data. As a result, the eye opening of data received by the semiconductor test apparatus and the device under test is reduced. Therefore, in the semiconductor test apparatus, timing training for adjusting the timing of the clock and the data is required for the purpose of sampling the data at the center position in the time direction of the eye opening.
  • UI Unit Interval
  • Timing training is roughly classified into read training performed when reading data from the device under test and write training performed when writing data to the device under test.
  • the semiconductor test apparatus adjusts the phase of the strobe signal for latching so as to latch the data received from the device under test near the center position of the eye opening.
  • the semiconductor test apparatus adjusts the phase of data output to the device under test so that the device under test latches the received data near the center position of the eye opening.
  • the semiconductor test apparatus In order to detect the center position of the eye opening, the semiconductor test apparatus sequentially changes the relative phase of the data and the strobe, and determines whether the received data and the expected value match in each relative phase. judge. When it is determined that the received data does not match the expected value, the semiconductor test apparatus determines that the relative phase is in a fail state in which data cannot be transmitted / received normally. On the other hand, when the semiconductor test apparatus determines that the received data matches the expected value, it determines that the relative phase is in a path state where data can be normally transmitted and received.
  • the semiconductor test apparatus detects the left end of the eye opening by shifting the relative phase to the left side after setting the initial phase of the relative phase at the timing when the pass state is reached, and the eye opening by shifting to the right side.
  • the right edge of the part is detected.
  • the data output from the device under test or the phase of the strobe in the device under test is uncertain, it is difficult to set the initial phase of the relative phase at the timing of the pass state. As a result, there is a problem that it takes a long time to detect the end of the eye opening.
  • a test apparatus for testing a device under test, wherein input / output data of the device under test and a relative phase of a predetermined strobe signal are determined in advance.
  • a phase control unit that sequentially changes in one direction, and an expected value comparison unit that determines whether or not a value obtained by sampling input / output data with a strobe signal matches a predetermined expected value by a predetermined number of times in each relative phase
  • a first relative phase in which at least one of the predetermined number of determination results indicates a mismatch, a first relative phase in which all of the predetermined number of determination results indicate a match, and a transition from the path state to the fail state.
  • a phase detector that detects the second relative phase, and supplies the device under test based on the first relative phase and the second relative phase detected by the phase detector.
  • a phase adjusting unit for adjusting the phase of the test signal, with a test signal whose phase is adjusted by the phase adjusting unit to provide a test apparatus and a test unit for testing the device under test.
  • a test method for testing a device under test wherein input / output data of the device under test and a relative phase of a predetermined strobe signal are sequentially changed in a predetermined one direction, Whether or not the value obtained by sampling the input / output data with the strobe signal matches the predetermined expected value is determined a predetermined number of times in each relative phase, and at least one of the determination results of the predetermined number of times from the fail state indicating a mismatch
  • the first relative phase that transitions to the path state in which all of the determination results of the predetermined number of times match and the second relative phase that transitions from the path state to the fail state are detected, and the first relative phase and the second relative phase are detected.
  • a program for causing a test apparatus for testing a device under test to function, wherein the test apparatus includes input / output data of the device under test and a relative phase of a predetermined strobe signal.
  • a phase control unit that sequentially changes in one direction, and an expected value comparison unit that determines whether or not a value obtained by sampling input / output data with a strobe signal matches a predetermined expected value by a predetermined number of times in each relative phase
  • a first relative phase in which at least one of the predetermined number of determination results indicates a mismatch, a first relative phase in which all of the predetermined number of determination results indicate a match, and a transition from the path state to the fail state.
  • the device under test Based on the phase detector that detects the second relative phase and the first relative phase and the second relative phase detected by the phase detector, the device under test A phase adjusting unit for adjusting the phase of the sheet to the test signal, with a test signal whose phase is adjusted by the phase adjusting unit to provide the program to function as a test unit for testing the device under test.
  • FIG. 1 shows a configuration of a semiconductor test apparatus 100 according to the present embodiment.
  • the lead training procedure in the semiconductor test apparatus 100 according to the present embodiment is shown.
  • the light training procedure in the semiconductor test apparatus 100 according to the present embodiment is shown.
  • 5 shows a flowchart of timing training and testing of a device under test in the semiconductor test apparatus 100 according to the present embodiment.
  • a lead training procedure in the semiconductor test apparatus 100 according to the second embodiment will be described.
  • the lead training procedure in the semiconductor test apparatus 100 according to the third embodiment is shown.
  • the structure of the semiconductor test apparatus 100 which concerns on 4th Embodiment is shown.
  • 10 shows a configuration of a semiconductor test apparatus 100 according to a fifth embodiment.
  • FIG. 1 shows a configuration of a semiconductor test apparatus 100 according to the present embodiment.
  • the semiconductor test apparatus 100 includes a control unit 10, a test unit 20, a timing control unit 30, a phase control unit 40, a timing comparator 46, an expected value storage unit 50, an expected value comparison unit 52, a phase detection unit 54, and a phase adjustment unit 56.
  • An analysis memory 58 a fail memory 60, a driver 92, a level comparator 94, and a driver 96.
  • the device under test 200 includes an internal logic 210, a timing comparator 220, a level comparator 230, a driver 240, and a level comparator 250.
  • control unit 10 controls the test of the device under test 200.
  • the control unit 10 may be a CPU that operates according to a program stored in a nonvolatile memory.
  • the test unit 20 generates data and a clock used for timing training and testing of the device under test 200.
  • the test unit 20 determines the test result based on the data received from the device under test 200.
  • the timing control unit 30 generates timing signals, strobe signals, and setting signals used for timing training and testing of the device under test 200.
  • the timing control unit 30 may supply the strobe signal STB1 and the setting signal DLY1 to the delay circuit 44, the strobe signal STB2 to the test unit 20, the timing signal TMG to the expected value storage unit 50, and the setting signal DLY2 to the delay circuit 42.
  • the setting signal DLY1 and the setting signal DLY2 may be signals indicating values for setting the delay amounts of the delay circuit 44 and the delay circuit 42, respectively.
  • the phase control unit 40 includes a delay circuit 42 and a delay circuit 44, and controls the phase of the data and the strobe signal input to the phase control unit 40 according to the setting signal output from the timing control unit 30.
  • the phase control unit 40 sequentially changes the input / output data of the device under test 200 and the relative phase of the strobe signal output from the timing control unit 30 in a predetermined direction.
  • the phase control unit 40 may sequentially change the data output from the device under test 200 and the relative phase of the strobe signal that latches the data.
  • the phase control unit 40 may change only the phase of the input / output data, or may change both the phase of the input / output data and the strobe signal.
  • the timing control unit 30 generates a strobe signal STB1 that latches data output from the device under test 200.
  • the delay circuit 44 may delay the strobe signal STB1 based on the timing signal DLY1 output from the timing control unit 30. By sequentially delaying the timing signal DLY1, the relative phase of the strobe signal output from the delay circuit 44 sequentially changes in the delay direction.
  • the timing comparator 46 latches the data received from the device under test 200 based on the strobe signal whose relative phase has been changed by the delay circuit 44.
  • the timing comparator 46 sends the latched data to the expected value comparison unit 52.
  • the data output from the timing comparator 46 may be a logic signal of “1” or “0”.
  • the semiconductor test apparatus 100 may sequentially change the data and the relative phase of the clock output to the device under test 200 when performing light training.
  • the test unit 20 generates data and a clock to be output to the device under test 200.
  • the test unit 20 may generate the clock CLK1 output to the device under test 200 based on the strobe signal STB2 generated by the timing control unit 30.
  • the delay circuit 42 changes the relative phase with the clock CLK1 by delaying the data received from the test unit 20. Further, the delay circuit 42 sends the delayed data to the device under test 200.
  • the delay circuit 42 may determine the delay amount based on the timing signal DLY2 output from the timing control unit 30.
  • the device under test 200 may latch the data delayed by the delay circuit 42 based on the clock CLK1 generated by the test unit 20.
  • the semiconductor test apparatus 100 receives the response data generated according to the data latched by the device under test 200, thereby determining whether the device under test 200 has received data normally in each relative phase. You can do it.
  • the expected value storage unit 50 stores an expected value of data received from the device under test 200.
  • the expected value storage unit 50 may store an expected value used in timing training and an expected value used in a test of the device under test 200.
  • the expected value storage unit 50 may include a nonvolatile memory, and the stored expected value may be output to the expected value comparison unit 52 based on the timing signal TMG output from the timing control unit 30.
  • the expected value comparison unit 52 determines whether the value obtained by sampling the data input / output to / from the device under test 200 with the strobe signal output from the timing control unit 30 matches a predetermined expected value. A predetermined number of times is determined in the phase. For example, if the output value of the sampled timing comparator 46 is “1” and the expected value output from the expected value storage unit 50 is also “1”, the expected value comparing unit 52 determines that the expected value matches the expected value. Good. On the other hand, the expected value comparison unit 52 does not match the expected value if the sampled output value of the timing comparator 46 is "1" and the expected value output by the expected value storage unit 50 is "0". You may determine.
  • the expected value comparison unit 52 may store the determination result in each sampling in the analysis memory 58 connected to the test unit 20. For example, the expected value comparison unit 52 may store “0” in the analysis memory 58 for a sampling value that matches the expected value, and may store “1” for a sampling value that does not match the expected value. .
  • the phase detector 54 reads out the determination result stored in the analysis memory 58. Further, the phase detection unit 54 makes a transition from a fail state in which at least one of the predetermined number of determination results indicates a mismatch to a path state in which all of the predetermined number of determination results indicate a match based on the read determination result. , And a second relative phase that transitions from the pass state to the fail state.
  • the phase detection unit 54 reads out the determination result in each sampling from the analysis memory 58 for each relative phase, and the read determination result includes a predetermined number or more (one or more in this example) “1”. If it is, it may be determined as a fail state. Further, the phase detection unit 54 may determine that the path state is “0” when a predetermined number or more (all in this example) of values sampled over a predetermined number of times for each relative phase is “0”. The phase detection unit 54 determines that the relative phase at which the determination result transitions from the fail state to the pass state is the first relative phase, and sets the relative phase at which the determination result transitions from the pass state to the fail state is the second relative phase. It may be determined that the relative phase is.
  • the phase adjustment unit 56 adjusts the phase of the test signal supplied to the device under test 200 based on the first relative phase and the second relative phase detected by the phase detection unit 54. For example, when testing the device under test 200, the phase detector 54 sets the relative phase of the test clock and test data output from the test unit 20 to a phase approximately between the first relative phase and the second relative phase. Therefore, the phase of the test data output from the test unit 20 may be changed back and forth. By adjusting in this way, the device under test 200 can sample the received test data at a substantially central position of the eye opening.
  • the test unit 20 tests the device under test 200 using the test signal whose phase is adjusted by the phase adjustment unit 56.
  • the test unit 20 may send test data including digital data “1” and “0” based on a predetermined logic vector and a test clock synchronized with the test data to the device under test 200.
  • the relative phase of the test data and the test clock may be the relative phase obtained in the light training.
  • the device under test 200 generates response data with the internal logic 210 in accordance with the received test data, and outputs the response data to the semiconductor test apparatus 100.
  • the response data received from the device under test 200 is latched in the timing comparator 46.
  • the timing comparator 46 may latch the received data with a strobe signal having a relative phase obtained in the lead training.
  • the expected value comparison unit 52 compares the data received from the device under test 200 with the expected value, and outputs the comparison result to the test unit 20.
  • the test unit 20 may determine pass / fail of the device under test 200 based on the comparison result, and may store the determined result in the fail memory 60.
  • the timing control unit 30 may start generating a timing signal, a strobe signal, and a setting signal in response to a trigger from the control unit 10. Further, the test unit 20 and the timing control unit 30 may operate with the same clock. Therefore, the semiconductor test apparatus 100 does not need to send a timing training signal via the bus of the control unit 10. Further, when analyzing data received from the device under test 200, it is not necessary to go through the bus. As a result, the semiconductor test apparatus 100 according to the present embodiment can perform timing training at a higher speed than the method of controlling via the bus.
  • FIG. 2 shows a lead training procedure in the semiconductor test apparatus 100 according to the present embodiment.
  • clock indicates a clock transmitted from the semiconductor test apparatus 100 to the device under test 200.
  • Data indicates data output by the device under test 200.
  • Strobe indicates a strobe signal output from the delay circuit 44.
  • UI indicates the length of one unit of data output from the device under test 200.
  • the device under test 200 may output data in synchronization with the falling edge of the input clock. Further, the semiconductor test apparatus 100 outputs data having a value that matches the expected value only in one cycle during timing training, and outputs data having a value that does not match the expected value in other cycles. Device 200 may be controlled. One UI may be an integer multiple of the length of one clock cycle.
  • the phase of data output from the device under test 200 varies with respect to the phase of the clock output from the semiconductor test apparatus 100 due to the influence of jitter caused by power supply noise and the like. As a result, a value different from the data value output from the device under test 200 may be obtained near the data change point. Therefore, in order to obtain the data received from the device under test 200 without error, the semiconductor test apparatus 100 preferably samples at the center position of the eye opening, not near the data change point.
  • the phase control unit 40 determines the phase of the strobe signal output from the timing control unit 30 based on the timing signal output from the timing control unit 30 in order to detect the phase of the strobe signal sampled at the center position of the eye opening. And change sequentially. For example, the phase control unit 40 may change the relative phase of the strobe signal in one direction at a phase interval of T1 from the initial phase position to the final phase.
  • the delay circuit 44 when the read circuit is started, the delay circuit 44 generates a strobe signal whose relative phase with the data is in the initial phase.
  • the expected value comparison unit 52 compares the expected value with the expected value a predetermined number of times in the relative phase, and stores the determination result in the analysis memory 58.
  • the timing control unit 30 switches the timing signal output to the delay circuit 44.
  • the delay circuit 44 generates a strobe signal whose phase is different from the initial phase by T1 based on the switched timing signal.
  • the expected value comparison unit 52 compares the expected value with the expected value a predetermined number of times in the relative phase.
  • the delay circuit 44 may repeat the change every T1 until the phase of the strobe signal reaches the final phase.
  • the “failure rate” shown in FIG. 2 indicates a ratio of data that the expected value comparison unit 52 determines that does not match the expected value among the predetermined number of sampling data in each relative phase. For example, when the test unit 20 performs sampling 100 times in one relative phase, if the sampled data and the expected value read from the expected value storage unit 50 differ 100 times, the fail rate is 100%. is there. Similarly, when the sampled data and the expected value read from the expected value storage unit 50 are different 50 times, the fail rate is 50%. If the sampled data and the expected value all match, the fail rate is 0%.
  • the “determination result” indicates a result of the phase detection unit 54 determining whether the state is the fail state or the pass state based on the determination result of the expected value comparison unit 52 stored in the analysis memory 58.
  • a fail state is determined in a relative phase where the fail rate is not 0%
  • a pass state is determined in a relative phase where the fail rate is 0%.
  • the semiconductor test apparatus 100 cannot recognize whether the relative phase is in the pass state or the fail state at the time of starting the timing training. .
  • the phase control unit 40 may set the initial phase of the strobe signal to a phase where the fail state is detected.
  • the phase control unit 40 may be positioned away from the center position of the eye opening by 0.5 UI to 1.5 UI.
  • the relative phase of 0.5 UI to 1.5 UI there is a possibility that the received data and the expected value are different, so the fail rate does not become 0%. Therefore, when the initial phase is set within the range, the semiconductor test apparatus 100 can reliably detect the first relative phase that changes from the fail state to the pass state only by changing the relative phase in only one direction. Further, the second relative phase can be detected by further changing the relative phase after the detection of the first relative phase. As a result, the timing training time can be shortened.
  • the semiconductor test apparatus 100 sequentially changes the relative phase of the strobe signal, and then analyzes the received data from the device under test 200, so that the relative phase of transition from the fail state to the pass state, and the fail state from the pass state. You may detect the relative phase which changes to a state.
  • the phase detection unit 54 may detect the first relative phase and the second relative phase based on the data stored in the analysis memory 58.
  • FIG. 3 shows a light training procedure in the semiconductor test apparatus 100 according to the present embodiment.
  • a “clock” is a strobe signal sent from the semiconductor test apparatus 100 to the device under test 200.
  • Data is data transmitted from the semiconductor test apparatus 100 to the device under test 200.
  • the device under test 200 may acquire received data by latching data at the rising edge of the input clock. Further, the device under test 200 may send data corresponding to the acquired data to the semiconductor test apparatus 100.
  • the semiconductor test apparatus 100 can determine whether or not the device under test 200 has successfully acquired data by comparing the data received from the device under test 200 with an expected value.
  • the device under test 200 samples data at the center position of the eye opening of data received from the semiconductor test apparatus 100. Therefore, the semiconductor test apparatus 100 controls the phase of the data sent to the device under test 200 so that the sampling position of the device under test 200 substantially matches the eye opening center position of the data.
  • the phase control unit 40 sequentially changes the relative phase between the input data supplied to the device under test 200 and the clock corresponding to the strobe signal for sampling the input data inside the device under test 200 in a predetermined one direction.
  • the phase control unit 40 may sequentially change the relative phase of the data output to the device under test 200 and the clock by changing the delay amount applied to the data output to the device under test 200.
  • the phase control unit 40 may change the relative phase by changing the delay amount given to the clock, and may change the relative phase by changing the delay amount given to each of the data and the clock.
  • the timing comparator 220 When the timing comparator 220 receives data from the semiconductor test apparatus 100, the timing comparator 220 latches the data with the strobe signal received from the semiconductor test apparatus 100 and outputs the data to the internal logic 210.
  • the internal logic 210 loops back the latch signal received from the timing comparator 220 and sends it to the semiconductor test apparatus 100 via the driver 240.
  • the semiconductor test apparatus 100 may provide the device under test 200 with a control signal for outputting a UI signal larger than the UI of the signal transmitted by the semiconductor test apparatus 100.
  • the expected value comparison unit 52 receives from the device under test 200 the value of the input data acquired by the device under test 200 according to the strobe signal.
  • the expected value comparison unit 52 may receive data output from the device under test 200 via the phase control unit 40.
  • the phase control unit 40 latches the data received from the device under test 200 by the strobe signal output from the delay circuit 44 and sends the data to the expected value comparison unit 52.
  • the expected value comparison unit 52 may determine whether the data received from the phase control unit 40 matches the expected value read from the expected value storage unit 50.
  • the plurality of “data” shown in FIG. 3 indicates data having different relative phases, which is obtained by delaying the data generated by the test unit 20 in the delay circuit 42.
  • the timing comparator 220 latches data at the first boundary position of the data eye opening.
  • the determination result in the phase detector 54 transitions from the fail state to the pass state.
  • the timing comparator 220 latches data at the second boundary position of the data eye opening.
  • the determination result in the phase detector 54 transitions from the pass state to the fail state.
  • the timing comparator 220 latches data at a position separated by 0.5 UI or more from the center position of the data eye opening.
  • the rising edge of the clock output to the device under test 200 is based on the detected first relative phase and second relative phase, and the center of the eye opening of the data output to the device under test 200 is detected.
  • the phase of data may be controlled so as to substantially match the position.
  • FIG. 4 shows a flowchart of timing training and testing of a device under test in the semiconductor test apparatus 100 according to the present embodiment.
  • the timing control unit 30 sets the received data and the relative phase of the strobe signal for latching the data to the initial phase (S401). Subsequently, the timing control unit 30 delays the strobe signal by a predetermined amount to change the relative phase (S402).
  • the timing comparator 46 samples the data received from the device under test 200 in the relative phase, and then outputs the sampled data to the expected value comparison unit 52 (S403).
  • the expected value comparison unit 52 determines whether or not the received data matches the expected value read from the expected value storage unit 50, and stores the determination result in the analysis memory 58.
  • the timing control unit 30 changes the relative phase again (S402), and executes S403 and S404.
  • the phase detection unit 54 detects the first relative phase based on the determination data stored in the analysis memory 58 (S406). Subsequently, the phase detection unit 54 detects the second relative phase based on the determination data stored in the analysis memory 58 (S407).
  • the phase adjustment unit 56 adjusts the phase of the test signal supplied to the device under test 200 based on the first relative phase and the second relative phase (S408). For example, in the phase adjustment unit 56, the rising position of the clock that the semiconductor test apparatus 100 sends to the device under test 200 is approximately the center position of the eye opening of the data that the semiconductor test apparatus 100 sends to the device under test 200. In order to match, the phase of the data to be sent may be changed back and forth.
  • the semiconductor test apparatus 100 outputs the clock output from the test unit 20 and the data adjusted in phase by the phase adjustment unit 56 to the device under test 200 as test signals.
  • the device under test 200 sends data corresponding to the received test signal to the semiconductor test apparatus 100, and the test unit 20 makes a determination (S409).
  • FIG. 5 shows a lead training procedure in the semiconductor test apparatus 100 according to the second embodiment.
  • the phase control unit 40 changes the relative phase at a predetermined interval until the phase detection unit 54 detects the first relative phase, and the phase detection unit When the first relative phase is detected, the relative phase may be changed at a predetermined interval after the relative phase is changed at an interval larger than the predetermined interval.
  • the phase control unit 40 sequentially changes the phase of the strobe signal at intervals of T1 from the initial phase of the first change area shown in FIG.
  • the phase control unit 40 latches the data received from the device under test 200 with the strobe signal and sends it to the expected value comparison unit 52, and the expected value comparison unit 52 stores the determination result in the analysis memory 58.
  • the phase detection unit 54 detects the first relative phase that changes from the fail state to the pass state based on the determination result stored in the analysis memory 58.
  • T2 may be a value larger than T1 and may be a value smaller than 1 UI.
  • the phase controller 40 sequentially changes the phase of the strobe signal at intervals of T1 in the second phase change area.
  • the phase detector 54 detects the second relative phase that changes from the pass state to the fail state based on the determination result stored in the analysis memory 58. According to the above procedure, measurement is not required in the period T2, so that the time required for timing training can be shortened.
  • the phase control unit 40 may determine the first phase change area and the second phase change area in advance. For example, the phase control unit 40 determines a phase that is different by 0.4 UI or more and 0.8 UI or less from a position assumed to be the center position of the eye opening as the first phase change area, and at the center position of the eye opening A range of 0.4 UI before and after the position assumed to be present may be defined as the phase area of T2. This eliminates the need to analyze data for each relative phase, so that the first relative phase and the second relative phase can be detected even when the time required for data analysis is T1 or more.
  • FIG. 6 shows a lead training procedure in the semiconductor test apparatus 100 according to the third embodiment.
  • the phase detection unit 54 may detect the relative phase at which the fail rate is a predetermined ratio as the first relative phase that transitions from the fail state to the pass state.
  • the phase detection unit 54 may detect the relative phase at which the fail rate is a predetermined ratio as the second relative phase that transitions from the pass state to the fail state.
  • the predetermined ratio is 50%.
  • the semiconductor test apparatus 100 may set the first relative phase to a phase obtained by averaging the relative phases when transitioning from the fail state to the pass state over a plurality of cycles.
  • the semiconductor test apparatus 100 may set the second relative phase to a phase obtained by averaging the relative phases when transitioning from the pass state to the fail state over a plurality of cycles.
  • FIG. 7 shows a configuration of a semiconductor test apparatus 100 according to the fourth embodiment.
  • the phase controller 40 may change the phase of at least one of input data and a clock supplied to the device under test 200. For example, in the light training, the relative phase may be changed by changing the delay amount of the clock instead of changing the delay amount of the data.
  • the clock output from the test unit 20 is input to the phase control unit 40.
  • the phase control unit 40 includes a delay circuit 48, and the delay circuit 48 may change the phase of the clock based on the timing signal DLY3 output from the timing control unit 30.
  • the device under test 200 may acquire data received from the semiconductor test apparatus 100 according to a clock whose phase has been changed by the delay circuit 48. Further, the device under test 200 may transmit the acquired data to the semiconductor test apparatus 100.
  • the expected value comparison unit 52 may compare the data received from the device under test 200 with the expected value, and the test unit 20 may determine pass / fail of the device under test 200 based on the comparison result.
  • FIG. 8 shows an example of a hardware configuration of a computer 1900 according to the fifth embodiment.
  • a computer 1900 according to this embodiment is connected to a CPU peripheral unit having a CPU 2000, a RAM 2020, a graphic controller 2075, and a display device 2080 that are connected to each other by a host controller 2082, and to the host controller 2082 by an input / output controller 2084.
  • Input / output unit having communication interface 2030, hard disk drive 2040, and CD-ROM drive 2060, and legacy input / output unit having ROM 2010, flexible disk drive 2050, and input / output chip 2070 connected to input / output controller 2084 With.
  • the host controller 2082 connects the RAM 2020 to the CPU 2000 and the graphic controller 2075 that access the RAM 2020 at a high transfer rate.
  • the CPU 2000 operates based on programs stored in the ROM 2010 and the RAM 2020 and controls each unit.
  • the graphic controller 2075 acquires image data generated by the CPU 2000 or the like on a frame buffer provided in the RAM 2020 and displays it on the display device 2080.
  • the graphic controller 2075 may include a frame buffer for storing image data generated by the CPU 2000 or the like.
  • the input / output controller 2084 connects the host controller 2082 to the communication interface 2030, the hard disk drive 2040, and the CD-ROM drive 2060, which are relatively high-speed input / output devices.
  • the communication interface 2030 communicates with other devices via a network.
  • the hard disk drive 2040 stores programs and data used by the CPU 2000 in the computer 1900.
  • the CD-ROM drive 2060 reads a program or data from the CD-ROM 2095 and provides it to the hard disk drive 2040 via the RAM 2020.
  • the ROM 2010, the flexible disk drive 2050, and the relatively low-speed input / output device of the input / output chip 2070 are connected to the input / output controller 2084.
  • the ROM 2010 stores a boot program that the computer 1900 executes at startup and / or a program that depends on the hardware of the computer 1900.
  • the flexible disk drive 2050 reads a program or data from the flexible disk 2090 and provides it to the hard disk drive 2040 via the RAM 2020.
  • the input / output chip 2070 connects the flexible disk drive 2050 to the input / output controller 2084 and inputs / outputs various input / output devices via, for example, a parallel port, a serial port, a keyboard port, a mouse port, and the like. Connect to controller 2084.
  • the program provided to the hard disk drive 2040 via the RAM 2020 is stored in a recording medium such as the flexible disk 2090, the CD-ROM 2095, or an IC card and provided by the user.
  • the program is read from the recording medium, installed in the hard disk drive 2040 in the computer 1900 via the RAM 2020, and executed by the CPU 2000.
  • a program that is installed in the computer 1900 and causes the computer 1900 to function as the semiconductor test apparatus 100 causes the computer 1900 to sequentially change the input / output data of the device under test 200 and the relative phase of a predetermined strobe signal in one predetermined direction.
  • a phase control module, an expected value comparison module that determines whether or not a value obtained by sampling input / output data using a strobe signal matches a predetermined expected value, and a predetermined number of determination results in each relative phase A first relative phase in which a predetermined number of determination results transition to a pass state in which all of the determination results match and a second relative phase in which a transition from the pass state to the fail state is detected from at least one of the failure states indicating mismatch
  • Phase detector module and phase detector A device under test using a phase adjustment module that adjusts the phase of a test signal supplied to the device under test based on the relative phase of 1 and the second relative phase, and a test signal whose phase is adjusted by the phase adjustment unit And a test module for testing.
  • phase control unit 40 the expected value comparison unit 52, which are specific means in which the software and the various hardware resources described above cooperate with each other, It functions as the phase detection unit 54, the phase adjustment unit 56, and the test unit 20.
  • the calculation or processing of the information according to the purpose of use of the computer 1900 in the present embodiment is realized, so that a specific semiconductor test apparatus 100 according to the purpose of use is constructed.
  • the CPU 2000 executes a communication program loaded on the RAM 2020 and executes a communication interface based on the processing content described in the communication program.
  • a communication process is instructed to 2030.
  • the communication interface 2030 reads transmission data stored in a transmission buffer area or the like provided on a storage device such as the RAM 2020, the hard disk drive 2040, the flexible disk 2090, or the CD-ROM 2095, and sends it to the network.
  • the reception data transmitted or received from the network is written into a reception buffer area or the like provided on the storage device.
  • the communication interface 2030 may transfer transmission / reception data to / from the storage device by a DMA (direct memory access) method. Instead, the CPU 2000 transfers the storage device or the communication interface 2030 as a transfer source.
  • the transmission / reception data may be transferred by reading the data from the data and writing the data to the communication interface 2030 or the storage device of the transfer destination.
  • the CPU 2000 is all or necessary from among files or databases stored in an external storage device such as a hard disk drive 2040, a CD-ROM drive 2060 (CD-ROM 2095), and a flexible disk drive 2050 (flexible disk 2090). This portion is read into the RAM 2020 by DMA transfer or the like, and various processes are performed on the data on the RAM 2020. Then, CPU 2000 writes the processed data back to the external storage device by DMA transfer or the like.
  • an external storage device such as a hard disk drive 2040, a CD-ROM drive 2060 (CD-ROM 2095), and a flexible disk drive 2050 (flexible disk 2090).
  • the RAM 2020 and the external storage device are collectively referred to as a memory, a storage unit, or a storage device.
  • Various types of information such as various programs, data, tables, and databases in the present embodiment are stored on such a storage device and are subjected to information processing.
  • the CPU 2000 can also store a part of the RAM 2020 in the cache memory and perform reading and writing on the cache memory. Even in such a form, the cache memory bears a part of the function of the RAM 2020. Therefore, in the present embodiment, the cache memory is also included in the RAM 2020, the memory, and / or the storage device unless otherwise indicated. To do.
  • the CPU 2000 performs various operations, such as various operations, information processing, condition determination, information search / replacement, etc., described in the present embodiment, specified for the data read from the RAM 2020 by the instruction sequence of the program. Is written back to the RAM 2020. For example, when performing the condition determination, the CPU 2000 determines whether the various variables shown in the present embodiment satisfy the conditions such as large, small, above, below, equal, etc., compared to other variables or constants. When the condition is satisfied (or not satisfied), the program branches to a different instruction sequence or calls a subroutine.
  • the CPU 2000 can search for information stored in a file or database in the storage device. For example, in the case where a plurality of entries in which the attribute value of the second attribute is associated with the attribute value of the first attribute are stored in the storage device, the CPU 2000 displays the plurality of entries stored in the storage device. The entry that matches the condition in which the attribute value of the first attribute is specified is retrieved, and the attribute value of the second attribute that is stored in the entry is read, thereby associating with the first attribute that satisfies the predetermined condition The attribute value of the specified second attribute can be obtained.
  • the program or module shown above may be stored in an external recording medium.
  • an optical recording medium such as DVD or CD
  • a magneto-optical recording medium such as MO
  • a tape medium such as an IC card, and the like
  • a storage device such as a hard disk or RAM provided in a server system connected to a dedicated communication network or the Internet may be used as a recording medium, and the program may be provided to the computer 1900 via the network.
  • the relative phase of the data and the strobe is sequentially changed in one direction, and the data transmitted / received between the semiconductor test apparatus 100 and the device under test 200 is compared with the expected value.
  • the phase for starting the change of the relative phase is set to a phase that is assumed that the received data and the expected value do not match, there is an effect that both ends of the eye opening can be detected at higher speed.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

L'invention concerne un équipement de test comportant une unité de commande de phase servant à modifier séquentiellement les phases relatives des données d’entrée / sortie d’un dispositif en cours de test et d'un signal d’échantillonnage prédéterminé dans une direction unique prédéterminée ; une unité de comparaison de valeurs prévues servant à déterminer un nombre prédéterminé de fois à chaque phase relative si une valeur obtenue en échantillonnant les données d’entrée / sortie à l’aide du signal d’échantillonnage correspond ou non à une valeur prévue prédéterminée ; une unité de détection de phase servant à détecter une première phase relative où un état d’échec évolue vers un état de validation et une deuxième phase relative où l’état de validation évolue vers l’état d’échec, l’état d’échec indiquant qu’au moins un des résultats de détermination du nombre prédéterminé de fois présente un désaccord et l’état de validation indiquant que tous les résultats de détermination du nombre prédéterminé de fois présentent une concordance ; une unité d’ajustement de phase servant à ajuster, sur la base des première et deuxième phases relatives détectées par l’unité de détection de phase, la phase d’un signal de test appliqué au dispositif en cours de test ; et une unité de test servant à tester le dispositif en cours de test à l’aide du signal de test dont la phase a été ajustée par l’unité d’ajustement de phase. Il en résulte une réduction du temps nécessaire pour l’apprentissage du minutage.
PCT/JP2008/003395 2008-11-19 2008-11-19 Équipement de test, procédé de test et programme WO2010058441A1 (fr)

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KR1020117008127A KR101221080B1 (ko) 2008-11-19 2008-11-19 시험 장치, 시험 방법, 및 프로그램
PCT/JP2008/003395 WO2010058441A1 (fr) 2008-11-19 2008-11-19 Équipement de test, procédé de test et programme
JP2010539052A JPWO2010058441A1 (ja) 2008-11-19 2008-11-19 試験装置、試験方法、および、プログラム
TW098138993A TW201028707A (en) 2008-11-19 2009-11-17 Test device, test method and recording medium
US13/084,561 US20120123726A1 (en) 2008-11-19 2011-04-12 Test apparatus, test method, and storage medium

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US8625222B2 (en) * 2012-02-03 2014-01-07 Lsi Corporation Storage device having calibration circuitry providing programmable phase update values
KR102059467B1 (ko) 2013-06-28 2019-12-27 에스케이하이닉스 주식회사 반도체 장치 및 이를 포함하는 반도체 시스템
KR102299380B1 (ko) * 2014-12-19 2021-09-08 에스케이하이닉스 주식회사 반도체 장치 및 그의 구동방법
CN115291090B (zh) * 2022-10-09 2023-01-31 苏州华兴源创科技股份有限公司 芯片测试机信号延迟测量方法、装置及计算机设备

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TW201028707A (en) 2010-08-01
KR101221080B1 (ko) 2013-01-11

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