WO2010050283A1 - Cellules de mémoire et dispositif de mémorisation associatif utilisant celles-ci - Google Patents

Cellules de mémoire et dispositif de mémorisation associatif utilisant celles-ci Download PDF

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WO2010050283A1
WO2010050283A1 PCT/JP2009/063789 JP2009063789W WO2010050283A1 WO 2010050283 A1 WO2010050283 A1 WO 2010050283A1 JP 2009063789 W JP2009063789 W JP 2009063789W WO 2010050283 A1 WO2010050283 A1 WO 2010050283A1
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node
source
search
read
drain connected
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PCT/JP2009/063789
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English (en)
Japanese (ja)
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久忠 宮武
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インターナショナル・ビジネス・マシーンズ・コーポレーション
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Publication of WO2010050283A1 publication Critical patent/WO2010050283A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements

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  • the present invention relates to a memory cell used in an associative memory device that searches whether or not the same data as input data is stored, and more specifically, CAM (Content-Addressable Memory), cache memory, TLB (Translation -aside (buffer), etc.
  • CAM Content-Addressable Memory
  • TLB Translation -aside (buffer)
  • CAM is a semiconductor memory device that can search all addresses at the same time and read the address storing the same data as the input data or the data associated with the data.
  • FIG. 16 is a circuit diagram showing a memory cell and its periphery in a conventional static CAM.
  • the memory cell 1 includes cross-coupled CMOS (Complimentary Metal Oxide Semiconductor) inverters 14 and 16 and access transistors TNA0 and TNA1, as well as SRAM (Static Random Access Memory) memory cells.
  • Consists of The CMOS inverter 14 includes a load transistor TP0 composed of a p-channel MOS transistor and a drive transistor TN0 composed of an n-channel MOS transistor.
  • the CMOS inverter 16 includes a load transistor TP1 made of a p-channel MOS transistor and a drive transistor TN1 made of an n-channel MOS transistor.
  • the gate of access transistor TNA0 is connected to word line WL, while the source / drain (when the potential of read / write bit line BLTRW is lower than the potential of storage node SNT, the potential of source / read / write bit line BLTRW is The drain is connected to the read / write bit line BLTRW when it is higher than the potential of the storage node SNT, and the other source / drain (the source when the potential of the storage node SNT is lower than the potential of the read / write bit line BLTRW) When the potential of storage node SNT is higher than the potential of read / write combined bit line BLTRW, the drain) is connected to storage node SNT.
  • Access transistor TNA1 has its gate connected to word line WL, while source / drain (when the potential of read / write bit line BLCRW is lower than the potential of storage node SNC, the potential of source / read / write bit line BLCRW is The drain is connected to the read / write bit line BLCRW when it is higher than the potential of the storage node SNC, and the other source / drain (the source when the potential of the storage node SNC is lower than the read / write bit line BLCRW) When the potential of storage node SNC is higher than the potential of read / write bit line BLCRW, the drain) is connected to storage node SNC.
  • CAM often does not need to read and write data at the same time, so bit lines BLTRW and BLCRW are shared for reading and writing.
  • the memory cell 1 further includes a search comparison circuit 2 that compares data input from the outside via the bit lines BLTS and BLCS with data stored in the memory cell 1.
  • the search comparison circuit 2 includes a comparison transistor TNC0 composed of an n-channel MOS transistor, a comparison transistor TNC1 composed of an n-channel MOS transistor, and a match transistor TNM composed of an n-channel MOS transistor.
  • the gate of the comparison transistor TNC0 is connected to the storage node SNC, one source / drain is connected to the search dedicated bit line BLTS, and the other source / drain is connected to the common match node MN.
  • the gate of the comparison transistor TNC1 is connected to the storage node SNT, one source / drain is connected to the search dedicated bit line BLCS, and the other source / drain is connected to the common match node MN.
  • the gate of the match transistor TNM is connected to the common match node MN, the source is grounded, and the drain is connected to the search match line ML.
  • FIG. 17 is a circuit diagram showing another example of a comparison circuit for search in a conventional CAM.
  • the search comparison circuit 3 is composed of comparison transistors TNC0 to TNC3 made of n-channel MOS transistors.
  • the current drive capability of the load transistors TP0 and TP1, the drive transistors TN0 and TN1, and the access transistors TNA0 and TNA1 (which is determined by the channel width W and the channel length L) is read and written. It is determined in consideration of the stability of data in each of reading and holding, the speed of data inversion at the time of writing, the driving condition of the bit line at the time of reading, and the like.
  • comparison transistors TNC0 to TNC3 only pass the charges of the search match line ML and the common match node MN, and are not related to draw current from the other transistors TP0, TP1, TN0, TN1, TNA0, and TNA1, so that the memory It is not greatly related to cell operation or data retention stability.
  • Patent Document 1 discloses a CAM that achieves high speed and low power consumption.
  • the CAM includes a word match line, a plurality of associative memory cells connected in parallel to the word match line, a charging circuit for charging the word match line, and a voltage provided between the charging circuit and the word match line. And a control device.
  • this publication does not disclose the problem of the present invention and the solution thereof.
  • Patent Document 2 discloses a CAM that enables high-speed comparison operation, low power consumption, and avoidance of charge sharing.
  • the CAM includes N data holding circuits for storing data for each bit, N comparison circuits for comparing N bit data and N bit input data in the data holding circuit in bit units, and each comparison circuit.
  • N wired-or logic circuits that output the comparison results on one match line, and N-bit data and N-bit input in the data holding circuit are input according to the potential on the match line after the comparison operation by each comparison circuit.
  • each wired OR logic circuit is set to an inactive state before a comparison operation by each comparison circuit.
  • this publication also does not disclose the problem of the present invention and the solution thereof.
  • JP 2000-132978 A Japanese Patent Laid-Open No. 11-260067
  • An object of the present invention is to provide a memory cell configured with as few transistors as possible and capable of ensuring the stability of data reading, writing and holding operations, and an associative memory device including the same. It is.
  • a memory cell according to the present invention is used in an associative memory device that searches whether or not the same data as input data is stored, and includes first and second inverters, first and second access transistors, First and second comparison switching elements and a read switching element are provided.
  • the first inverter has an input node connected to the first storage node and an output node connected to the second storage node.
  • the second inverter has an input node connected to the second storage node and an output node connected to the first storage node.
  • the first access transistor includes a gate connected to the write word line, one source / drain connected to the first write bit line, and the other source / drain connected to the first storage node. And have.
  • the second access transistor has a gate connected to the write word line, one source / drain connected to the second write bit line, and the other source / drain connected to the second storage node. And have.
  • the first comparison switching element is connected between the first search / read bit line and the common match node, and is turned on or off according to the potential of one of the first and second storage nodes.
  • the second comparison switching element is connected between the second search / read bit line and the common match node, and is turned on or off according to the other potential of the first and second storage nodes.
  • the read switching element is connected between the common match node and a predetermined potential node, and is turned on or off according to the potential of the read word line.
  • An associative memory device includes the memory cell.
  • the present invention it is possible to configure the memory cell with as few transistors as possible, and to ensure the stability of data reading, writing and holding operations.
  • the number of memory cell elements is small and the occupied area is small.
  • the element size of the memory cell can be optimized independently for each of the read operation and the write operation, the element size can be reduced, and as a result, the area occupied by the memory cell is further reduced. For the same reason, the operation can be speeded up.
  • the precharge level of the bit line can be set to the high level or the low level. Therefore, the degree of freedom in design is high.
  • the precharge level of the bit line can be set to the high level or the low level also by changing the element to be used in the search operation. Combined with the degree of freedom of the bit line precharge level of the read operation, the degree of freedom in designing the memory device is extremely large.
  • the bit line is naturally shared for reading and searching because of the structure of the memory cell.
  • the access transistor and the transistor of the comparison circuit for searching are bit lines.
  • the parasitic capacitance of the bit line increases. For this reason, the operation speed becomes slow and the power consumption increases.
  • the parasitic capacitance is half or less than the conventional one, the operation is fast, and the power consumption is small.
  • FIG. 1 is a circuit diagram showing a configuration of a CAM memory cell and its periphery according to a first embodiment of the present invention.
  • FIG. 6 is a circuit diagram showing a configuration of a CAM memory cell and its periphery according to a second embodiment of the present invention.
  • FIG. 5 is a circuit diagram showing a configuration of a CAM memory cell and its periphery according to a third embodiment of the present invention.
  • FIG. 10 is a circuit diagram showing a configuration of a CAM memory cell and its periphery according to a fourth embodiment of the present invention.
  • FIG. 1 is a circuit diagram showing a configuration of a CAM memory cell and its periphery according to a first embodiment of the present invention.
  • FIG. 6 is a circuit diagram showing a configuration of a CAM memory cell and its periphery according to a second embodiment of the present invention.
  • FIG. 5 is a circuit diagram showing a configuration of a CAM memory cell and its periphery according
  • FIG. 10 is a circuit diagram showing a configuration of a CAM memory cell and its periphery according to a fifth embodiment of the present invention.
  • FIG. 10 is a circuit diagram showing a configuration of a CAM memory cell and its periphery according to a sixth embodiment of the present invention. It is a circuit diagram which shows the structure of the memory cell for CAM by the 7th Embodiment of this invention, and its periphery. It is a circuit diagram which shows the structure of the memory cell for CAM by the 8th Embodiment of this invention, and its periphery. It is a circuit diagram which shows the structure of the memory cell for CAM by the 9th Embodiment of this invention, and its periphery.
  • FIG. 17 is a circuit diagram showing a configuration of a conventional CAM memory cell different from the example shown in FIG. 16 and its periphery.
  • CAM 8 includes N (natural number) memory cells 10, a search match line ML, a match line precharge circuit 11, and a word. And a sense circuit 13.
  • Each memory cell 10 stores 1-bit data. The configuration of the memory cell 10 will be described later.
  • the match line precharge circuit 11 precharges the search match line ML to a high level (power supply potential VDD) in response to the precharge signal MLPC. When the N-bit data supplied from the outside and the N-bit data stored in the memory cell 10 all match, the search match line ML is not discharged and maintains a high level.
  • the search match line ML is discharged and low level (ground potential GND). become. Details will be described later.
  • the sense circuit 13 detects and amplifies the potential of the search match line ML and outputs a determination signal HIT indicating data match or mismatch.
  • CAM 8 further includes write bit lines BLTW and BLCW, write word line WWL, search / read combined bit lines BLTSR and BLCSR, read word line RWL, and search match line.
  • ML and precharge circuits 15, 17, 19, and 21 are provided.
  • the write word line WWL is driven to a high level during data writing.
  • Read word line RWL is driven to a high level during data read.
  • the search match line ML is precharged to a high level during data search.
  • the precharge circuits 15 and 17 precharge the write bit lines BLTW and BLCW to high level, respectively, at the time of data writing.
  • the precharge circuits 19 and 21 precharge the search / read combined bit lines BLTSR and BLCSR to a low level at the time of data search, and precharge the search / read combined bit lines BLTSR and BLCSR to a high level at the time of data read, respectively.
  • Memory cell 10 includes a latch circuit 12 that holds 1-bit data, and access transistors TNWA0 and TNWA1 that are n-channel MOS transistors.
  • Latch circuit 12 includes cross-coupled CMOS inverters 14 and 16.
  • Input node 18 of CMOS inverter 14 is connected to storage node SNC, and output node 20 is connected to storage node SNT.
  • Input node 22 of CMOS inverter 16 is connected to storage node SNT, and output node 24 is connected to storage node SNC.
  • the CMOS inverter 14 includes a load transistor TP0 composed of a p-channel MOS transistor and a drive transistor TN0 composed of an n-channel MOS transistor.
  • Load transistor TP 0 has a gate connected to input node 18, a source connected to power supply 26, and a drain connected to output node 20.
  • the gate of the driving transistor TN0 is connected to the input node 18, the source is connected to the ground 28, and the drain is connected to the output node 20.
  • the CMOS inverter 16 includes a load transistor TP1 made of a p-channel MOS transistor and a drive transistor TN1 made of an n-channel MOS transistor.
  • Load transistor TP 1 has a gate connected to input node 22, a source connected to power supply 26, and a drain connected to output node 24.
  • the gate of the driving transistor TN1 is connected to the input node 22, the source is connected to the ground 28, and the drain is connected to the output node 24.
  • the gate of the access transistor TNWA0 is connected to the write word line WWL, one source / drain is connected to the write bit line BLTW, and the other source / drain is connected to the storage node SNT.
  • Access transistor TNWA1 has a gate connected to write word line WWL, one source / drain connected to write bit line BLCW, and the other source / drain connected to storage node SNC.
  • the memory cell 10 further includes a search comparison circuit 30 that compares the input data provided via the bit lines BLTSR and BLCSR with the data stored in the latch circuit 12.
  • Search comparison circuit 30 includes comparison transistors TNC0 and TNC1 made of n-channel MOS transistors, and a match transistor TNM made of n-channel MOS transistors.
  • the gate of the comparison transistor TNC0 is connected to the storage node SNC, one source / drain is connected to the search / read bit line BLTSR, and the other source / drain is connected to the common match node MN.
  • the gate of comparison transistor TNC1 is connected to storage node SNT, one source / drain is connected to search / read bit line BLCSR, and the other source / drain is connected to common match node MN.
  • the gate of the match transistor TNM is connected to the common match node MN, the source is connected to the ground 28, and the drain is connected to the search match line ML.
  • Memory cell 10 further includes a read transistor TNRA composed of an n-channel MOS transistor.
  • Read transistor TNRA has its gate connected to read word line RWL, its source connected to ground 28, and its drain connected to common match node MN.
  • the difference from the prior art shown in FIG. 16 is that a read transistor TNRA is added.
  • the bit lines BLTRW and BLCRW are used for both reading and writing, whereas in the present embodiment, the bit lines BLTW and BLCW are dedicated for writing.
  • the bit lines BLTS and BLCS are exclusively used for searching, whereas in the present embodiment, the bit lines BLTSR and BLCSR are used for both searching and reading. Therefore, the comparison transistors TNC0 and TNC1 are exclusively used for searching in the prior art, but in this embodiment are used for both searching and reading. That is, in this embodiment, the read port and the write port are separated, and the search port and the read port are merged.
  • the precharge circuits 15 and 17 precharge both the write bit lines BLTW and BLCW to a high level. In this state, one of the write bit lines BLTW and BLCW is pulled down to a low level according to the data to be written, and the write word line WWL is driven to a high level. As a result, the access transistors TNWA0 and TNWA1 are turned on, and data is written to the latch circuit 12.
  • a write data driver (not shown) for driving the write bit lines BLTW and BLCW is connected to the load transistors TP0 and TP1 via the access transistors TNWA0 and TNWA1.
  • one storage node SNT or SNC must be changed from high level to low level, and the other storage node SNC or SNT must be changed from low level to high level. Therefore, in order to perform a stable write operation, it is preferable to design the access transistors TNWA0 and TNWA1 to be sufficiently larger than the load transistors TP0 and TP1. However, it is preferable not to design the drive transistors TN0 and TN1 to be too large.
  • the match line precharge circuit 11 shown in FIG. 1 precharges the search match line ML to a high level, While being lightly fixed (held at a constant potential by a high resistance), the precharge circuits 19 and 21 precharge the search / read bit lines BLTSR and BLCSR to a low level.
  • the comparison transistor TNC0 or TNC1 since the comparison transistor TNC0 or TNC1 is turned on in response to the high-level storage node SNT or SNC, the common match node MN becomes low level. Therefore, the match transistor TNM is off.
  • the common match node MN is at the low level in the memory cell 10 in which the data to be searched matches the stored data.
  • the common match node MN rises toward high level in the memory cell 10 that does not match. Therefore, in the memory cell 10 that does not match the data, the match transistor TNM is turned on, and the search match line ML becomes low level, indicating a data mismatch.
  • the comparison transistors TNC0 and TNC1 only need to have a size sufficient to cause the potential of the common match node MN to follow the potential of the search / read bit lines BLTSR and BLCSR sufficiently early.
  • the match transistor TNM may have a size (W / L) that can drive the search match line ML having a predetermined length in a predetermined time.
  • the precharge circuits 19 and 21 precharge the search / read bit lines BLTSR and BLCSR to a high level.
  • the search / read-use bit lines BLTSR and BLCSR may be in a floating state, or may be connected to the power supply 26 through a bit line load element (for example, a pull-up resistor).
  • the precharged search / read bit lines BLTSR and BLCSR are at the same potential. In this state, when the read word line RWL becomes high level, the read transistor TNRA is turned on, and the search / read bit line BLTSR or BLCSR becomes low level according to the data stored in the memory cell 10.
  • the search / read combined bit line BLCSR is at a low level
  • the search / read combined bit line BLTSR is at a low level
  • the search / read combined bit line BLTSR is at a low level.
  • the search / read combined bit lines BLTSR and BLCSR are in a floating state
  • the search / read combined bit lines BLTSR and BLCSR are substantially lowered to the ground potential GND.
  • the search / read combined bit lines BLTSR and BLCSR are connected to the power source 26 through the bit line load element
  • the search / read combined bit lines BLTSR and BLCSR are powered by the resistance of the bit line load element and the ON resistance of the transistors TNC1 and TNRA.
  • the potential VDD is lowered to a divided potential.
  • the read data is amplified by a known sense circuit (not shown), converted to a high or low level used in the logic circuit, and finally output to the outside of the CAM 8.
  • This memory cell 10 outputs a differential signal.
  • the sense circuit is constituted by a single-ended circuit, only one of the search / read bit lines BLTSR or BLCSR may be used for reading.
  • the comparison transistors TNC0 and TNC1 and the read transistor TNRA may be of a size sufficient to pull the search / read bit lines BLTSR and BLCSR to a predetermined potential at a predetermined speed.
  • the size required for the search operation is compared with the size required for the read operation, and the larger size may be selected. Then, according to the size, the size of the read transistor TNRA may be determined to be optimal for the read operation as a whole.
  • the drive transistors TN0 and TN1 are not so large for the write operation.
  • the drive transistors TN0 and TN1 are large. This is because the bit lines BLTRW and BLCRW must be pulled down as strongly as possible in the read operation.
  • the latch circuit 12 must hold data against the bit lines BLTRW and BLCRW that are precharged to a high level or the bit lines BLTRW and BLCRW connected to the power supply via the bit line load element. Because it will not be.
  • the driving transistors TN0 and TN1 are not directly involved in the reading operation, it is not necessary to consider the reading operation when determining the sizes of the driving transistors TN0 and TN1. Therefore, in recent miniaturized and low-voltage semiconductor technologies, not only the degree of design freedom is increased, but also the possibility of design can be widely secured.
  • the stability during data retention is determined by noise factors such as soft errors caused by radiation incident on the CAM 8 from the load transistors TP0 and TP1, the drive transistors TN0 and TN1, and the outside.
  • noise factors such as soft errors caused by radiation incident on the CAM 8 from the load transistors TP0 and TP1, the drive transistors TN0 and TN1, and the outside.
  • it is preferable that all of the load transistors TP0 and TP1 and the drive transistors TN0 and TN1 are large.
  • the transistors TP0, TP1, TN0, and TN1 are made larger, the current consumption due to the subthreshold current cannot be ignored, so it is necessary to make the size appropriate according to the design requirement and the noise factor to be noticed. For example, it is necessary to secure the current supply capability so that the critical charge amount of soft error (the charge amount necessary for reversing the retained data) does not become small.
  • the gate capacitances of the comparison transistors TNC0 and TNC1 are added as parasitic capacitances to the storage nodes SNT and SNC, the critical charge amount of the soft error is increased. Soft errors are unlikely to occur compared to SRAM memory cells. Therefore, even if the transistors TP0, TP1, TN0, and TN1 are small, charges sufficient to hold data can be supplied to the storage nodes SNT and SNC.
  • the transistor size may be determined as follows. First, considering the stability during data retention, the size of the load transistors TP0 and TP1 having a weaker current driving capability per unit size is determined. Accordingly, the sizes of the drive transistors TN0 and TN1 and the access transistors TNWA0 and TNWA1 are determined in consideration of the write operation. At this time, as described above, in the conventional memory cell, it is necessary to consider the speed of the read operation, the data retention characteristic at the time of reading, and the data retention characteristic of the non-selected cell at the time of writing, as described above. On the other hand, in the memory cell 10 according to the present embodiment, it is not necessary to consider the write operation and the read operation at the same time.
  • the sizes of the comparison transistors TNC0 and TNC1 are determined in consideration of the search operation and the read operation, and the size of the read transistor TNRA is determined in consideration of the read operation. According to this determination method, restrictions (conditions required for each transistor for reading, writing, and holding data) resulting from miniaturization of elements and lowering of voltage are significantly less than those of conventional memory cells. can do. As a result, the memory cell 10 that sufficiently satisfies all of the write, read and search operations and the data retention characteristics can be configured with a small area.
  • the write bit lines BLTW and BLCW and the search / read bit lines BLTSR and BLCSR are provided independently of each other. However, as shown in FIG. It may be shared by BLT and BLC. That is, in the second embodiment, the bit line BLT is connected to the source / drain of the access transistor TNWA0 and the comparison transistor TNC0, and the bit line BLC is connected to the source / drain of the access transistor TNWA1 and the comparison transistor TNC1.
  • the second embodiment cannot read and write simultaneously, but can halve the total number of necessary bit lines.
  • the comparison transistors TNC0 and TNC1 are source followers, when the potentials of the search / read bit lines BLTSR and BLCSR are high, they are not directly transmitted to the common match node MN. It drops by the threshold voltage of TNC1. Therefore, as shown in FIG. 4, the comparison transistors TNC0 and TNC1 in the first embodiment may be replaced with CMOS transmission gates 32 and.
  • the CMOS transmission gate 32 includes an n-channel MOS transistor TNC0 and a p-channel MOS transistor TPC0.
  • Transistor TNC0 has its gate connected to storage node SNC, one source / drain connected to search / read bit line BLTSR, and the other source / drain connected to common match node MN.
  • Transistor TPC0 has its gate connected to storage node SNT, one source / drain connected to search / read bit line BLTSR, and the other source / drain connected to common match node MN.
  • the CMOS transmission gate 34 includes an n-channel MOS transistor TNC1 and a p-channel MOS transistor TPC1.
  • Transistor TNC1 has its gate connected to storage node SNT, one source / drain connected to search / read bit line BLCSR, and the other source / drain connected to common match node MN.
  • Transistor TPC1 has its gate connected to storage node SNC, one source / drain connected to search / read bit line BLCSR, and the other source / drain connected to common match node MN.
  • the potentials of the search / read combined bit lines BLTSR and BLCSR are directly transmitted to the common match node MN, so that the search and read operations can be speeded up.
  • the total number of necessary transistors is increased as compared with the first embodiment, the sizes of the transistors TNC0, TPC0, TNC1, and TPC1 can be reduced.
  • comparison transistors TNC0 and TNC1 in the second embodiment may be replaced with CMOS transmission gates 32 and 34, as shown in FIG.
  • the precharge level of the search / read bit lines BLTSR and BLCSR is at a low level during the search operation and is at a high level during the read operation.
  • the precharge circuits 36 and 37 precharge the search / read bit lines BLTSR and BLCSR at a low level during both the search operation and the read operation.
  • read transistor TNRA in the above embodiment is an n-channel MOS transistor
  • read transistor TPRA in this embodiment is a p-channel MOS transistor.
  • the source of the read transistor TPRA is connected to the power supply 26.
  • Read word line RWL is at a low level during a read operation, and is maintained at a high level otherwise.
  • the read transistor TPRA is turned on during the read operation, and the search / read bit line BLTSR or BLCSR is set to the high level according to the data stored in the memory cell 10.
  • the read data has a polarity opposite to that at the time of writing, but the polarity may be reversed before it is output from the CAM 8.
  • the bit line precharge level during the read operation can be changed by dividing the read port and the write port and using the comparison transistors TNC0 and TNC1 not only in the search operation but also in the read operation. It is only possible to achieve this. Moreover, this can be realized with a minimum number of transistors.
  • the load transistors TP0 and TP1 are p-channel MOS transistors, so that the driving force is an n-channel MOS transistor.
  • the precharge level of the bit line has three reasons: it is weaker than the drive transistors TN0 and TN1, it is necessary to achieve both data retention and write operation during read operation, and the memory cell needs to be made small. There is no choice but to make it a high level.
  • comparison transistors TNC0 and TNC1 in the fifth embodiment may be replaced with CMOS transmission gates 32 and.
  • the match transistor TNM is composed of an n-channel MOS transistor
  • the match transistor TPM is composed of a p-channel MOS transistor.
  • the source of the match transistor TPM is connected to the power supply 26.
  • the comparison transistors TNC0 and TNC1 are n-channel MOS transistors
  • the comparison transistors TPC0 and TPC1 are p-channel MOS transistors.
  • the precharge circuits 36 and 37 precharge the search / read bit lines BLTSR and BLCSR at a low level both in the search operation and in the read operation.
  • the precharge circuits 38 and 39 precharge the search / read bit lines BLTSR and BLCSR to a high level during a search operation and precharge to a low level during a read operation. In this case, since the read data has the same polarity as when it was written, it is not necessary to invert the polarity before it is output from the CAM 8.
  • the search match line ML is precharged to a low level during the search operation. Therefore, the search match line ML remains at the low level when the data matches, but becomes the high level when the data does not match.
  • the comparison transistors TPC0 and TPC1 in the seventh embodiment may be replaced with CMOS transmission gates 32 and 34 as shown in FIG.
  • the comparison transistors TNC0 and TNC1 are n-channel MOS transistors, and the gate of the comparison transistor TNC0 is connected to the storage node SNT.
  • the gate of transistor TNC1 is connected to storage node SNC.
  • the drain of the match transistor TPM is connected to the ground 28.
  • the read transistor TNRA is the same as that in the first to fourth embodiments.
  • the precharge circuits 40 and 41 precharge the search / read bit lines BLTSR and BLCSR to a high level during both the search operation and the read operation. Therefore, the read data has the opposite polarity to that when it was written, but the polarity may be reversed before it is output from the CAM 8.
  • the search match line ML is precharged to a high level during the search operation. Therefore, the search match line ML remains at the high level when the data matches, but becomes the low level when the data does not match. However, even when the data do not match, the search match line ML does not fall to the ground potential GND, but remains at a potential higher than the ground potential GND by the threshold voltage of the match transistor TPM. Therefore, the sense circuit 13 shown in FIG. 1 may detect and amplify the potential by regarding the potential as a low level.
  • comparison transistors TNC0 and TNC1 in the ninth embodiment may be replaced with CMOS transmission gates 32 and.
  • the transistor TNM or TPM charges / discharges the search match line ML according to the potential of the common match node MN.
  • a CMOS inverter 42 may be provided.
  • the inverter 42 includes a p-channel MOS transistor TPM and an n-channel MOS transistor TNM, and its input node is connected to the common match node MN. If the data match, the common match node MN is at the low level, so the inverter 42 sets the bit match signal BM to the high level. On the other hand, if the data do not match, the common match node MN is at the high level, so the inverter 42 sets the bit match signal BM to the low level.
  • an AND circuit is provided instead of the match line ML, the match line precharge circuit 11 and the sense circuit 13 shown in FIG.
  • the bit match signal BM output from each memory cell 10 is input to this AND circuit.
  • the determination signal HIT is output from this AND circuit.
  • the write bit lines BLTW and BLCW and the search / read bit lines BLTSR and BLCSR in the eleventh embodiment are as shown in FIG. 13 as in the second embodiment shown in FIG. , All may be shared by the bit lines BLT and BLC.
  • CMOS inverter 42 may be provided.
  • the write bit lines BLTW and BLCW and the search / read bit lines BLTSR and BLCSR in the thirteenth embodiment are as shown in FIG. 15 as in the second embodiment shown in FIG. , All may be shared by the bit lines BLT and BLC.
  • the transistor TNM or TPM in the first to tenth embodiments and the CMOS inverter 42 in the eleventh to fourteenth embodiments are for amplifying and outputting the potential of the common match node MN. is there. Therefore, if a sufficient output current can be secured, the transistor TNM or TPM and the CMOS inverter 42 may be omitted and the potential of the common match node MN may be directly output.
  • the search match line ML is preliminarily driven. Unlike the first to tenth embodiments in which the bit line used for the search needs to be precharged to an appropriate potential according to the charge state, it is not necessary to precharge the bit line used for the search to a specific potential. . This has the advantage of increasing the degree of freedom in circuit design.
  • the n-channel MOS transistor and the p-channel MOS transistor may be interchanged.

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  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)

Abstract

L'invention concerne une cellule de mémoire qui peut garantir une stabilité des opérations de lecture, d'écriture et de conservation des données, et qui est constituée du plus petit nombre possible de transistors. Cette mémoire associative (CAM) comprend une cellule de mémoire (10), des lignes de bits d'écriture (BLTW, BLCW), une ligne de mots d'écriture (WWL), des lignes de bits de recherche/lecture (BLTSR, BLCSR), une ligne de mots de lecture (RWL), et une ligne de correspondances de recherche (ML). La cellule de mémoire (10) comprend un circuit à verrouillage (12) constitué d'inverseurs CMOS à couplage transversal (14, 16); des transistors d'accès (TNWA 0, TNWA 1); un circuit de comparateur de recherche (30) qui compare des données d'entrée à des données mémorisées dans le circuit à verrouillage (12); et un transistor de lecture (TNRA). Le transistor de lecture (TNRA) a été prévu en plus. De plus, les transistors de comparaison (TNC 0, TNC 1) sont chacun utilisés à des fins de recherche/lecture. En outre, des ports de lecture sont séparés des ports d'écriture, et des ports de recherche et des ports de lecture sont fusionnés.
PCT/JP2009/063789 2008-10-31 2009-08-04 Cellules de mémoire et dispositif de mémorisation associatif utilisant celles-ci WO2010050283A1 (fr)

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CN107564564A (zh) * 2016-06-30 2018-01-09 三星电子株式会社 存储器单元、存储器件及其电子设备
US9971394B2 (en) 2012-09-18 2018-05-15 International Business Machines Corporation Cache array with reduced power consumption
WO2023123305A1 (fr) * 2021-12-29 2023-07-06 大连理工大学 Moteur de recherche matériel par table de consultation tl-tcam amélioré

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US10366747B2 (en) * 2017-11-30 2019-07-30 Micron Technology, Inc. Comparing input data to stored data

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JPS573291A (en) * 1980-06-09 1982-01-08 Nippon Telegr & Teleph Corp <Ntt> Associative memory circuit
JPH03100997A (ja) * 1989-09-13 1991-04-25 Nec Corp 選択的連想記憶装置及びその制御方式
JPH08147986A (ja) * 1994-11-28 1996-06-07 Internatl Business Mach Corp <Ibm> 連想メモリの制御回路及び連想メモリ装置
JPH11260067A (ja) * 1998-03-10 1999-09-24 Toshiba Corp 半導体記憶装置
JP2000132978A (ja) * 1998-10-29 2000-05-12 Internatl Business Mach Corp <Ibm> 連想メモリ（ｃａｍ）

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Publication number Priority date Publication date Assignee Title
JPS573291A (en) * 1980-06-09 1982-01-08 Nippon Telegr & Teleph Corp <Ntt> Associative memory circuit
JPH03100997A (ja) * 1989-09-13 1991-04-25 Nec Corp 選択的連想記憶装置及びその制御方式
JPH08147986A (ja) * 1994-11-28 1996-06-07 Internatl Business Mach Corp <Ibm> 連想メモリの制御回路及び連想メモリ装置
JPH11260067A (ja) * 1998-03-10 1999-09-24 Toshiba Corp 半導体記憶装置
JP2000132978A (ja) * 1998-10-29 2000-05-12 Internatl Business Mach Corp <Ibm> 連想メモリ（ｃａｍ）

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9971394B2 (en) 2012-09-18 2018-05-15 International Business Machines Corporation Cache array with reduced power consumption
CN107564564A (zh) * 2016-06-30 2018-01-09 三星电子株式会社 存储器单元、存储器件及其电子设备
CN107564564B (zh) * 2016-06-30 2023-01-13 三星电子株式会社 存储器单元、存储器件及其电子设备
WO2023123305A1 (fr) * 2021-12-29 2023-07-06 大连理工大学 Moteur de recherche matériel par table de consultation tl-tcam amélioré

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