201023185 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種用於相聯記憶體裝置或内容可定址記 憶體（CAM)中的記憶體單元，該相聯記憶體裝置或該内容 可定址記憶體（CAM)用於進行搜尋以判定是否儲存有與所 輸入資料相同之資料。更具體而言，本發明係關於一種用 於CAM或相聯記憶體、快取記憶體、TLB(轉譯後備緩衝 器）或其類似物中之記憶體單元。 【先前技術】 CAM或相聯記憶體為可同時搜尋所有位址以讀出儲存有 與所輸入資料相同之資料的位址或讀出與該資料相關聯之 資料的半導體記憶體裝置。 圖16為展示相關技術靜態CAM之記憶體單元及其周邊的 電路圖。如圖16中所示，如同SRAM(靜態隨機存取記憶 體）之記憶體單元，記憶體單元1包括交叉耦接CMOS(互補 金氧半導體）反相器14及16與存取電晶體ΤΝΑ0及TNA1。 CMOS反相器14包括一由p通道MOS電晶體製成之負載電晶 體ΤΡ0及一由η通道MOS電晶體製成之驅動電晶體ΤΝ0。 CMOS反相器16包括一由ρ通道MOS電晶體製成之負載電晶 體TP1及一由η通道MOS電晶體製成之驅動電晶體TN1。存 取電晶體ΤΝΑ0之閘極耦接至字線WL，其之第一源極/汲極 (若用於讀取及寫入之位元線BLTRW之電位低於儲存節點 SNT之電位，則為源極；若用於讀取及寫入之位元線 BLTRW之電位高於儲存節點SNT之電位，貝丨J為汲極）耦接 142877.doc 201023185 至用於讀取及寫入之位元線BLTRW，且其之第二源極/汲 極（若儲存節點SNT之電位低於用於讀取及寫入之位元線 BLTRW之電位，貝1J為源極；若儲存節點SNT之電位高於用 於讀取及寫入之位元線BLTRW之電位’則為汲極）耦接至 儲存節點SNT。存取電晶體TNA1之閘極耦接至字線WL， 其之第一源極/汲極（若用於讀取及寫入之位元線BLCRW之 電位低於儲存節點SNC之電位’則為源極；若用於讀取及 寫入之位元線BLCRW之電位高於儲存節點SNC之電位，則 為汲極）耦接至用於讀取及寫入之位元線BLCRW，且其之 第二源極/汲極（若儲存節點SNC之電位低於用於讀取及寫 入之位元線BLCRW之電位’則為源極；若儲存節點SNC之 電位高於用於讀取及寫入之位元線BLCRW之電位’則為 汲極）耦接至儲存節點SNC。如同在典型SRAM中’在許多 狀況下不需要在CAM中同時執行資料讀取及資料寫入；因 此，將位元線BLTRW及BLCRW用於讀取及寫入雨者。 又，記憶體單元1包括一用於搜尋之比較電絡2 ’其用於 比較經由位元線BLTS及BLCS而自外部輸入之資料與儲存 於記億體單元1中之資料。用於搜尋之比較電絡2包括一由 η通道MOS電晶體製成之比較電晶體TNC0、〆由n通道 MOS電晶體製成之比較電晶體TNC1及一由η通道M〇S電晶 體製成之匹配電晶體TNM。比較電晶體TNC0义閉極輛接 至儲存節點SNC，其之第一源極/汲極耦接至專用於搜尋之 位元線BLTS，且其之第二源極/汲極耦接至共同匹配即點 ςΝΤ，Α 之 MN。比較電晶體TNC1之閘極耦接至儲存節黠5 〃 142877.doc 201023185 第一源極/汲極耦接至專用於搜尋之位元線BLCS，且其之 第二源極/汲極耦接至共同匹配節點MN。匹配電晶體TNM 之閘極耦接至共同匹配節點MN，其之源極耦接至接地， 且其之汲極耦接至一用於搜尋之匹配線ML。 圖17為展示相關技術CAM之用於搜尋之比較電路的另一 實例之電路圖。如圖17中所示，用於搜尋之比較電路3包 括比較電晶體TNC0至TNC3，每一比較電晶體由η通道 MOS電晶體製成。 在相關技術CAM之上文所提及的記憶體單元中，考慮到 資料讀取操作、資料寫入操作及資料保持之穩定性、在寫 入期間資料反轉之快速性、用於在讀取期間驅動位元線之 條件及其類似物來判定負載電晶體ΤΡ0及TP1、驅動電晶 體ΤΝ0及TN1以及存取電晶體ΤΝΑ0及TNA1之電流驅動能 力（由通道寬度W及通道長度L來判定）。 然而，隨著近年來電源供應器電壓減小且電晶體之閘極 電位與其臨限電壓之間的差異（通常稱為「過激勵（overdrive) 」）減小， 已難以 判定記 憶體單 元中之 電晶體 的尺寸 (W/L)使得該尺寸適合用於所有操作。此係因為關於資料 讀取之要求、關於資料寫入之要求以及關於資料保持之要 求隨電晶體而變化且在某些狀況下該等要求係矛盾的。 順便提及，比較電晶體TNC0至TNC3將用於搜尋之匹配 線ML之電荷及共同匹配節點MN之電荷傳遞穿過其自身， 且因此並不抵抗其他電晶體ΤΡ0、TP1、ΤΝ0、TN1、 ΤΝΑ0及TNA1來吸取電流。因此，該等比較電晶體對記憶 142877.doc 201023185 體單兀之操作或在資料保持期間對資料之穩定性不具有任 何顯著影響。 曰本未審查專利申請公開案第2000-132978號（專利文獻 1)揭示一種高速、低功率消耗型CAM。此CAM包括一字匹 配線 '多個並聯耦接至該字匹配線之相聯記憶體單元、用 於對字匹配線充電之一充電電路及提供於該充電電路與該 字匹配線之間的一電壓控制裝置。然而，此公開案根本未 提及本發明中所描述之問題及用於解決該問題之方法。 曰本未審查專利申請公開案第11_26〇〇67號（專利文獻2) 揭示一種可執行尚速比較運算、可降低功率消耗且可避免 電荷共用之CAM。此CAM包括用於儲存每一位元之資料 的N個資料保持電路、用於逐位元地比較資料保持電路中 之N個資料位元與所輸入之N個資料位元的N個比較電路以 及用於將由比較電路執行之比較的結果輸出至一匹配線上 的N個有線OR邏輯電路。此CAM(亦即，半導體記憶體裝 置）基於由比較電路執行之比較運算之後的某一時刻的匹 配線上之電位來判定資料保持電路中之N個資料位元是否 與所輸入之N個資料位元匹配，該CAM在比較電路執行比 較運算之前使有線OR邏輯電路處於其不活動狀態◎然 而，此公開案亦根本未提及本發明中所描述之問題及用於 解決該問題之方法。 [專利文獻U日本未審查專财請公開案第細Ο.· 號 [專利文獻2]日本未審查專利申請公開案第i i_2_7號 142877.doc 201023185 【發明内容】 待由本發明解決之問題 因此，本發明之-目標係提供-種包括最少之可能電晶 體並確保貝料讀取操作、資料寫入操作及資料保持之穩定 性的5己憶體單TL以及-種包括該記憶體單元之相聯纪惊 裝置。 心 用於解決該等問題之方法 將根據本發明之記憶體單元用於相聯記憶體袭置或内容 可定址記憶體|置中，該相聯記憶體裝置或該内容可定址 記憶體裝置用於進行搜尋以判定是否儲存有與所輸入資料 相同之資料。該記憶體單元包括第一及第二反相器、第一 及第一存取電晶體、第一及第二比較切換元件以及-用於 4取之切換TG件。第—反相器包括麵接至第一餘存節點之 一輸入節點及㈣至第二儲存節點之—輸出節點。第二反 相器包括麵接至第二儲存節點之一輸入節點及叙接至第一 儲存卽點之-輸出節點。第一存取電晶體具有麵接至用於 寫入之字線的一閘極、福接至用於寫入之第一位元線的一 第一源極/沒極及麵接至第一錯存節點之一第二源極/沒 極。第二存取電晶體具有耦接至用於寫入之字線的一閘 +輕接至用於寫入之第二位元線的一第一源極"及極以 及麵接至第二儲存節點之—第二源極/沒極。第-比較切 換凡件耗接於用於搜尋及讀取之第一位元線與共同匹配節 點之間’且根據第-儲存節點及第二儲存節點中之一者之 電位而被接通或切斷。第二比較切換元件轉接於用於搜尋 142877.doc 201023185 二！取之第二位元線與共同匹配節點之間，且根據第-儲 ’及第_儲存卽點中之另—者之電位而被接通或切201023185 VI. Description of the Invention: [Technical Field] The present invention relates to a memory unit for use in an associative memory device or a content addressable memory (CAM), the associated memory device or the content The Address Memory (CAM) is used to perform a search to determine whether or not the same material as the input data is stored. More specifically, the present invention relates to a memory unit for use in CAM or associative memory, cache memory, TLB (Translation Backup Buffer) or the like. [Prior Art] CAM or associative memory is a semiconductor memory device that can simultaneously search all addresses to read an address in which the same material as the input data is stored or to read data associated with the data. Fig. 16 is a circuit diagram showing a memory unit of the related art static CAM and its periphery. As shown in FIG. 16, like the memory unit of the SRAM (Static Random Access Memory), the memory unit 1 includes cross-coupled CMOS (complementary MOS) inverters 14 and 16 and an access transistor ΤΝΑ0 and TNA1. The CMOS inverter 14 includes a load transistor ΤΡ0 made of a p-channel MOS transistor and a driver transistor ΤΝ0 made of an n-channel MOS transistor. The CMOS inverter 16 includes a load transistor TP1 made of a p-channel MOS transistor and a drive transistor TN1 made of an n-channel MOS transistor. The gate of the access transistor ΤΝΑ0 is coupled to the word line WL, and the first source/drain thereof (if the potential of the bit line BLTRW for reading and writing is lower than the potential of the storage node SNT) Source; if the potential of the bit line BLTRW for reading and writing is higher than the potential of the storage node SNT, Bellow J is the bungee) coupling 142877.doc 201023185 to the bit for reading and writing Line BLTRW, and its second source/drain (if the potential of the storage node SNT is lower than the potential of the bit line BLTRW for reading and writing, the Bay 1J is the source; if the potential of the storage node SNT is high The potential 'B" of the bit line BLTRW for reading and writing is coupled to the storage node SNT. The gate of the access transistor TNA1 is coupled to the word line WL, and the first source/drain thereof (if the potential of the bit line BLCRW for reading and writing is lower than the potential of the storage node SNC) is a source; if the potential of the bit line BLCRW for reading and writing is higher than the potential of the storage node SNC, the drain is coupled to the bit line BLCRW for reading and writing, and The second source/drain (if the potential of the storage node SNC is lower than the potential of the bit line BLCRW for reading and writing) is the source; if the potential of the storage node SNC is higher than for reading and writing The potential of the bit line BLCRW, which is the drain of the bit line, is coupled to the storage node SNC. As in a typical SRAM, data reading and data writing are not required to be performed simultaneously in the CAM in many cases; therefore, the bit lines BLTRW and BLCRW are used to read and write to the rainer. Further, the memory unit 1 includes a comparison electric network 2' for searching for data input from the outside via the bit lines BLTS and BLCS and data stored in the unit cell 1. The comparison circuit 2 for searching includes a comparison transistor TNC0 made of an n-channel MOS transistor, a comparison transistor TNC1 made of an n-channel MOS transistor, and a transistor made of an η-channel M〇S transistor. Matching transistor TNM. The comparator transistor TNC0 is connected to the storage node SNC, and the first source/drain is coupled to the bit line BLTS dedicated to the search, and the second source/drain is coupled to the common match. That is, click ςΝΤ, Α MN. The gate of the comparator transistor TNC1 is coupled to the storage node 〃 〃 142 142 142 142 142 142 142 142 142 142 142 142 142 142 142 142 142 142 142 142 142 142 142 142 142 142 142 142 142 142 142 142 142 142 142 142 142 142 142 142 142 142 142 142 142 142 To the common matching node MN. The gate of the matching transistor TNM is coupled to the common matching node MN, the source of which is coupled to the ground, and the drain of the gate is coupled to a matching line ML for searching. Fig. 17 is a circuit diagram showing another example of a comparison circuit for searching by the related art CAM. As shown in Fig. 17, the comparison circuit 3 for searching includes comparison transistors TNC0 to TNC3, each of which is made of an n-channel MOS transistor. In the memory unit mentioned above in the related art CAM, considering the data reading operation, the data writing operation, and the stability of data retention, the rapidity of data inversion during writing, for reading The conditions of the driving bit line and the like are used to determine the current driving capability of the load transistors ΤΡ0 and TP1, the driving transistors ΤΝ0 and TN1, and the access transistors ΤΝΑ0 and TNA1 (determined by the channel width W and the channel length L) . However, as the power supply voltage has decreased in recent years and the difference between the gate potential of the transistor and its threshold voltage (commonly referred to as "overdrive") has decreased, it has been difficult to determine the memory cell. The size (W/L) of the transistor makes this size suitable for all operations. This is because the requirements for data reading, the requirements for data writing, and the requirements for data retention vary with the transistor and in some cases these requirements are contradictory. Incidentally, the comparison transistors TNC0 to TNC3 pass the charge of the matching line ML for searching and the charge of the common matching node MN through itself, and thus are not resistant to other transistors ΤΡ0, TP1, ΤΝ0, TN1, ΤΝΑ0. And TNA1 to draw current. Therefore, these comparative transistors do not have any significant effect on the operation of the memory or the stability of the data during data retention. A high-speed, low-power consumption type CAM is disclosed in Unexamined Patent Application Publication No. 2000-132978 (Patent Document 1). The CAM includes a word match line 'a plurality of associated memory cells coupled in parallel to the word match line, a charge circuit for charging the word match line, and a voltage supply between the charge circuit and the word match line A voltage control device. However, this publication does not mention at all the problems described in the present invention and the methods for solving the problems. Japanese Unexamined Patent Application Publication No. Hei No. Hei No. Hei No. Hei No. Hei No. 11-26-67 (Patent Document 2) discloses a CAM that can perform a speed comparison operation, can reduce power consumption, and can avoid charge sharing. The CAM includes N data holding circuits for storing data of each bit, N comparison circuits for bit-wisely comparing N data bits in the data holding circuit and the input N data bits. And N wired OR logic circuits for outputting the results of the comparison performed by the comparison circuit to a match line. The CAM (ie, the semiconductor memory device) determines whether the N data bits in the data holding circuit and the input N data bits are based on the potential on the matching line at a certain time after the comparison operation performed by the comparison circuit. Meta-matching, the CAM places the wired OR logic circuit in its inactive state before the comparison circuit performs the comparison operation. However, this disclosure also does not mention at all the problems described in the present invention and the method for solving the problem. [Patent Document U Japanese Unexamined Patent Application Publication No. [No. Patent Document 2] Japanese Unexamined Patent Application Publication No. ii No. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The object of the present invention is to provide a five-remembered single TL including the least possible possible crystals and ensuring the stability of the bedding reading operation, the data writing operation and the data retention, and the phase including the memory unit. Joint Jixian device. The method for solving such problems is to use the memory unit according to the present invention for associative memory or content addressable memory|centering, the associated memory device or the content addressable memory device A search is performed to determine whether or not the same material as the input data is stored. The memory unit includes first and second inverters, first and first access transistors, first and second comparison switching elements, and a switching TG for use. The first-inverter includes an input node that is interfaced to the first remaining node and (iv) to an output node of the second storage node. The second inverter includes an input node that is connected to one of the second storage nodes and an output node that is connected to the first storage node. The first access transistor has a gate that is connected to the word line for writing, a first source/nopole that is connected to the first bit line for writing, and is connected to the first One of the missing nodes is the second source/no pole. The second access transistor has a gate coupled to the word line for writing + a first source connected to the second bit line for writing and a face and a second face Storage node - second source / no pole. The first-comparison switching device is connected between the first bit line for searching and reading and the common matching node' and is turned on according to the potential of one of the first storage node and the second storage node or Cut off. The second comparison switching element is switched to use for searching 142877.doc 201023185 II! Taking the second bit line and the common matching node, and being turned on or cut according to the potential of the other of the first storage and the storage storage point
用於讀取之切換元件相接於共同匹配節點與具有預定 電位之一節WJ； ->· BB ‘· S ’且根據用於讀取之字線之電位而被接 通或切斷。 記憶體裝置包括上文所提及之記憶體 根據本發明之相聯 〇g 單7L。 優勢 藉由採用本發明， 並確保資料讀取操作 性。 5己憶體單元包括最少之可能電晶體， 、資料寫入操作及資料保持之穩定 由於將相同元件用 憶體單元之元件數目 較小。 於資料搜尋及資料讀取兩者，所以記 較小，且由記憶體單元所佔據之面積 由於§己憶體之元件之ρ 1 中之相對於讀取操作及寫入操+ 母者而獨立地最佳化，所以访笪- A 結果，由々传P 所以該等兀件之尺寸減小c 由δ己隐體早兀所佔據 m y 像之面積減小。又，出於相同w 因’操作得以加速。 仰丨J々 用於讀取之埠盥用於曾 ,^ /、用寫入之埠分開，且使用記怜體i - 中之不同電路來執行讀取摔己隐體早π ^ ^ ^ ^ 锞作及寫入刼作。因此，可使# 凡線之預充電位準為古 J使位 性得以增加。 m果，6又叶之靈活 如將在以下實施例中所見，甚至對 藉由改變待使用之开 、搜寻知作而言，可 艾付便用之兀件而使 及*踝之預充電位準為高 】42877.doc 201023185 或低位準。與用於讀取操作之位元線之預充電位準的靈活 性相組合’記憶體裝置之設計靈活性顯著增加。 在本發明中，自然地將來自記憶體單元之結構的相同位 元線用於讀取及搜尋兩者，相反，當在相關技術記憶體單 元中將相同位元線用於讀取及搜尋兩者時，存取電晶體及 用於搜尋之比較電路充當位元線上之負載。因此，位元線 之寄生電谷增加。此減小操作速度以及增加功率消耗。本 發明將寄生電容減小至相關技術中之寄生電容的一半或更 小’因此加速操作並減小功率消耗。 【實施方式】 現將參看隨附圖式來描述本發明之實施例。在此等圖式 中，相同或等效元件經指派有相同參考數字且將不予以重 複描述。 第一實施例 在圖1中，關於每一字，根據本發明之第一實施例之 括N個（自然數）記憶體單元1〇、一用於搜尋之匹 配線ML」-匹配線預充電電路u及一感測電路"。每一 。己隐體單7L10儲存一個資料位元。梢後將描述記憶體翠元 1〇之組態。匹配線預充電電路11回應於預充電信號MLPC 而將用於搜尋之匹配線肌預充電至高位準（電源供應電位 VDD)。若自外部提供之資料㈣個位元與儲存於記憶體單 W0中之資料的咖位元全部匹配，則用於搜尋之匹配線 肌保持該高位準而不被放電。另一方面，若自外部提供 之資料的N個位元與儲存於記德體單元1〇中之資料的_ 142877.doc 201023185 位元甚至一個位元都不匹配，則對用於搜尋之匹配線ML 放電使得其給出低位準（接地電位GND)。稍後將描述細 節。感測電路13感測並放大用於搜尋之匹配線ML的電 位，並輸出一指示資料匹配或資料失配之判定信號HIT。 在圖2中，CAM 8進一步包括用於寫入之位元線BLTW及 BLC W、一用於寫入之字線WWL、用於搜尋及讀取之位元 線BLTSR及BLCSR、一用於讀取之字線RWL、一用於搜尋 之匹配線ML以及預充電電路1 5、1 7、19及2 1。 將用於寫入之字線WWL驅動至高位準以用於寫入資 料。將用於讀取之字線RWL驅動至高位準以用於讀取資 料。將用於搜尋之匹配線ML預充電至高位準以用於搜尋 資料。 預充電電路1 5及1 7分別將用於寫入之位元線BLTW及 BLCW預充電至高位準以用於寫入資料。預充電電路19及 21分別將用於搜尋及讀取之位元線BLTSR及BLCSR預充電 至低位準以用於搜尋資料，且分別將用於搜尋及讀取之位 元線BLTSR及BLCSR預充電至高位準以用於讀取資料。 每一記憶體單元10包括用於保持一個資料位元之一鎖存 電路12以及存取電晶體TNWA0及TNWA1，每一存取電晶 體由η通道MOS電晶體製成。鎖存電路12包括交叉耦接 CMOS反相器14及16。CMOS反相器14之輸入節點18耦接 至儲存節點SNC，且其之輸出節點20耦接至儲存節點 SNT。CMOS反相器16之輸入節點22耦接至儲存節點 SNT，且其之輸出節點24耦接至儲存節點SNC。 142877.doc •12- 201023185 CMOS反相器14包括由p通道MOS電晶體製成之一負載電 晶體ΤΡ0及由η通道MOS電晶體製成之一驅動電晶體ΤΝ0。 負載電晶體ΤΡ0之閘極耦接至輸入節點1 8，其之源極耦接 至電源供應器26，且其之汲極耦接至輸出節點20。驅動電 晶體ΤΝ0之閘極耦接至輸入節點1 8，其之源極耦接至接地 28，且其之汲極耦接至輸出節點20。 CMOS反相器16包括一由ρ通道MOS電晶體製成之負載電 晶體TP1及一由η通道MOS電晶體製成之驅動電晶體TN1。 負載電晶體ΤΡ1之閘極耦接至輸入節點22，其之源極耦接 至電源供應器26，且其之汲極耦接至輸出節點24。驅動電 晶體ΤΝ1之閘極耦接至輸入節點22，其之源極耦接至接地 28，且其之汲極耦接至輸出節點24。 存取電晶體TNWA0之閘極耦接至用於寫入之字線 WWL。其之第一源極/汲極耦接至用於寫入之位元線 BLTW，且其之第二源極/汲極耦接至儲存節點SNT。存取 電晶體TNWA1之閘極耦接至用於寫入之字線WWL，其之 第一源極/汲極耦接至用於寫入之位元線BLCW，且其之第 二源極/汲極耦接至儲存節點SNC。 每一記憶體單元10進一步包括一用於搜尋之比較電路 30，該比較電路30用於比較經由位元線BLTSR及BLCSR所 提供之輸入資料與儲存於鎖存電路12中之資料。用於搜尋 之比較電路30包括：比較電晶體TNC0及TNC 1，每一比較 電晶體由η通道MOS電晶體製成；及匹配電晶體ΤΝΜ，其 由η通道MOS電晶體製成。比較電晶體TNC0之閘極耦接至 142877.doc 13 201023185 儲存節點SNC，且其之第一源極/汲極耦接至用於搜尋及讀 取之位元線BLTSR，且其之第二源極/汲極耦接至共同匹配 節點MN。比較電晶體TNC1之閘極耦接至儲存節點SNT， 且其之第一源極/汲極耦接至用於搜尋及讀取之位元線 BLCSR，且其之第二源極/汲極耦接至共同匹配節點MN。 匹配電晶體TNM之閘極耦接至共同匹配節點MN，其之源 極耦接至接地28，且其之汲極耦接至用於搜尋之匹配線 ML。 每一記憶體單元10進一步包括一用於讀取之電晶體 TNRA，其由η通道MOS電晶體製成。用於讀取之電晶體 TNRA的閘極耦接至用於讀取之字線RWL，其之源極耦接 至接地28，且其之汲極耦接至共同匹配節點ΜΝ。 根據此實施例之CAM 8不同於圖16中所示之相關技術實 例，因為CAM 8另外包括用於讀取之電晶體TNRA。又， 在相關技術實例中將位元線BLTRW及BLCRW用於讀取及 寫入，而在此實施例中將位元線BLTW及BLCW僅用於寫 入。又，在相關技術實例中將位元線BLTS及BLCS僅用於 搜尋，而在此實施例中將位元線BLTSR及BLCSR用於搜尋 及讀取。因此，在相關技術實例中將比較電晶體TNC0及 TNC1僅用於搜尋，而在此實施例中將此等電晶體用於搜 尋及讀取兩者。亦即，在此實施例中，將用於讀取之埠與 用於寫入之埠分開，且將用於搜尋之埠與用於讀取之埠合 併。 下文將描述CAM 8之操作。 142877.doc -14· 201023185 (1)寫入操作 為將資料寫入至記憶體單元10中，首先，預充電電路15 及17將用於寫入之位元線BLTW及BLCW兩者預充電至高 位準。自此狀態開始，根據待寫入之資料而將用於寫入之 位元線BLTW及BLCW中之一者的電位降低至低位準，且 將用於寫入之字線WWL驅動至高位準。因此，存取電晶 體TNWA0及TNWA1接通，且資料被寫入至鎖存電路12 中〇 ❹ 士 為了反轉由鎖存電路12保持之資料，用於驅動用於寫入 之位元線BLTW及BLCW的一寫入資料驅動器（圖中未繪示） 必須經由存取電晶體TNWA0及TNWA1而抵抗負載電晶體 ΤΡ0及TP1將儲存節點SNT及SNC中之一者的電位自高位準 改變至低位準，且將儲存節點SNT及SNC中之另一者的電 位自低位準改變至高位準。因此，為執行穩定之寫入操 作’較佳地，以如此之方式設計存取電晶體TNWA0及 φ TNWA1使得此等電晶體之尺寸充分大於負載電晶體ΤΡ0及 TP1。並且，亦較佳地，不將驅動電晶體ΤΝ0及TN1設計得 太大。此係因為當將用於寫入之位元線BLCW經驅動至低 位準時，驅動電晶體ΤΝ0妨礙儲存節點SNT之電位增加， 且當將位元線BLTW驅動至低位準時驅動電晶體TN1妨礙 儲存節點SNC之電位增加。 (2)搜尋操作 為搜尋儲存於記憶體單元10中之資料，首先，圖1中所 示之匹配線預充電電路11將用於搜尋之匹配線ML預充電 142877.doc 15 201023185 至高位準，並將該匹配線保持處於電浮動或稍微固定之高 位準（經由高電阻而保持於給定電位），而預充電電路19及 21將用於搜尋及讀取之位元線BLTSR及BLCSR預充電至低 位準。接著，將共同匹配節點MN置於低位準，因為根據 被置於高位準之儲存節點SNT或SNC比較電晶體TNC0或 TNC1係接通的。因此，匹配電晶體TNM係切斷的。在此 狀態下，將待搜尋之資料提供至位元線BLTSR及BLCSR。 在此狀況下，使儲存資料與待搜尋之資料匹配的記憶體單 元10之共同匹配節點MN保持處於低位準，而使儲存資料 不與待搜尋之資料匹配的記憶體單元10之共同匹配節點 MN的電位朝高位準升高。因此，在發生資料失配之記憶 體單元10中，匹配電晶體TNM接通，且用於搜尋之匹配線 ML變成低位準使得指示資料失配。 此處，較佳地，比較電晶體TNC0及TNC 1具有足夠大之 尺寸，使得共同匹配節點MN之電位充分快速地遵循用於 搜尋及讀取之位元線BLTSR及BLCSR的電位。又，較佳 地，匹配電晶體TNM具有足夠大之尺寸（W/L)，使得該匹 配電晶體可在預定時間内驅動具有預定長度之用於搜尋之 匹配線ML。 (3)讀取操作 為自記憶體單元10讀取資料，首先，預充電電路19及21 將用於搜尋及讀取之位元線BLTSR及BLCSR預充電至高位 準。預充電之後，位元線BLTSR及BLCSR可保持為浮動或 可經由位元線負載元件（例如，上拉電阻器）而耦接至電源 142877.doc -16- 201023185 供應器26。將經預充電之位元線BLTSR及BLCSR置於相同 位準下。自此狀態開始，當將用於讀取之字線RWL驅動至 高位準時，根據儲存於記憶體單元10中之資料接通用於讀 取之電晶體TNRA，且將位元線BLTSR或BLCSR下拉至低 位準。亦即，若儲存節點SNT處於高位準，則將位元線 BLCSR下拉至低位準。若儲存節點SNC處於高位準，則將 位元線BLTSR下拉至低位準。此處，關於被下拉之位元線 的低位準，在位元線BLTSR及BLCSR浮動之狀況下，將該 位元線降低至大致接地電位GND，且在位元線BLTSR及 BLCSR經由位元線負載元件而耦接至電源供應器26的狀況 下，將下拉之位元線降低至藉由電源供應器電位VDD除以 位元線負載元件之電阻以及電晶體TNC1及TNRA之接通電 阻所獲得的電位。 讀取資料由已知之感測電路（圖中未繪示）進行放大，接 著經轉換為高位準或低位準以用於邏輯電路中，且最終自 CAM 8輸出。儘管CAM單元10輸出一對差動信號，但僅可 將用於搜尋及讀取之位元線BLTSR及BLCSR中之任一者用 於讀取（藉由使用單端電路形成感測電路）。 較佳地，比較電晶體TNC0及TNC 1以及用於讀取之電晶 體TNRA具有足夠大之尺寸，從而以預定速度將用於搜尋 及讀取之位元線BLTSR及BLCSR中之一者降低至預定電 位。 由於將比較電晶體TNC0及TNC 1用於搜尋及讀取，所以 較佳地，比較搜尋操作所需之尺寸與讀取操作所需之尺寸 142877.doc • 17· 201023185 且接著選擇該等尺寸中之較大者。隨後，較佳地，根據選 定尺寸判定用於讀取之電晶體TNRA的尺寸，使得包括電 晶體TNRA與電晶體TNC0及TNC1中之一者作為一個整體 之路徑的電阻對於讀取操作而言係最佳的。 如上文所描述，對於寫入操作而言，較佳地，驅動電晶 體ΤΝ0及TN1未必如此大。然而，關於如圖16中所示之 CAM之相關技術記憶體單元，較佳地，驅動電晶體ΤΝ0及 TN1應為大的。此係因為位元線BLTRW及BLCRW中之一 者在讀取操作期間必須儘可能強有力地保持為低。此亦係 因為鎖存電路12必須抵抗預充電至高位準之位元線BLTRW 及BLCRW或經由位元線負載元件而耦接至電源供應器之 位元線BLTRW及BLCRW來保持資料。 與上文之相關技術記憶體單元相反，關於根據此實施例 之記憶體單元1 〇，在讀取操作中並未直接涉及驅動電晶體 ΤΝ0及TN1。因此，當判定驅動電晶體ΤΝ0及TN1之尺寸時 不需要考慮讀取操作。此允許不僅增加設計之靈活性而且 確保在以先進小型化及低電壓為特徵之新近半導體技術中 設計之廣泛可能性。 在資料保持期間資料之穩定性取決於負載電晶體ΤΡ0及 TP1、驅動電晶體ΤΝ0及TN1以及雜訊因數（諸如由自外部 進入CAM 8之輻射所引起的軟錯誤）。為使受雜訊影響的 程度較小，較佳地，負載電晶體ΤΡ0及TP1以及驅動電晶 體ΤΝ0及TN1應皆為大的。然而，若使電晶體ΤΡ0、TP1、 ΤΝ0及TN1更大，貝ij歸因於亞臨限電流之電流消耗變得不 142877.doc -18- 201023185 可忽略。因此，必須使此等電晶體之尺寸為根據設計要求 及待考慮之雜訊因數的適當尺寸。舉例而言，必須確保電 流供應能力使得軟錯誤之臨界電荷量（反轉經保持之資料 所必要的電荷量）未減小。 在根據此實施例之記憶體單元10中’比較電晶體11^(：〇 及TNC1之閘極電容被加至儲存節點SNT及SNc而作為寄生 電容。因此，軟錯誤之臨界電荷量增加，使得在記憶體單 φ 兀10中發生軟錯誤的可能性要小於在SRAM之典型記憶體 單元中發生軟錯誤的可能性。結果，電晶體τρ〇、τρι、 二0及TN1可將用以保持資料之足夠量的電荷供應至儲存 節點SNT及SNC(即使在此等電晶體之尺寸較小的情況 下）。 ' 自以上描述，較佳地如下判定該等電晶體之尺寸。首 先’考慮在資料保持期間資料之穩純，判定為pFET且每 單位尺寸具有較低之電流驅動能力的負載電晶體τρ〇及 Φ TP1之尺寸。因此，考慮到寫入操作來判定驅動電晶體 ΤΝ0及TN1與存取電晶體7^|八〇及1^贾八1的尺寸。此處， 在相關技術記憶體單元之狀況下，如上文所描述必須考慮 讀取操作之速度、讀取期間之資料保持特性及寫入期間未 選定單元之資料保持特性以及寫入操作自身。與此相反， 在根據此實施例之記憶體單元1〇的狀況下，無需同時考慮 寫入操作及讀取操作。考慮搜尋操作及讀取操作來判定比 較電晶體TNC0及TNC1之財且接著考慮讀取操作來判定 用於讀取之電晶體TNRA的尺寸已足夠。藉由採用此判定 142877.doc -19- 201023185 方法，可歸因於元件小型化及低電壓之限制（需要電晶體 滿足以用於讀取資料、寫入資料及保持資料的條件）與相 關技術記憶體單元中之限制相比得以大體上減少。此允許 以完全滿足關於寫入操作、讀取操作、搜尋操作及資料保 持特性之所有條件的小面積來建構記憶體單元10。 第二實施例 儘管在上文所提及之第一實施例中獨立地提供用於寫入 之位元線BLTW及BLCW與用於搜尋及讀取之位元線BLTSR 及BLCSR，但可將位元線BLT及BLC而非上文之位元線用 於所有寫入操作、搜尋操作及讀取操作，如圖3中所示。 具體而言，在第二實施例中，位元線BLT耦接至存取電晶 體TNWA0之源極/汲極及比較電晶體TNC0之源極/汲極， 且位元線BLC耦接至存取電晶體TNWA1之源極/汲極及比 較電晶體TNC 1之源極/汲極。 與在第一實施例中不同，在第二實施例中不能同時執行 讀取與寫入；然而，必要位元線之總數目減少一半。 第三實施例 在上文所提及之第一實施例中，將比較電晶體TNC0及 TNC 1用作源極隨耦器。因此，當用於搜尋及讀取之位元 線BLTSR及BLCSR之電位高時，該等電位並未如其將至共 同匹配節點MN被傳輸而是下降了比較電晶體TNC0及 TNC 1之臨限電壓。為應付此問題，如圖4中所示，可用 CMOS傳輸閘32及34來替代第一實施例中之比較電晶體 TNC0及 TNC1。 142877.doc -20· 201023185 CMOS傳輸閘32包括一 η通道MOS電晶體TNC0及一 p通道 MOS電晶體TPC0。電晶體TNC0之閘極耦接至儲存節點 SNC，其之第一源極/汲極耦接至用於搜尋及讀取之位元線 BLTSR ’且其之第·一源極/汲·極麵接至共同匹配節點MN。 電晶體TPC0之閘極耦接至儲存節點SNT，其之第一源極/ 汲極耦接至用於搜尋及讀取之位元線BLTSR，且其之第二 源極/汲極搞接至共同匹配節點MN。 ❹ CMOS傳輸閘34包括一 η通道MOS電晶體TNC1及一p通道 MOS電晶體TPC1。電晶體TNC1之閘極耦接至錯存節點 SNT，其之第一源極/汲極耦接至用於搜尋及讀取之位元線 BLCSR ’且其之第二源極/沒極耦接至共同匹配節點μν。 電晶體TPC1之閘極柄接至儲存節點SNC，其之第_源極/ 汲極耦接至用於搜尋及讀取之位元線BLCSR，且其之第二 源極/沒極輕接至共同匹配節點ΜΝ。 藉由採用第三實施例’用於搜尋及讀取之位元線BLTSR ❹ 及BLCSR之電位直接傳輸至共同匹配節點MN而無任何電 壓降落。因此，搜尋操作及讀取操作得以加速。健管必要 電晶體之數目與第一實施例中之電晶體數目相比而增加， 但可減小電晶體TNC0、TPC0、TNC1及TPC1之尺寸。 第四實施例 如圖5中所示，如同在上文所提及之第三實施例中，可 用CMOS傳輸閘32及34來替代上文所提及之第二實施例中 的比較電晶體TNC0及TNC1。 第五實施例 142877.doc -21· 201023185 在上文所提及之實施例中，用於搜尋及讀取之位元線 BLTSR及BLCSR之預充電位準對於搜尋操作而言為低位 準，且對於讀取操作而言為高位準。然而，由於預先並不 知道請求搜尋操作與讀取操作中之哪一者，所以假定請求 此等操作中之一者，需要將位元線預充電於低位準或高位 準。因此，若請求與所假定之操作不同的操作，則必須再 次執行預充電。此係高速操作之障礙，因為必須在整個定 時設計中假定最壞狀況（再次執行預充電之狀況）。 為應付此障礙，在第五實施例中，預充電電路36及37針 對搜尋操作與讀取操作兩者而將用於搜尋及讀取之位元線 BLTSR及BLCSR預充電至低位準，如圖6中所示。又，在 此實施例中用於讀取之電晶體TPRA由p通道電晶體組成， 而在上文所提及之實施例中用於讀取之電晶體TNRA由η通 道MOS電晶體組成。又，根據此實施例用於讀取之電晶體 TPRA的源極耦接至電源供應器26。在讀取操作期間用於 讀取之字線RWL被驅動至低位準，且當不請求讀取操作時 維持高位準。因此，用於讀取之電晶體TPRA針對讀取操 作而被接通，且用於搜尋及讀取之位元線BLTSR及BLCSR 中之一者根據儲存於記憶體單元1 〇中之資料而被上拉至高 位準。在此狀況下，讀取之資料具有與在資料已被寫入時 之極性相反的極性；因此，較佳地，在自CAM 8輸出資料 之前將極性反轉。 正是由於用於讀取之埠與用於寫入之埠分開且比較電晶 體TNCO及TNC 1不僅用於搜尋操作而且用於讀取操作，所 142877.doc -22· 201023185 以才可如此實施例中所示來改變用於讀取操作之位元線的 預充電位準。又，藉由最小數目之電晶體來實現此。與此 相反，關於將相同埠用於讀取及寫入兩者之相關技術記憶 體單元，除將位元線之預充電位準界定為高位準之外無其 他選擇，原因有三個：負載電晶體ΤΡ0及TP1之驅動力比 驅動電晶體ΤΝ0及TN1(其為η通道MOS電晶體）之驅動力 弱，因為負載電晶體ΤΡ0及ΤΡ1中之每一者由ρ通道MOS電 晶體製成；必須確保讀取期間之資料保持與穩定之寫入操 作；及必須使記憶體單元為小的。 第六實施例 如圖7中所示，如同在上文所提及之第三實施例中，可 用CMOS傳輸閘32及34來替代在上文所提及之第五實施例 中的比較電晶體TNC0及TNC1。 第七實施例 雖然在上文所提及之第五實施例中匹配電晶體TNM由η 通道MOS電晶體製成，但在圖8中所示之第七實施例中匹 配電晶體TPM由ρ通道MOS電晶體製成。匹配電晶體TPM 之源極耦接至電源供應器26。雖然在上文所提及之第五實 施例中比較電晶體TNC0及TNC1中之每一者由η通道MOS 電晶體製成，但在第七實施例中比較電晶體TPC0及TPC 1 中之每一者由ρ通道MOS電晶體製成。雖然在第五實施例 中預充電電路36及37針對搜尋操作及讀取操作而將用於搜 尋及讀取之位元線BLTSR及BLCSR預充電至低位準，但在 第七實施例中預充電電路38及39針對搜尋操作而將用於搜 142877.doc -23- 201023185 尋及讀取之位元線BLTSR及BLCSR預充電至高位準且針對 讀取操作而將此等位元線預充電至低位準。在此狀況下， 讀取之資料具有與在資料已被寫入時之極性相同的極性。 因此，不需要在自CAM 8輸出資料之前將極性反轉。 又，在第七實施例中針對搜尋操作而將用於搜尋之匹配 線ML預充電至低位準。因此，當資料匹配時匹配線ML保 持處於低位準；當資料不匹配時，其被上拉至高位準。 第八實施例 如圖9中所示，如同在上文所提及之第三實施例中，可 用CMOS傳輸閘32及34來替代在上文所提及之第七實施例 中的比較電晶體TPC0及TPC1。 第九實施例 在圖10中所示之第九實施例中，與在上文所提及之第七 實施例中不同，比較電晶體TNC0及TNC1中之每一者由η 通道MOS電晶體製成。又，比較電晶體TNC0之閘極耦接 至儲存節點SNT，且比較電晶體TNC1之閘極耦接至儲存節 點SNC。匹配電晶體ΤΡΜ之汲極耦接至接地28。用於讀取 之電晶體TNRA與在上文所提及之第一至第四實施例中之 電晶體TNRA相同。 又，在第九實施例中，預充電電路40及41針對搜尋操作 及讀取操作兩者而將用於搜尋及讀取之位元線BLTSR及 BLCSR預充電至高位準。因此，讀取資料具有與在資料已 被寫入時之極性相反的極性。因此，較佳地，在自CAM 8 輸出資料之前將極性反轉。 142877.doc • 24- 201023185 又，在第九實施例中，針對搜尋操作而將用於搜尋之匹 配線ML預充電至高位準。因此，當資料匹配時，匹配線 ML保持處於高位準；當資料不匹配時，其經下拉朝向低 位準。然而，即使當資料不匹配時，匹配線ML仍並不完 全降低至接地電位GND而是停止於一比接地電位GND高匹 配電晶體TPM之臨限電壓的電位。因此，較佳地，圖1中 所示之感測電路13藉由將此電位看作低電位來感測並放大 此電位。 第十實施例 如圖11中所示，如同在上文所提及之第三實施例中，可 用CMOS傳輸閘32及34來替代在上文所提及之第九實施例 中之比較電晶體TNC0及TNC1。 第十一實施例 在上文所提及之第一至第十實施例中，電晶體TNM或 TPM根據共同匹配節點MN之電位來對用於搜尋之匹配線 ML進行充電或放電。取而代之，如圖12中所示，可提供 CMOS反相器42。反相器42包括一 p通道MOS電晶體TPM及 一 η通道MOS電晶體TNM。又，其之輸入節點耦接至共同 匹配節點ΜΝ。當資料匹配時，反相器42將一位元匹配信 號ΒΜ驅動至高位準，因為共同匹配節點ΜΝ被下拉至低位 準。相反，當資料不匹配時，反相器42將位元匹配信號 ΒΜ驅動至低位準，因為共同匹配節點ΜΝ被上拉至高位 準。 在此狀況下，提供AND電路而非圖1中所示之匹配線 142877.doc -25- 201023185 ML、匹配線預充電電路11及感測電路13。將自每一記憶 體單元10輸出之位元匹配信號BM輸入至AND電路中。自 AND電路輸出判定信號HIT。 第十二實施例 如圖13中所示，如同在圖3中所示之第二實施例中，可 將位元線BLT及BLC而非在上文所提及之第十一實施例中 之所有的用於寫入之位元線BLT W及BLCW以及用於搜尋 及讀取之位元線BLTSR及BLCSR用於所有的寫入操作、搜 尋操作及讀取操作。 第十三實施例 如圖14中所示，如同在圖I2中所示之第十一實施例中， 可提供CMOS反相器42而非圖4中所示之第三實施例或圖1〇 中所示之第九實施例中之電晶體TNM或TPM。 第十四實施例 如圖15中所示，如同在圖3中所示之第二實施例中，可 將位元線BLT及BLC而非在上文所提及之第十三實施例中 之所有的用於寫入之位元線BLTW及BLCW以及用於搜尋 及讀取之位元線BLTSR及BLCSR用於所有的寫入操作、搜 尋操作及讀取操作 上文所提及之第一至第十實施例中之電晶體TNM及TPM 與上文所提及之第十一至第十四實施例中之CMOS反相器 42皆意欲感測並放大共同匹配節點MN之電位且輸出經感 測放大之信號。因此，若確保足夠之輸出電流，則可省略 電晶體TNM或TPM或者CMOS反相器42使得直接輸出共同 142877.doc -26- 201023185 匹配節點MN之電位。 在上文所提及之第--至第十四實施例中，CMOS反相 器42靜態地驅動位元匹配信號bm，且AND電路靜態地驅 動判定信號HIT。因此，與在第一至第十實施例（其中必須 根據用於搜尋之匹配線ML之預充電狀態而將用於搜尋之 • 位元線預充電至適當電位）中不同’不需要將用於搜尋之 位元線預充電至特定位準。此係有利的’因為電路設計之 靈活性得以增加。 ❹ 又’在所有上文所提及之實施例中，η通道MOS電晶體 與ρ通道MOS電晶體可彼此替代。 雖然已描述了本發明之實施例，但上文所提及之實施例 僅為用以實施本發明之實例。因此，本發明並不限於上文 所提及之實施例，且該等實施例可在不背離本發明之精神 及範疇的情況下在適當時加以修改並予以實施。 【圖式簡單說明】 φ 圖1為展示根據本發明之一實施例之CAM之字的組態的 功能方塊圖； 圖2為展示根據本發明之第一實施例之cam之記憶體單 - 元及其周邊的組態的電路圖； - 圖3為展示根據本發明之第二實施例之CAM之記·憶體單 元及其周邊的組態的電路圖； 圖4為展示根據本發明之第三實施例之CAM之記憶體單 元及其周邊的組態的電路圖； 圖5為展示根據本發明之第四實施例之cam之記憶體單 142877.doc • 27· 201023185 元及其周邊的組態的電路圖； 圖6為展示根據本發明之第五實施例之CAM之記憶體單 元及其周邊的組態的電路圖； 圖7為展示根據本發明之第六實施例之之記憶體單 元及其周邊的組態的電路圖； 圖8為展示根據本發明之第七實施例之之記憶體單 元及其周邊的組態的電路圖； 圖9為展示根據本發明之第八實施例之cam之記憶體單 元及其周邊的組態的電路圖； 圖10為展示根據本發明之第九實施例之cam之記憶體單 元及其周邊的組態的電路圖； 圖11為展示根據本發明之第十實施例之cam之記憶體單 元及其周邊的組態的電路圖； 圖12為展示根據本發明之第十一實施例之cam之記憶體 單元及其周邊的組態的電路圖； 圖13為展示根據本發明之第十二實施例之cam之記憶體 單元及其周邊的組態的電路圖； 圖14為展示根據本發明之第十三實施例之cam之記憶體 單元及其周邊的組態的電路圖； 圖15為展示根據本發明之第十四實施例之cam之記憶體 單元及其周邊的組態的電路圖； 圖16為展示CAM之相關記憶體單元及其周邊的組態的電 路圖；及 圖17為展示CAM之相關記憶體單元及其周邊之組態的電 142877.doc -28- 201023185 路圖，該CAM不同於圖16中所示之實例。 【主要元件符號說明】 10 11 12 13 14 、 16 、 42 15 、 17 、 19 、 21 18 20 22 24 26 28 30 φ 32、 34 36、37、38、39、 40 ' 41The switching element for reading is connected to the common matching node and has a predetermined potential section WJ; -> BB ‘· S ′ and is turned on or off according to the potential of the word line for reading. The memory device includes the memory referred to above in accordance with the present invention. Advantages By using the present invention, and ensuring data readability. 5 Recalling unit includes the least possible transistor, data writing operation and data retention are stable. The number of components using the same component is smaller. For both data search and data reading, the record is small, and the area occupied by the memory unit is independent of the read operation and the write operation + mother in the ρ 1 of the component of the ** memory The optimization is optimized, so the visit-A results, due to the rumor P, the size reduction of these components is reduced by the area of the my image occupied by the δ-hidden early sputum. Also, the operation is accelerated for the same w.丨 丨 々 々 读取 读取 读取 曾 曾 曾 曾 曾 曾 曾 曾 曾 曾 曾 曾 曾 曾 ^ ^ ^ ^ ^ 曾 ^ ^ ^ ^ 曾 曾 曾 ^ 曾 ^ ^ ^ ^ ^ ^ ^ 曾 曾Action and write action. Therefore, the pre-charging level of the line can be increased. m fruit, 6 and leaf flexibility as will be seen in the following examples, even by changing the to-be-used, search for knowledge, can be used to make the pre-charged position The standard is high] 42877.doc 201023185 or low. In combination with the flexibility of the pre-charge level of the bit line for the read operation, the design flexibility of the memory device is significantly increased. In the present invention, the same bit line from the structure of the memory cell is naturally used for reading and searching for both. Conversely, when the same bit line is used for reading and searching in the related art memory unit, The access transistor and the comparison circuit used for the search act as a load on the bit line. Therefore, the parasitic electric valley of the bit line increases. This reduces the speed of operation and increases power consumption. The present invention reduces the parasitic capacitance to half or less of the parasitic capacitance in the related art', thereby accelerating the operation and reducing the power consumption. [Embodiment] Embodiments of the present invention will now be described with reference to the accompanying drawings. In this figures, the same or equivalent elements are assigned the same reference numerals and will not be described repeatedly. First Embodiment In FIG. 1, with respect to each word, according to a first embodiment of the present invention, N (natural number) memory cells 1 〇, a matching line for searching ML"-match line pre-charging Circuit u and a sensing circuit ". Every. The hidden single 7L10 stores a data bit. The configuration of the memory Cuiyuan 1〇 will be described later. The match line precharge circuit 11 precharges the matching line muscle for searching to a high level (power supply potential VDD) in response to the precharge signal MLPC. If the information provided from the external (four) bits matches all the coffee bits stored in the memory list W0, the matching line muscle used for the search maintains the high level without being discharged. On the other hand, if the N bits of the material supplied from the outside do not match the _ 142877.doc 201023185 bit or even one bit of the data stored in the cell of the cell, then the match for the search is used. The line ML discharge causes it to give a low level (ground potential GND). The details will be described later. The sensing circuit 13 senses and amplifies the potential of the matching line ML for searching, and outputs a decision signal HIT indicating data matching or data mismatch. In FIG. 2, the CAM 8 further includes bit lines BLTW and BLC W for writing, a word line WWL for writing, bit lines BLTSR and BLCSR for searching and reading, and one for reading. The word line RWL, a match line ML for searching, and precharge circuits 15 5, 17, 7, and 21 are taken. The word line WWL for writing is driven to a high level for writing data. The word line RWL for reading is driven to a high level for reading the data. The match line ML for the search is precharged to a high level for searching for data. Precharge circuits 1 5 and 17 precharge the bit lines BLTW and BLCW for writing to a high level for writing data, respectively. The pre-charging circuits 19 and 21 pre-charge the bit lines BLTSR and BLCSR for searching and reading to the low level for searching for data, and pre-charging the bit lines BLTSR and BLCSR for searching and reading, respectively. The highest level is used to read data. Each of the memory cells 10 includes a latch circuit 12 for holding one of the data bits and access transistors TNWA0 and TNWA1, each of which is made of an n-channel MOS transistor. Latch circuit 12 includes cross-coupled CMOS inverters 14 and 16. The input node 18 of the CMOS inverter 14 is coupled to the storage node SNC, and its output node 20 is coupled to the storage node SNT. The input node 22 of the CMOS inverter 16 is coupled to the storage node SNT, and the output node 24 thereof is coupled to the storage node SNC. 142877.doc • 12- 201023185 The CMOS inverter 14 includes a load transistor ΤΡ0 made of a p-channel MOS transistor and a drive transistor ΤΝ0 made of an n-channel MOS transistor. The gate of the load transistor ΤΡ0 is coupled to the input node 18, the source of which is coupled to the power supply 26, and the drain of the load transistor is coupled to the output node 20. The gate of the driving transistor ΤΝ0 is coupled to the input node 18, the source of which is coupled to the ground 28, and the drain of the driving transistor is coupled to the output node 20. The CMOS inverter 16 includes a load transistor TP1 made of a p-channel MOS transistor and a drive transistor TN1 made of an n-channel MOS transistor. The gate of the load transistor ΤΡ1 is coupled to the input node 22, the source of which is coupled to the power supply 26, and the drain of which is coupled to the output node 24. The gate of the driving transistor ΤΝ1 is coupled to the input node 22, the source of which is coupled to the ground 28, and the drain of which is coupled to the output node 24. The gate of the access transistor TNWA0 is coupled to the word line WWL for writing. The first source/drain is coupled to the bit line BLTW for writing, and the second source/drain is coupled to the storage node SNT. The gate of the access transistor TNWA1 is coupled to the word line WWL for writing, the first source/drain is coupled to the bit line BLCW for writing, and the second source thereof is/ The drain is coupled to the storage node SNC. Each memory unit 10 further includes a comparison circuit 30 for searching, which compares the input data provided via the bit lines BLTSR and BLCSR with the data stored in the latch circuit 12. The comparison circuit 30 for searching includes: comparison transistors TNC0 and TNC 1, each of the comparison transistors being made of an n-channel MOS transistor; and a matching transistor ΤΝΜ made of an n-channel MOS transistor. The gate of the comparison transistor TNC0 is coupled to the 142877.doc 13 201023185 storage node SNC, and the first source/drain is coupled to the bit line BLTSR for searching and reading, and the second source thereof The pole/drain is coupled to the common matching node MN. The gate of the comparison transistor TNC1 is coupled to the storage node SNT, and the first source/drain is coupled to the bit line BLCSR for searching and reading, and the second source/drain coupling thereof Connected to the common matching node MN. The gate of the matching transistor TNM is coupled to the common matching node MN, the source of which is coupled to the ground 28, and the drain of which is coupled to the matching line ML for searching. Each memory cell 10 further includes a transistor TNRA for reading, which is made of an n-channel MOS transistor. The gate of the transistor TNRA for reading is coupled to the word line RWL for reading, the source of which is coupled to the ground 28, and the drain of which is coupled to the common matching node ΜΝ. The CAM 8 according to this embodiment is different from the related art example shown in Fig. 16 because the CAM 8 additionally includes a transistor TNRA for reading. Further, the bit lines BLTRW and BLCRW are used for reading and writing in the related art example, and the bit lines BLTW and BLCW are used only for writing in this embodiment. Further, in the related art example, the bit lines BLTS and BLCS are used only for searching, and in this embodiment, the bit lines BLTSR and BLCSR are used for searching and reading. Therefore, the comparative transistors TNC0 and TNC1 are used only for the search in the related art example, and in this embodiment, the transistors are used for both searching and reading. That is, in this embodiment, the 用于 for reading is separated from the 用于 for writing, and the 用于 for searching is combined with for reading. The operation of the CAM 8 will be described below. 142877.doc -14· 201023185 (1) The write operation is to write data into the memory unit 10. First, the precharge circuits 15 and 17 precharge the bit lines BLTW and BLCW for writing to a high level. Level. From this state, the potential of one of the bit lines BLTW and BLCW for writing is lowered to a low level in accordance with the material to be written, and the word line WWL for writing is driven to a high level. Therefore, the access transistors TNWA0 and TNWA1 are turned on, and the data is written to the latch circuit 12 for driving the data held by the latch circuit 12 for driving the bit line BLTW for writing. And a write data driver of the BLCW (not shown) must resist the load transistors ΤΡ0 and TP1 via the access transistors TNWA0 and TNWA1 to change the potential of one of the storage nodes SNT and SNC from a high level to a low level. The potential of the other of the storage nodes SNT and SNC is changed from a low level to a high level. Therefore, in order to perform a stable write operation, it is preferable to design the access transistors TNWA0 and φ TNWA1 in such a manner that the sizes of the transistors are sufficiently larger than the load transistors ΤΡ0 and TP1. Also, preferably, the drive transistors ΤΝ0 and TN1 are not designed too large. This is because when the bit line BLCW for writing is driven to a low level, the driving transistor ΤΝ0 hinders the potential increase of the storage node SNT, and when the bit line BLTW is driven to the low level, the driving transistor TN1 hinders the storage node. The potential of the SNC increases. (2) The search operation is to search for the data stored in the memory unit 10. First, the match line precharge circuit 11 shown in FIG. 1 precharges the match line ML for searching to 142877.doc 15 201023185 to a high level. The match line is maintained at an electrically floating or slightly fixed high level (maintained at a given potential via a high resistance), and the precharge circuits 19 and 21 precharge the bit lines BLTSR and BLCSR for searching and reading. To the low level. Next, the common matching node MN is placed at a low level because the transistor TNC0 or TNC1 is turned on according to the storage node SNT or SNC placed at a high level. Therefore, the matching transistor TNM is cut off. In this state, the data to be searched is supplied to the bit lines BLTSR and BLCSR. In this case, the common matching node MN of the memory unit 10 that matches the data to be searched is kept at a low level, and the common matching node MN of the memory unit 10 that stores the data without matching the data to be searched is made. The potential rises towards a high level. Therefore, in the memory unit 10 in which the data mismatch occurs, the matching transistor TNM is turned on, and the matching line ML for searching becomes a low level so that the data mismatch is indicated. Here, preferably, the comparison transistors TNC0 and TNC 1 are of a sufficiently large size that the potential of the common matching node MN sufficiently follows the potentials of the bit lines BLTSR and BLCSR for searching and reading. Further, preferably, the matching transistor TNM has a sufficiently large size (W/L) so that the horsepower distribution crystal can drive the matching line ML for search having a predetermined length for a predetermined time. (3) Read operation To read data from the memory unit 10, first, the precharge circuits 19 and 21 precharge the bit lines BLTSR and BLCSR for searching and reading to a high level. After pre-charging, the bit lines BLTSR and BLCSR may remain floating or may be coupled to a power supply 142877.doc -16 - 201023185 supply 26 via a bit line load element (eg, a pull-up resistor). The precharged bit lines BLTSR and BLCSR are placed at the same level. Starting from this state, when the word line RWL for reading is driven to a high level, the transistor TNRA for reading is turned on according to the data stored in the memory unit 10, and the bit line BLTSR or BLCSR is pulled down to Low level. That is, if the storage node SNT is at a high level, the bit line BLCSR is pulled down to a low level. If the storage node SNC is at a high level, the bit line BLTSR is pulled down to a low level. Here, regarding the low level of the bit line to be pulled down, in the case where the bit lines BLTSR and BLCSR are floating, the bit line is lowered to substantially the ground potential GND, and the bit lines BLTSR and BLCSR are passed through the bit lines. In the case where the load component is coupled to the power supply 26, the pull-down bit line is reduced to be obtained by dividing the power supply potential VDD by the resistance of the bit line load component and the on-resistance of the transistors TNC1 and TNRA. Potential. The read data is amplified by a known sensing circuit (not shown), then converted to a high or low level for use in the logic circuit, and finally output from the CAM 8. Although the CAM unit 10 outputs a pair of differential signals, only one of the bit lines BLTSR and BLCSR for searching and reading can be used for reading (by using a single-ended circuit to form the sensing circuit). Preferably, the comparison transistors TNC0 and TNC 1 and the transistor TNRA for reading have a sufficiently large size to reduce one of the bit lines BLTSR and BLCSR for searching and reading to a predetermined speed to Predetermined potential. Since the comparator transistors TNC0 and TNC 1 are used for searching and reading, it is preferable to compare the size required for the seek operation with the size required for the read operation 142877.doc • 17· 201023185 and then select the sizes The bigger one. Subsequently, preferably, the size of the transistor TNRA for reading is determined according to the selected size such that the resistance including the path of the transistor TNRA and one of the transistors TNC0 and TNC1 as a whole is for the read operation The best. As described above, for the writing operation, it is preferable that the driving of the electric crystals ΤΝ0 and TN1 is not necessarily so large. However, regarding the related art memory cell of the CAM as shown in Fig. 16, preferably, the driving transistors ΤΝ0 and TN1 should be large. This is because one of the bit lines BLTRW and BLCRW must be kept as low as possible during the read operation. This is also because the latch circuit 12 must resist the pre-charge to high level bit lines BLTRW and BLCRW or the bit lines BLTRW and BLCRW coupled to the power supply via the bit line load elements to hold the data. In contrast to the above-described related art memory unit, with respect to the memory cell unit 1 according to this embodiment, the driving transistors ΤΝ0 and TN1 are not directly involved in the reading operation. Therefore, it is not necessary to consider the read operation when determining the size of the drive transistors ΤΝ0 and TN1. This allows for not only increased design flexibility but also a wide range of possibilities for design in recent semiconductor technologies characterized by advanced miniaturization and low voltage. The stability of the data during data retention depends on the load transistors ΤΡ0 and TP1, the drive transistors ΤΝ0 and TN1, and the noise factor (such as soft errors caused by radiation entering the CAM 8 from the outside). In order to minimize the influence of noise, it is preferable that the load transistors ΤΡ0 and TP1 and the driving transistors ΤΝ0 and TN1 should be large. However, if the transistors ΤΡ0, TP1, ΤΝ0, and TN1 are made larger, the current consumption due to the sub-limit current becomes not 142877.doc -18- 201023185 is negligible. Therefore, the dimensions of these transistors must be such that they are appropriately sized according to design requirements and the noise factor to be considered. For example, it must be ensured that the current supply capability is such that the critical charge amount of the soft error (the amount of charge necessary to invert the retained data) is not reduced. In the memory unit 10 according to this embodiment, 'the comparison transistor 11^ (the gate capacitance of 〇 and TNC1 is applied to the storage nodes SNT and SNc as a parasitic capacitance. Therefore, the critical charge amount of the soft error is increased, so that The possibility of a soft error in the memory single φ 兀 10 is less than the possibility of a soft error in the typical memory cell of the SRAM. As a result, the transistors τρ〇, τρι, "0" and TN1 can be used to hold the data. A sufficient amount of charge is supplied to the storage nodes SNT and SNC (even in the case where the size of the transistors is small). From the above description, the size of the transistors is preferably determined as follows. The data of the load cell τρ〇 and Φ TP1 which are judged to be pFETs and have a lower current drive capability per unit size are held during the hold period. Therefore, it is determined that the drive transistors ΤΝ0 and TN1 are stored in consideration of the write operation. Take the dimensions of the transistor 7^|Bagua and 1^Jia. 1. Here, in the case of the related art memory unit, the speed of the read operation and the data during the read period must be considered as described above. The characteristics and the data retention characteristics of the unselected cells and the write operation itself during the writing period. In contrast, in the case of the memory cell unit 1 according to this embodiment, it is not necessary to simultaneously consider the write operation and the read operation. The operation and the read operation determine the comparison of the transistors TNC0 and TNC1 and then consider the read operation to determine the size of the transistor TNRA for reading is sufficient. By adopting the decision 142877.doc -19-201023185 method, Attributable to component miniaturization and low voltage limitations (requiring that the transistor is satisfied for reading data, writing data, and maintaining data) is substantially reduced compared to limitations in related art memory cells. The memory unit 10 is allowed to be constructed in a small area that fully satisfies all the conditions regarding the write operation, the read operation, the seek operation, and the data retention characteristics. The second embodiment is independent in the first embodiment mentioned above. The bit lines BLTW and BLCW for writing and the bit lines BLTSR and BLCSR for searching and reading are provided, but the bit lines BLT and BLC can be used instead of the above The line is used for all write operations, seek operations, and read operations, as shown in Figure 3. Specifically, in the second embodiment, the bit line BLT is coupled to the source/汲 of the access transistor TNWA0. And the source/drain of the transistor TNC0, and the bit line BLC is coupled to the source/drain of the access transistor TNWA1 and the source/drain of the comparator transistor TNC 1. In the example, reading and writing cannot be performed simultaneously in the second embodiment; however, the total number of necessary bit lines is reduced by half. The third embodiment will be compared in the first embodiment mentioned above. The transistors TNC0 and TNC 1 are used as source followers. Therefore, when the potentials of the bit lines BLTSR and BLCSR for searching and reading are high, the potentials are not transmitted as they are to the common matching node MN. It is a drop in the threshold voltage of the comparator transistors TNC0 and TNC 1. To cope with this problem, as shown in Fig. 4, CMOS transfer gates 32 and 34 can be used in place of the comparison transistors TNC0 and TNC1 in the first embodiment. 142877.doc -20· 201023185 CMOS transmission gate 32 includes an n-channel MOS transistor TNC0 and a p-channel MOS transistor TPC0. The gate of the transistor TNC0 is coupled to the storage node SNC, and the first source/drain is coupled to the bit line BLTSR ' for searching and reading and the first source/pole/pole surface thereof Connected to the common matching node MN. The gate of the transistor TPC0 is coupled to the storage node SNT, and the first source/drain is coupled to the bit line BLTSR for searching and reading, and the second source/drain is connected to Commonly match the node MN. The CMOS transmission gate 34 includes an n-channel MOS transistor TNC1 and a p-channel MOS transistor TPC1. The gate of the transistor TNC1 is coupled to the memory node SNT, and the first source/drain is coupled to the bit line BLCSR ' for searching and reading, and the second source/no pole is coupled To the common matching node μν. The gate of the transistor TPC1 is connected to the storage node SNC, and the first source/drain is coupled to the bit line BLCSR for searching and reading, and the second source/the pole is lightly connected to Match the nodes together. The potential of the bit lines BLTSR ❹ and BLCSR for the search and read by the third embodiment is directly transmitted to the common matching node MN without any voltage drop. Therefore, the seek operation and the read operation are accelerated. The number of necessary transistors for the health tube is increased as compared with the number of transistors in the first embodiment, but the sizes of the transistors TNC0, TPC0, TNC1 and TPC1 can be reduced. The fourth embodiment is as shown in FIG. 5, as in the third embodiment mentioned above, the CMOS transfer gates 32 and 34 may be used instead of the comparative transistor TNC0 in the second embodiment mentioned above and TNC1. Fifth Embodiment 142877.doc -21· 201023185 In the above-mentioned embodiments, the pre-charge levels of the bit lines BLTSR and BLCSR for searching and reading are low for the seek operation, and High level for read operations. However, since it is not known in advance which of the seek operation and the read operation is requested, it is assumed that one of the operations is requested, and the bit line needs to be precharged to a low level or a high level. Therefore, if a different operation than the assumed operation is requested, the precharge must be performed again. This is an obstacle to high-speed operation because the worst-case condition must be assumed throughout the timing design (the pre-charge condition is performed again). To cope with this obstacle, in the fifth embodiment, the precharge circuits 36 and 37 precharge the bit lines BLTSR and BLCSR for searching and reading to a low level for both the seek operation and the read operation, as shown in the figure. Shown in 6. Further, the transistor TPRA for reading in this embodiment is composed of a p-channel transistor, and the transistor TNRA for reading in the above-mentioned embodiment is composed of an n-channel MOS transistor. Further, the source of the transistor TPRA for reading according to this embodiment is coupled to the power supply 26. The word line RWL for reading during a read operation is driven to a low level and maintains a high level when a read operation is not requested. Therefore, the transistor TPRA for reading is turned on for the read operation, and one of the bit lines BLTSR and BLCSR for searching and reading is based on the data stored in the memory unit 1 Pull up to a high level. In this case, the read data has a polarity opposite to that when the data has been written; therefore, it is preferable to invert the polarity before outputting the data from the CAM 8. It is precisely because the 用于 for reading is separate from the 用于 for writing and the comparison transistors TNCO and TNC 1 are used not only for the search operation but also for the read operation, 142877.doc -22· 201023185 can be implemented as such The precharge level of the bit line for the read operation is changed as shown in the example. Again, this is achieved by a minimum number of transistors. In contrast, with regard to the related art memory cells that use the same 埠 for both reading and writing, there is no choice but to define the pre-charging level of the bit line as a high level for three reasons: The driving forces of the crystals ΤΡ0 and TP1 are weaker than those of the driving transistors ΤΝ0 and TN1 (which are n-channel MOS transistors) because each of the load transistors ΤΡ0 and ΤΡ1 is made of a p-channel MOS transistor; Ensure that the data during the read period remains stable and that the write operation is stable; and that the memory unit must be small. The sixth embodiment is as shown in FIG. 7, as in the third embodiment mentioned above, the CMOS transfer gates 32 and 34 can be used instead of the comparative transistor TNC0 in the fifth embodiment mentioned above. And TNC1. Seventh Embodiment Although the matching transistor TNM is made of an n-channel MOS transistor in the fifth embodiment mentioned above, the matching transistor TPM is constituted by the ρ channel in the seventh embodiment shown in FIG. Made of MOS transistor. The source of the matching transistor TPM is coupled to the power supply 26 . Although in the fifth embodiment mentioned above, each of the comparative transistors TNC0 and TNC1 is made of an n-channel MOS transistor, in the seventh embodiment, each of the transistors TPC0 and TPC 1 is compared. One is made of a p-channel MOS transistor. Although the precharge circuits 36 and 37 precharge the bit lines BLTSR and BLCSR for searching and reading to the low level for the seek operation and the read operation in the fifth embodiment, the precharge is performed in the seventh embodiment. Circuits 38 and 39 precharge the bit lines BLTSR and BLCSR for searching and reading to 142877.doc -23-201023185 for the seek operation and precharge the bit lines to the read operation. Low level. In this case, the read data has the same polarity as when the data has been written. Therefore, it is not necessary to invert the polarity before outputting data from the CAM 8. Further, in the seventh embodiment, the match line ML for search is precharged to a low level for the seek operation. Therefore, the match line ML remains at a low level when the data matches; when the data does not match, it is pulled up to a high level. The eighth embodiment is as shown in FIG. 9, as in the third embodiment mentioned above, the CMOS transfer gates 32 and 34 can be used instead of the comparative transistor TPC0 in the seventh embodiment mentioned above. And TPC1. Ninth Embodiment In the ninth embodiment shown in FIG. 10, unlike the seventh embodiment mentioned above, each of the comparative transistors TNC0 and TNC1 is made of n-channel MOS transistor. to make. Moreover, the gate of the comparison transistor TNC0 is coupled to the storage node SNT, and the gate of the comparison transistor TNC1 is coupled to the storage node SNC. The drain of the matching transistor is coupled to ground 28. The transistor TNRA for reading is the same as the transistor TNRA in the first to fourth embodiments mentioned above. Further, in the ninth embodiment, the precharge circuits 40 and 41 precharge the bit lines BLTSR and BLCSR for searching and reading to a high level for both the seek operation and the read operation. Therefore, the read data has a polarity opposite to that when the data has been written. Therefore, it is preferable to invert the polarity before outputting data from the CAM 8. 142877.doc • 24-201023185 Further, in the ninth embodiment, the wiring ML for searching is precharged to a high level for the seek operation. Therefore, when the data matches, the match line ML remains at a high level; when the data does not match, it is pulled down toward a low level. However, even when the data does not match, the match line ML does not completely fall to the ground potential GND but stops at a potential higher than the ground potential GND by the threshold voltage of the power distribution crystal TPM. Therefore, preferably, the sensing circuit 13 shown in Fig. 1 senses and amplifies the potential by considering this potential as a low potential. The tenth embodiment is as shown in FIG. 11, as in the third embodiment mentioned above, the CMOS transfer gates 32 and 34 can be used instead of the comparative transistor TNC0 in the ninth embodiment mentioned above. And TNC1. Eleventh Embodiment In the first to tenth embodiments mentioned above, the transistor TNM or TPM charges or discharges the matching line ML for searching based on the potential of the common matching node MN. Instead, as shown in Fig. 12, a CMOS inverter 42 can be provided. The inverter 42 includes a p-channel MOS transistor TPM and an n-channel MOS transistor TNM. In addition, its input node is coupled to a common matching node. When the data matches, inverter 42 drives the one-bit match signal ΒΜ to a high level because the common match node ΜΝ is pulled down to the low level. Conversely, when the data does not match, inverter 42 drives bit match signal ΒΜ to a low level because the common match node 上 is pulled up to a high level. In this case, an AND circuit is provided instead of the match line 142877.doc -25 - 201023185 ML, the match line precharge circuit 11, and the sense circuit 13 shown in FIG. The bit matching signal BM output from each of the memory cells 10 is input to the AND circuit. The decision signal HIT is output from the AND circuit. The twelfth embodiment is as shown in FIG. 13, as in the second embodiment shown in FIG. 3, the bit lines BLT and BLC can be used instead of all of the eleventh embodiment mentioned above. The bit lines BLT W and BLCW for writing and the bit lines BLTSR and BLCSR for searching and reading are used for all write operations, seek operations, and read operations. The thirteenth embodiment is as shown in FIG. 14, as in the eleventh embodiment shown in FIG. 12, a CMOS inverter 42 may be provided instead of the third embodiment shown in FIG. 4 or in FIG. The transistor TNM or TPM in the ninth embodiment shown. The fourteenth embodiment is as shown in FIG. 15, as in the second embodiment shown in FIG. 3, the bit lines BLT and BLC can be used instead of all of the thirteenth embodiments mentioned above. The bit lines BLTW and BLCW for writing and the bit lines BLTSR and BLCSR for searching and reading are used for all write operations, search operations, and read operations, first to first mentioned above The transistors TNM and TPM in the tenth embodiment and the CMOS inverters 42 in the eleventh to fourteenth embodiments mentioned above are intended to sense and amplify the potential of the common matching node MN and the output is sensed. The signal of amplification. Therefore, if sufficient output current is ensured, the transistor TNM or TPM or CMOS inverter 42 can be omitted so that the potential of the common node 142877.doc -26-201023185 is directly output. In the above - to fourteenth embodiments mentioned above, the CMOS inverter 42 statically drives the bit matching signal bm, and the AND circuit statically drives the decision signal HIT. Therefore, unlike in the first to tenth embodiments, in which the bit line to be used for searching must be precharged to an appropriate potential according to the precharge state for the search match line ML, 'it is not required to be used for The searched bit line is precharged to a specific level. This is advantageous because the flexibility of circuit design is increased. ❹ And in all of the above-mentioned embodiments, the n-channel MOS transistor and the p-channel MOS transistor can be replaced with each other. Although the embodiments of the present invention have been described, the above-mentioned embodiments are merely examples for carrying out the invention. Therefore, the present invention is not limited to the embodiments described above, and the embodiments may be modified and implemented as appropriate without departing from the spirit and scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a functional block diagram showing a configuration of a CAM word according to an embodiment of the present invention; FIG. 2 is a view showing a memory single-element of a cam according to a first embodiment of the present invention. And a circuit diagram of a configuration of the periphery thereof; - FIG. 3 is a circuit diagram showing a configuration of a CAM recording and reproducing unit according to a second embodiment of the present invention and its periphery; FIG. 4 is a view showing a third embodiment according to the present invention. FIG. 5 is a circuit diagram showing the configuration of the memory unit of the cam of the CAM according to the fourth embodiment of the present invention; 142877.doc • 27·201023185 and its surroundings Figure 6 is a circuit diagram showing a configuration of a memory cell of a CAM and its periphery according to a fifth embodiment of the present invention; Figure 7 is a diagram showing a memory cell and its periphery in accordance with a sixth embodiment of the present invention; FIG. 8 is a circuit diagram showing a configuration of a memory unit and its periphery according to a seventh embodiment of the present invention; FIG. 9 is a view showing a memory unit of a cam according to an eighth embodiment of the present invention; Peripheral configuration of electricity Figure 10 is a circuit diagram showing a configuration of a memory unit of a cam and its periphery according to a ninth embodiment of the present invention; and Figure 11 is a memory unit and its periphery showing a cam according to a tenth embodiment of the present invention; FIG. 12 is a circuit diagram showing a configuration of a memory unit of a cam according to an eleventh embodiment of the present invention and its periphery; FIG. 13 is a view showing a cam according to a twelfth embodiment of the present invention; FIG. 14 is a circuit diagram showing a configuration of a memory unit of a cam according to a thirteenth embodiment of the present invention and its periphery; FIG. 15 is a diagram showing a configuration according to the thirteenth embodiment of the present invention; FIG. 16 is a circuit diagram showing a configuration of a memory unit of the cam and its surroundings; FIG. 16 is a circuit diagram showing a configuration of a CAM related memory unit and its periphery; The peripheral configuration of the 142877.doc -28-201023185 road map, which is different from the example shown in FIG. [Description of main component symbols] 10 11 12 13 14 , 16 , 42 15 , 17 , 19 , 21 18 20 22 24 26 28 30 φ 32, 34 36, 37, 38, 39, 40 ' 41
BLTSR、BLCSRBLTSR, BLCSR
BLTW、BLCWBLTW, BLCW
MLML
MNMN
RWLRWL
SNT、SNC 記憶體單元 匹配線預充電電路 鎖存電路 感測電路 反相器 預充電電路 輸入節點 輸出節點 輸入節點 輸出節點 電源供應器 接地 用於搜尋之比較電路 傳輸閘 預充電電路 用於搜尋及讀取之位元線 用於寫入之位元線 用於搜尋之匹配線 共同匹配節點 用於讀取之字線 儲存節點 142877.doc -29- 201023185 ΤΝΟ、TNI TNCO至 TNC3、 TPCO、TPC1 TNM、TPM TNRA、TPRA TNWAO ' TNWA1 TPO、TP1 WWL 驅動電晶體 比較電晶體 匹配電晶體 用於讀取之電晶體 存取電晶體 負載電晶體 用於寫入之字線 142877.doc -30·SNT, SNC memory cell match line precharge circuit latch circuit sense circuit inverter precharge circuit input node output node input node output node power supply grounding for comparison comparison circuit transmission gate precharge circuit for search and The read bit line is used to write the bit line for searching. The matching line is used to match the node for reading the word line storage node. 142877.doc -29- 201023185 ΤΝΟ, TNI TNCO to TNC3, TPCO, TPC1 TNM , TPM TNRA, TPRA TNWAO ' TNWA1 TPO, TP1 WWL drive transistor comparison transistor matched transistor for reading transistor access transistor load transistor for writing word line 142877.doc -30·