KR20000074832A - Write circuit for memory device - Google Patents

Abstract

PURPOSE: A write circuit of a memory device is provided which is appropriate for increasing the speed of write operation by reducing a turn-on resistance using an NMOS pass transistor. CONSTITUTION: A write circuit of a memory device, which is written by a row data, includes: a write driving part which is switched on/off selectively by a signal assembling a data signal inputted from the external and an input enable buffer clock signal and drives a data line(D), a /data line(/D) in a low state; a column selection part which receives a signal of the driven data line or /data line and drives a bit line(B), a /bit line(/B) selectively according to a column select signal; and a cell array part writing data included in the bit line, /bit line into a specific cell. Thus, the circuit improves the speed of write operation because it drives data line and bit line using an NMOS pass transistor.

Description

WRITE CIRCUIT FOR MEMORY DEVICE

The present invention relates to a memory device, and more particularly to a write circuit of a memory device suitable for increasing the speed of a write operation.

In general, a write operation selects a specific word line according to a row address signal so that data of a cell is loaded on a bit line and amplified by a bit line sense amplifier. Writes to a specific cell

The specific cell is selected by a column address signal inputted during the amplification operation, data to be written, and a write enable signal indicating a write operation.

At this time, the unselected cells only have an operation (refresh) in which the value amplified by the sense amplifier is rewritten.

In the write operation, external data is transferred to a data bus line, and the data voltage is overwritten in the order of overwriting the previous state of the bit line sense amplifier.

In the digital MOS circuit, a basic switching operation is performed by a transistor, and a basic logic operation is performed by a gate logic circuit.

NMOS (PMOS) pass transistors and CMOS transmission gates are used to implement the gate logic circuit.

Hereinafter, a write circuit of a memory device according to the related art will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram illustrating a write path of a conventional memory device, and includes an input data Data_in signal, an input enable buffer clock signal CIEB, and a write enable clock signal Clock Write. The write driver 13 driving the data line (D) and the / data line (/ D) by receiving the input of Enable; CWE, and the driven data line (D) or / data line A column select unit 12 which receives a signal of (/ D) and drives a bit line (B) or a / bit line (/ Bit line; / B) according to a column select (CS) signal; The cell array unit 11 receives a bit line equalization signal BEQ and a word line selection signal WL to write data connected to the bit line B or the bit line / B to a specific cell. .

FIG. 2 is a circuit diagram illustrating the write driver of FIG. 1, and includes first and second NOR gates 14 and 15 receiving input data data_in and an input enable buffer clock signal CIEB. And first and second inverters 16 and 17 receiving the output signals of the first and second NOR gates 14 and 15 and a write enable clock signal CWE. It consists of first and second transmission gates 18, 19 which transmit the output of (16, 17) to data line D or / data line / D.

Here, the first and second transmission gates 18 and 19 are inverted signals of the first and second NMOSs MN10 and MN20 and the write enable clock signal CWE, which are commonly inputted with the write enable clock signal CWE. Is composed of first and second PMOSs MP10 and MP20 that are commonly input.

The operation of the write circuit of the conventional memory device as described above is as follows.

First, when a cell is selected during data writing, the word line WL and the column select CS signal are high and the bit line equalization signal BEQ pulse is high, thereby causing the bit line B or the like. The / bit line / B and the data line D or the / data line / D are both precharged to the external power supply voltage VCC level.

At this time, even if the external input data Data_in is input high or low, since the input enable buffer clock CIEB signal is high, the first and second inverters 16 and 17 are independent of the input data Data_in. The outputs of are all high.

Then, when the write enable clock signal CWE becomes high and the input enable buffer clock signal CIEB becomes low, both the first and second transmission gates 18 and 19 are turned on, and the input enable buffer clock signal is turned on. Since the input data Data_in is input by the low signal of CIEB, one node of the data line D and / data line (/ D) or the bit line (B) and / bit line (/ B) becomes low. .

Subsequently, when a write operation is completed in the cell and the input enable buffer clock signal CIEB becomes high again, the outputs of the first and second inverters 16 and 17 are high regardless of externally input data Data_in. In this state, the node which is low among the data line D and the / data line / D or the bit line B and the / bit line / B is precharged to the external power supply voltage VCC level.

Next, when the write enable clock signal CWE is turned low, the first and second transmission gates 18 and 19 are turned off, and the word line select signal WL and the column select signal CS are turned low. Complete the operation cycle.

However, since the write circuit of the memory device according to the related art has a write enable clock (CWE) signal and a transmission gate during a write operation, the core block layout area is increased, and the turn-on resistance of the transmission gate is increased. There is a problem that the output is slow to transfer the data line and / data line because it is large.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a write circuit of a memory device suitable for increasing the speed of the write operation by reducing the turn-on resistance by using an NMOS (pass transistor).

1 is a block diagram showing a write path of a conventional memory device

2 is a write driving circuit diagram of a conventional memory device;

3 is a block diagram illustrating a write path of a memory device according to the present invention.

4 is a write driving circuit diagram of a memory device according to the present invention;

5 is a timing diagram of a write operation of a memory device according to the present invention.

Explanation of symbols for main parts of the drawings

31,32: 1st, 2nd Noah gate 33,34: 1st, 2nd inverter

35,36: 1st, 2nd NMOS

A write circuit of a memory device according to the present invention for achieving the above object is a data line that is selectively switched on / off by a signal combining a data signal input from the outside and an input enable buffer clock signal, / A write driver which drives a data line, a column select unit which receives a signal of the driven data line or / data line and selectively drives a bit line and a / bit line according to a column select signal, and the bit line and / bit line And a cell array unit for writing the data contained in the cell to a specific cell.

Hereinafter, a write circuit of a memory device according to the present invention will be described with reference to the accompanying drawings.

3 is a block diagram illustrating a write path of a memory device according to the present invention, and FIG. 4 is a light driving circuit diagram of the memory device according to the present invention.

5 is a timing diagram of a write operation of a memory device according to the present invention.

That is, the write circuit of the memory device according to the present invention is selectively switched on / off by a signal combining a data DATA_IN signal input from an external device and an input enable buffer clock signal CIEB, thereby being low. The write driver 100 for selectively driving the in-data line (D) and the / data line (/ D), and the driven data line (D) or the / data line (/ D). A column select unit 200 for receiving a signal and selectively driving bit lines (B) and / bit lines (/ Bit lines) according to a column select (CS) signal; (B) and a cell array unit 300 for writing data contained in the / bitline / B to a specific cell.

The write driver 100 may include first and second nodal gates 101 and 102 that selectively transmit data input from the outside to a cell by an input enable buffer clock. First and second inverters 103 and 104 that invert outputs respectively, and first and second NMOSs that are selectively switched on and off by outputs of the first and second inverters 103 and 104 to drive data lines and data lines. 105,106).

At this time, the first and second NMOS 105 and 106 are inputted with a signal in which the input data DATA_IN and the input enable buffer clock CIEB are input to the gate, and the data line D or the / data line / D at the drain. This is connected and the source is grounded.

In addition, the second NOR gate 102 receives a data DATA_IN signal inverted from the input enable buffer clock CIEB.

Hereinafter, the light driving circuit of the memory device according to the present invention will be described.

That is, according to the present invention, an output signal in which the input data DATA_IN and the input enable buffer clock CIEB are combined selectively switches on / off the first and second NMOSs 105 and 106 so that the data line D or the data line. Only nodes in the low state (/ D) are driven.

Initially, the data line (D) and the / data line (/ D) are equalized to a high state in the same manner as the read operation, and the externally input data DATA_IN is input enable buffer clock (CIEB). Is delivered internally.

Subsequently, when the input enable buffer clock CIEB signal is high (logic '1'), the outputs of the first and second inverters 103 and 104 are independent of the high or low state of the input data DATA_IN. All are high.

Subsequently, the first and second NMOSs 105 and 106 are turned on to make both the data line D and the / data line / D high.

Meanwhile, when the input enable buffer clock CIEB signal is in a low state (logic '0'), the input data DATA_IN is input therein so that the input enable buffer clock ( Logic combination with CIEB) signal.

Subsequently, one node of the outputs of the first and second inverters 103 and 104 is in a high state, and the other output node is in a low state, and only one transistor of the first and second NMOS 105 and 106 which receives a signal of the node in the high state. Turn on.

Therefore, only one node of the data line (D) and / data line (/ D) connected to the drain of the turned-on transistor is low, and the bit line (B) for selecting a cell (not shown) to which data is to be written; Only one node of the / bitline (/ B) goes low.

Subsequently, when the write operation is completed in the cell and the input enable buffer clock (CIEB) signal becomes high, the output of the first and second inverters 103 and 104 becomes high regardless of externally input data Data_in. The node which is low among the data line D and the / data line / D is precharged to the external power supply voltage VCC level.

As such, the data line D or the / data line / D and the bit line B or the / Bit line / B in the low state of the input enable buffer clock CIEB signal are in a high state and a low state. Simultaneously.

The write circuit of the memory device as described above writes data to a cell by driving a node in a low state of a data line (bit line) or a / data line (/ bit line) when the input enable clock is low.

Since the write circuit of the memory device according to the present invention drives the data line and the bit line using a pass transistor (NMOS) which is a switching device, the write operation speed can be improved.

Claims (6)

A light driver for selectively switching on / off by a combination of a data signal input from an external source and an input enable buffer clock signal to drive a data line and a data line in a low state; A column select unit which receives a signal of the driven data line or / data line and selectively drives a bit line and a / bit line according to a column select signal, And a cell array unit configured to write data included in the bit line and the bit line to a specific cell. The method of claim 1, The write driver may include first and second inverters for inverting the outputs of the first and second noah gates and the first and second noah gates, which selectively transmit data input from the outside to the cell by an input enable buffer clock. And first and second NMOSs which are selectively switched on / off by an output of the first and second inverters to drive the data lines and the / data lines. The method of claim 2, The output circuit combining the input data and the input enable buffer clock selectively turns on and off the first and second transistors, thereby driving only a node in a low state of the data line and the data line. . The method of claim 2, And the data line and the / data line are both in a high state when the input enable buffer clock is in a high state. The method of claim 2, The first and second NMOS write circuits of the memory device, characterized in that the combination of the input data and the input enable buffer clock is input to the gate, the data line or / data line is connected to the drain and the source is grounded. The method of claim 2, And the data line and the data line simultaneously maintain a high state and a low state when the input enable buffer clock signal is high.