WO2010032865A1 - Dispositif programmable à semi-conducteurs et procédé de transfert de signal dans un dispositif programmable à semi-conducteurs - Google Patents

Dispositif programmable à semi-conducteurs et procédé de transfert de signal dans un dispositif programmable à semi-conducteurs Download PDF

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Publication number
WO2010032865A1
WO2010032865A1 PCT/JP2009/066578 JP2009066578W WO2010032865A1 WO 2010032865 A1 WO2010032865 A1 WO 2010032865A1 JP 2009066578 W JP2009066578 W JP 2009066578W WO 2010032865 A1 WO2010032865 A1 WO 2010032865A1
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signal
programmable device
data signal
circuit
memory
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PCT/JP2009/066578
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English (en)
Japanese (ja)
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斎藤英彰
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日本電気株式会社
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Priority to JP2010529832A priority Critical patent/JP5365638B2/ja
Publication of WO2010032865A1 publication Critical patent/WO2010032865A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17784—Structural details for adapting physical parameters for supply voltage

Definitions

  • the present invention relates to a semiconductor programmable device and a signal transfer method capable of changing a circuit configuration.
  • TAT refers to the time from receipt of an order to completion of delivery.
  • Semiconductor programmable devices range from FPGAs (Field Programmable Gate Array) that reconfigure by combining circuits at the gate level to those that reconfigure by combining circuit blocks (for example, processors and memories) that are larger circuit units. There is something.
  • Non-Patent Document 1 discloses a technique of arranging circuit blocks in a two-dimensional array on a chip and connecting the circuit blocks by mesh wiring.
  • FIG. 14 is a block diagram showing an example of a related semiconductor programmable device in which circuit blocks are arranged in a two-dimensional array and the circuit blocks are connected by mesh-like wiring.
  • circuit blocks 211 are arranged in a two-dimensional array.
  • the circuit block 211 includes a processor, a memory, a custom hardware circuit, and the like. Further, as shown in FIG. 14, each of the circuit blocks 211 arranged in a two-dimensional array is connected to the switch fabric 213.
  • the switch fabric 213 inputs and outputs signals between itself and the circuit block 211 directly connected thereto. Further, it transfers a signal output from the switch fabric 213 adjacent to itself. Further, as shown in FIG. 14, in order to transfer the signal output from the circuit block 211 to the outside of the other circuit block 211 or the semiconductor programmable device, the switch fabrics 213 are connected to each other by mesh-like column wirings 214 and row wirings 215. It is connected. That is, the switch fabric 213 is connected to the other switch fabric 213 adjacent in the vertical direction in the drawing by the column wiring 214 and is connected to the other switch fabric 213 adjacent in the horizontal direction in the drawing by the row wiring 215. .
  • FIG. 15 is a block diagram showing a configuration of the switch fabric 213 of the related semiconductor programmable device shown in FIG.
  • the switch fabric 213 shown in FIG. 14 includes five selectors 213-1 and a selection logic circuit 213-2 connected to each selector 213-1. This is because the switch fabric 213 has inputs and outputs in five directions as described above.
  • the selector 213-1 selects and outputs any one of the signals input from four directions other than the direction in which the selector 213-1 outputs.
  • the selection logic circuit 213-2 determines which direction the signal is selected from.
  • the selection logic circuit 213-2 includes, for example, a decode circuit for decoding a data transfer direction. “Proceedings of the IEEE Computer Society Annual Symposium on VLSI”, 2002, p. 40, Proceedings of the IE Computer Society Annual Symposium on VLSI (Proceedings of the IEEE Computer Society Annual VLSI). 105-112
  • a semiconductor programmable device as disclosed in Non-Patent Document 1 includes a switch fabric that switches connections between circuit blocks in order to change the circuit configuration, compared to a normal semiconductor integrated circuit device in which the circuit configuration cannot be changed. It has different points.
  • the switch fabric occupies a large area on the chip. As a result, depending on the area occupied by the circuit block, a necessary and sufficient number of switch fabrics cannot be accommodated on the chip.
  • An object of the present invention is to provide a semiconductor programmable device and a signal transfer method in the semiconductor programmable device that solve the above-described problem that it is difficult to obtain a semiconductor programmable device with a small chip area and low power consumption. There is.
  • a semiconductor programmable device includes a plurality of switch fabrics that are provided at intersections of a plurality of row wirings and a plurality of column wirings arranged on a chip, and a row wiring and a column wiring, and transfer input data signals. And a plurality of circuit blocks that are directly connected to each of the plurality of switch fabrics and input / output data signals via the plurality of switch fabrics, and the other circuit blocks output the data signals. If so, a pseudo data signal is output, and the switch fabric performs an operation on the data signal and the pseudo data signal and outputs a data signal.
  • the signal transfer method in the semiconductor programmable device of the present invention is: Each of a plurality of switch fabrics provided at intersections of a plurality of row wirings and a plurality of column wirings arranged on a chip, and a row wiring and a column wiring, and for transferring an input data signal, and a plurality of switch fabrics Is a signal transfer method in a semiconductor programmable device having a plurality of circuit blocks that are directly connected to each other and input / output data signals via a plurality of switch fabrics, in which other circuit blocks output data signals If so, the pseudo data signal is output, and the switch fabric performs an operation on the data signal and the pseudo data signal and outputs the data signal.
  • a semiconductor programmable device having a small chip area and low power consumption can be obtained.
  • FIG. 1A is a block diagram showing a configuration of a semiconductor programmable device according to the first embodiment of the present invention.
  • FIG. 1B is a block diagram showing a configuration of a semiconductor integrated circuit device including the semiconductor programmable device according to the first embodiment of the present invention.
  • FIG. 2 is a block diagram showing the configuration of the memory macro of the semiconductor programmable device according to the first embodiment of the present invention.
  • FIG. 3 is a block diagram showing the configuration of the memory input / output unit of the semiconductor programmable device according to the first embodiment of the present invention.
  • FIG. 4 is a block diagram showing a configuration of the switch fabric according to the first exemplary embodiment of the present invention.
  • FIG. 5 is a block diagram showing a configuration of a semiconductor integrated circuit device including another semiconductor programmable device according to the first embodiment of the present invention.
  • FIG. 6 is a block diagram showing a configuration of a switch fabric of another semiconductor programmable device according to the first embodiment of the present invention.
  • FIG. 7 is a block diagram showing a configuration of a semiconductor integrated circuit device according to the second embodiment of the present invention.
  • FIG. 8 is a block diagram showing a configuration of a semiconductor integrated circuit device including a semiconductor programmable device according to the third embodiment of the present invention.
  • FIG. 9 is a block diagram showing a configuration of a switch fabric according to the fourth exemplary embodiment of the present invention.
  • FIG. 10 is a block diagram showing a configuration of a memory macro of a semiconductor programmable device according to the fourth embodiment of the present invention.
  • FIG. 11 is a block diagram showing a configuration of a semiconductor programmable device according to the fifth embodiment of the present invention.
  • FIG. 12 is a block diagram showing a configuration of a switch fabric including a NAND circuit according to the fifth embodiment of the present invention.
  • FIG. 13 is a block diagram showing a configuration of a switch fabric including a NOR circuit according to the fifth embodiment of the present invention.
  • FIG. 14 is a block diagram showing an example of a related semiconductor programmable device.
  • FIG. 15 is a block diagram showing a configuration of a switch fabric of a related semiconductor programmable device.
  • FIG. 1A is a block diagram showing a configuration of a semiconductor programmable device according to the first embodiment of the present invention.
  • the semiconductor programmable device 10 includes a plurality of switches that transfer input data signals provided at intersections of a plurality of column wirings 14 and a plurality of row wirings 15 and a column wiring 14 and a row wiring 15 arranged on the chip. It has a fabric 13. Each switch fabric 13 is directly connected to a circuit block, and each circuit block inputs / outputs a data signal via the switch fabric. The circuit block outputs a pseudo data signal when another circuit block outputs a data signal.
  • the memory macro 11 is used as a circuit block.
  • the switch fabric 13 inputs a data signal and a pseudo data signal and outputs a data signal.
  • the switch fabric 13 according to the present embodiment is configured by a plurality of AND circuits, OR circuits, or a combination of these logic circuits. Therefore, according to the present embodiment, the circuit scale of the switch fabric 13 can be reduced, and the input switching operation is not required for each data read operation. As a result, the area overhead and power consumption overhead caused by the switch fabric can be reduced, so that a semiconductor programmable device with a small chip area and low power consumption can be obtained. [Second Embodiment] FIG.
  • FIG. 1B is a block diagram showing a configuration of a semiconductor integrated circuit device including the semiconductor programmable device according to the first embodiment of the present invention.
  • the semiconductor integrated circuit device shown in FIG. 1B includes a semiconductor programmable device 10 and a logic device 20.
  • the semiconductor programmable device 10 includes a memory macro 11, which is a circuit block, a memory input / output unit 12, and a switch fabric 13.
  • 16 memory macros 11 are arranged in a 4 ⁇ 4 two-dimensional array. Each of the memory macros 11 is directly connected to the switch fabric 13. Further, in the semiconductor programmable device 10 shown in FIG. 1B, a plurality of wirings are laid in the row direction and the column direction.
  • the memory macro 11 includes, for example, a 1 k word SRAM (Static Random Access Memory) macro, and writes a write data signal output from the logic device 20 to a memory cell or outputs a read data signal to the logic device 20.
  • FIG. 2 is a block diagram showing a configuration of the memory macro 11 of the semiconductor programmable device 10 shown in FIG. 1B. As shown in FIG. 2, the memory macro 11 shown in FIG.
  • the 1B includes a control unit 11a, a memory cell array 11g, an address decoder 11b, a word line driver 11c, a sense amplifier 11d, a write buffer 11e, and a read buffer 11f. And.
  • the address decoder 11b controls access to the memory cells in the write and read operations of the memory cells in the memory cell array 11g.
  • the word line driver 11c controls the word line connected to each memory cell in the memory cell array 11g, and the sense amplifier 11d amplifies the signal. The operation of the control unit 11a will be described later.
  • the memory input / output unit 12 illustrated in FIG. 1B mediates signal input / output with the logic device 20.
  • FIG. 1B mediates signal input / output with the logic device 20.
  • FIG. 3 is a block diagram showing a configuration of the memory input / output unit 12 of the semiconductor programmable device 10 shown in FIG. 1B.
  • the memory input / output unit 12 receives a 16-bit read data signal from the memory macro 11 via the switch fabric 13 and outputs it to the logic macro 21 that configures the logic device 20. Further, a 16-bit write data signal, a 14-bit address signal, and a 2-bit command signal from the logic macro 21 are input and output to the switch fabric 13.
  • signal input / output between the logic macro 21 and the semiconductor programmable device 10 a case in which the logic macro 21 instructs the semiconductor programmable device 10 to read a data signal is described with reference to FIGS. 1B to 3. explain.
  • the logic macro 21 instructing to read data outputs a command signal and an address signal to the memory input / output unit 12 as shown in FIG.
  • the command signal and the address signal are input to all the memory macros 11 in the semiconductor programmable device 10 (see FIG. 1B) via the memory input / output unit 12.
  • the command signal indicates a data read instruction.
  • the control unit 11a (see FIG. 2) of the memory macro 11 to which the command signal and the address signal are input, stores its own address stored in advance, and the address of the memory macro 11 to be read from the data indicated by the address signal.
  • the address signal is composed of a total of 14 bits including a 4-bit memory macro address for designating the memory macro 11 and a 10-bit word address for designating a word address in the memory macro 11. It was decided that When the memory macro address of the address signal matches its own address stored in advance in the control unit 11a, an output signal that activates all the circuits in the subsequent stage is connected from the control unit 11a to the control unit 11a. To all the wiring on the output side. At this time, the control unit 11a reads data from the memory cell indicated by the word address in the memory cell array 11g. This is because the command signal indicates a data read instruction. The control unit 11a outputs the read data as a read data signal from the read buffer 11f.
  • the read data signal output from the read buffer 11f is input to the OR circuit 11i.
  • a signal obtained by inverting the output signal from the control unit 11a by the inverter 11h is input to the OR circuit 11i. When the addresses match, this signal is at a low level, so the read data signal output by the control unit 11a is output as it is from the OR circuit 11i.
  • the read data signal output from the memory macro 11 is transferred by the switch fabric 13 and output to the logic macro 21 via the memory input / output unit 12.
  • An OR circuit is a circuit that outputs a low level signal only when all of a plurality of input signals are low level signals, and outputs a high level signal in other cases. Say.
  • FIG. 4 is a block diagram illustrating a configuration of the switch fabric 13 illustrated in FIG. 1B.
  • the switch fabric 13 includes an AND circuit 13a.
  • the AND circuit 13a is provided for each signal input / output direction.
  • An AND circuit is a circuit that outputs a high level signal only when all of a plurality of input signals are high level signals, and outputs a low level signal otherwise. is there.
  • the switch fabric 13 has inputs and outputs in a total of five directions.
  • the switch fabric 13 is connected to the adjacent switch fabric 13 by the column wiring 14 in the vertical direction in FIG. 1B in addition to the connection to the memory macro 11. This is because they are connected to the adjacent switch fabric 13 by the row wiring 15 in the left-right direction.
  • the switch fabric 13 includes five AND circuits 13a that are the same as the number of signals in the input / output direction.
  • a signal output from the AND circuit 13a when a signal is input to the AND circuit 13a from four directions other than the direction in which the signal is output will be described.
  • the plurality of memory macros 11 sharing the memory input / output unit 12 constitute one memory area, the plurality of memory macros 11 do not output read data signals at the same time.
  • one logic macro 21 in the logic device 20 instructs the memory macro 11 in the semiconductor programmable device 10 to read a data signal. In this case, as shown in FIG.
  • the logic macro 21 is connected to each logic macro 21 with an address signal indicating the address of the memory macro 11 from which a data signal is to be read and a command signal indicating data reading. Output to the switch fabric 13 via the memory input / output unit 12.
  • the memory input / output unit 12 is connected to all the memory macros 11 by the switch fabric 13, the column wiring 14, and the row wiring 15. That is, all the memory macros 11 in the semiconductor programmable device 10 share the memory input / output unit 12 and constitute one memory area. Therefore, the address signal and the command signal output from the logic macro 21 are input to all the memory macros 11 in the semiconductor programmable device 10.
  • the memory macro 11 to which the address signal and the command signal are input compares its own address with the address indicated by the address signal, and outputs a read data signal when they match. That is, the memory macros 11 other than the memory macro 11 instructed to read the data signal by the logic macro 21 do not read the data signal because the address of the memory macro 11 does not match the address indicated by the address signal. Therefore, a plurality of memory macros 11 do not output read data signals at the same time. Further, as described above, the memory macros 11 other than the memory macro 11 instructed to read the data signal by the logic macro 21 receive a high level signal in which all bits are high level from the OR circuit 11i shown in FIG. Output.
  • a signal input to the switch fabric 13 from a direction other than the direction transferred from the memory macro 11 that outputs the read data signal becomes a high level signal in which all bits are at a high level.
  • the read data signal is output as it is from the switch fabric 13 by the AND circuit 13 a and transferred to the adjacent switch fabric 13.
  • all the memory macros 11 in the semiconductor programmable device 10 shown in FIG. 1B share the memory input / output unit, and configure one memory area for each logic macro 21. Therefore, the write data signal, address signal, and command signal shown in FIG. 3 are not simultaneously output from the logic macro 21 to the plurality of memory macros 11.
  • the switch fabric 13 can be configured using the same AND circuit 13a for the write data signal, the address signal, and the command signal output from the logic macro 21.
  • all the memory macros 11 in the semiconductor programmable device 10 shown in FIG. 1B constitute one memory area. Therefore, a plurality of different logic macros 21 do not instruct the separate memory macros 11 to simultaneously read data. That is, the plurality of memory macros 11 did not output read data signals at the same time.
  • a plurality of logic macros 21 instruct different memory macros 11 to simultaneously read data, and a plurality of memory macros 11 can simultaneously output read data signals so that the semiconductor programmable device 10 has a plurality of memory regions. It can be set as the structure divided
  • FIG. 5 is a block diagram showing a configuration of a semiconductor integrated circuit device including a semiconductor programmable device divided into a plurality of memory areas.
  • the memory macro 11 in the semiconductor programmable device 10 shown in FIG. 1B is divided into a memory region 1 and a memory region 2.
  • the memory area 1 and the memory area 2 can be separated by providing an output switch in the switch fabric 33.
  • FIG. 6 is a block diagram showing a configuration of the switch fabric 33 shown in FIG.
  • the switch fabric 33 includes an output switch 34 on the output side of the AND circuit 13a. Thereby, the memory area 1 and the memory area 2 shown in FIG. 5 are electrically separated.
  • the logic macro is connected to the memory area 1 or the memory area 2 via the memory input / output unit 12. Therefore, the logic macro connected to the memory area 1 and the logic macro connected to the memory area 2 can independently perform a read operation. As a result, even when a plurality of logic macros perform a read operation at the same time, the memory macro in the memory area 1 and the memory macro in the memory area 2 output the read data signal at the same time in each memory area. A read data signal can be transferred.
  • the memory macro 11 is an SRAM memory macro having 1k words and 16 bits. However, the memory macro 11 may have an arbitrary word and bit configuration.
  • the memory in the memory macro 11 is an SRAM, but this may be a DRAM (Dynamic Random Access Memory). Since DRAM has a small circuit area, a larger capacity memory can be mounted. Moreover, it is good also as non-volatile memories, such as flash memory, MRAM (Magnetorescent Random Access Memory), and ReRAM (Resistance Random Access Memory). By using the non-volatile memory, it is possible to stop the power supply of the memory area that is not used temporarily and enter the power saving mode. In this embodiment, the case where the memory macro 11 is a 4 ⁇ 4 two-dimensional array has been described. However, the size of the two-dimensional array is not limited to a 4 ⁇ 4 two-dimensional array.
  • the switch fabric 13 uses the AND circuit 13a having a smaller circuit scale than the selector as a circuit for transferring signals. Thereby, the area of the switch fabric 13 can be reduced. Further, the switch fabric 13 does not need to switch the transfer destination of the input signal. Thereby, the power consumption generated in the switch fabric 13 can be reduced.
  • the semiconductor integrated circuit device in which the semiconductor programmable device and the logic device are integrated on the same chip has been described.
  • a semiconductor integrated circuit device in which a semiconductor programmable device and a logic device are integrated on different chips and these chips are stacked will be described.
  • FIG. 7 is a block diagram showing the configuration of the semiconductor integrated circuit device according to the present embodiment.
  • the logic device 60 and the semiconductor programmable device 50 are stacked.
  • the memory input / output unit 12 is arranged around the memory macro 11. Was arranged.
  • the semiconductor programmable device 50 and the logic device 60 are integrated on different chips, and these chips are stacked. Therefore, the memory input / output unit 52 can be arranged for each memory macro 51 in the semiconductor programmable device 50.
  • signal transfer between the semiconductor programmable device 50 and the logic device 60 is performed via a memory input / output unit 52 and a logic input / output unit 62 provided for each memory macro 51. That is, since the memory input / output unit 52 is not shared by the plurality of memory macros 51, the memory input / output unit 52 is provided between the semiconductor programmable device 50 and the logic device 60 as compared with the semiconductor integrated circuit device described in the first embodiment. The amount of signal transfer can be increased.
  • a third embodiment of the present invention will be described. In the first embodiment and the second embodiment, the case where the semiconductor programmable device is configured by a memory macro has been described. In this embodiment, the semiconductor programmable device is configured by a processor.
  • FIG. 8 is a diagram showing a third embodiment of a semiconductor integrated circuit device provided with a semiconductor programmable device.
  • the semiconductor integrated circuit device shown in FIG. 8 differs from the semiconductor integrated circuit device shown in FIG. 1B in the following points. That is, the memory macro 11 in the semiconductor programmable device 10 shown in FIG. 1B is replaced with a processor 81, and the memory device 90 including the memory macro 91 is arranged around the semiconductor programmable device 80.
  • the processor 81 is, for example, a 16-bit RISC (Reduced Instruction Set Computer) processor.
  • FIG. 9 is a block diagram showing the configuration of the switch fabric according to the present embodiment.
  • the switch fabric 113 shown in FIG. 9 is different from the switch fabric 13 shown in FIG. 4 in that an AND circuit 13a included in the switch fabric 13 is an OR circuit 113a.
  • FIG. 10 is a block diagram showing a configuration of a memory macro of a semiconductor programmable device according to the fourth embodiment of the present invention.
  • the memory macro 111 shown in FIG. 10 is different from the memory macro 11 shown in FIG. 2 in that the OR circuit 11i shown in FIG. 2 is an AND circuit 111i. In the memory macro 111 shown in FIG. 10, the output signal from the control unit 111a is directly input to the AND circuit 111i.
  • the output signal from the control unit 111a is at a high level, so the read data output by the control unit 111a The signal is output as it is from the AND circuit 111i.
  • the output signal from the control unit 111a is at a low level.
  • the memory macros 111 other than the memory macro 111 outputting the read data signal output a signal in which all bits are at a low level.
  • a signal input to the switch fabric 113 from a direction other than the direction of transfer from the memory macro 111 that outputs the read data signal is a low-level signal.
  • the read data signal is output as it is by the OR circuit 113a and transferred to the adjacent switch fabric 113.
  • all bits transferred by the switch fabric 113 are output by the OR circuit, but this may be a combination of an output bit by the AND circuit and an output bit by the OR circuit.
  • a low level signal is output except for the memory macro that outputs the read data signal.
  • a high-level signal may be output except for the memory macro that outputs the read data signal.
  • the switch fabric 113 includes the OR circuit 113a having a smaller circuit scale than the selector as a circuit for transferring signals.
  • the switch fabric includes an AND circuit or an OR circuit.
  • the semiconductor programmable device 300 according to the present embodiment has a configuration in which switch fabrics 313A including NAND circuits and switch fabrics 313B including NOR circuits are alternately arranged.
  • FIG. 12 is a block diagram illustrating a configuration of the switch fabric 313A including the NAND circuit according to the present embodiment.
  • the switch fabric 313A including the NAND circuit is different from the switch fabric 13 illustrated in FIG. 4 in that the AND circuit 13a included in the switch fabric 13 is a NAND circuit 320.
  • FIG. 13 is a block diagram illustrating a configuration of a switch fabric 313B including a NOR circuit according to the present embodiment.
  • the switch fabric 313B including the NOR circuit is different from the switch fabric 113 illustrated in FIG. 9 in that the OR circuit 113a included in the switch fabric 113 is a NOR circuit 330.
  • the semiconductor programmable device 300 according to the present embodiment includes a memory macro 311 connected to each switch fabric 313.
  • the configuration of the memory macro 311A connected to the switch fabric 313A including the NAND circuit is the same as the configuration of the memory macro 11 according to the first embodiment illustrated in FIG. Therefore, the memory macro 311A that is not the target of data reading outputs a signal in which all bits are at a high level.
  • the configuration of the memory macro 311B connected to the switch fabric 313B having the NOR circuit is the same as the configuration of the memory macro 111 according to the fourth embodiment shown in FIG. Therefore, the memory macro 311B that is not the target of data reading outputs a signal in which all bits are at a low level.
  • the read data signal output from the memory macro 311 is inverted every time it passes through the switch fabric 313A having a NAND circuit or the switch fabric 313B having a NOR circuit.
  • the memory input / output unit 312 outputs the read data signal as a read data signal without or inverting the input signal according to the number of switch fabrics 313 through which the input signal has passed.
  • the memory input / output unit 312 first stores the address of the memory macro 311 that outputs the read data signal. This address is an address on the wiring matrix constituting the semiconductor programmable device 300 and is included in the address signal output from the logic macro 21.
  • the memory input / output unit 312 derives the number of switch fabrics 313 through which the input signal has passed, from the address of the switch fabric 313 to which the memory input / output unit 312 is connected and the address of the memory macro 311 that outputs the read data signal. .
  • the memory input / output unit 312 inverts the input signal and outputs the inverted signal to the logic macro 21 as a read data signal.
  • the memory input / output unit 312 outputs the input signal as it is to the logic macro 21 as a read data signal.
  • the switch fabric 313 includes the NAND circuit 320 or the NOR circuit 330 having a smaller circuit scale than the selector as a circuit for transferring signals. Thereby, the area of the switch fabric 313 can be reduced. Moreover, the operation
  • a semiconductor programmable device includes a plurality of switch fabrics that are provided at intersections of a plurality of row wirings and a plurality of column wirings laid on a chip and transfer input data signals.
  • a plurality of circuit blocks that are directly connected to each of the plurality of switch fabrics and input / output data signals through the plurality of switch fabrics, and the switch fabric performs AND operation of the plurality of input signals.
  • An AND circuit is provided for each bit.
  • the circuit block When the other circuit block outputs a data signal, the circuit block outputs a high level signal in which all bits are high level, and the switch fabric is directly connected.
  • Data input from the connected circuit block and the adjacent switch fabric on the row wiring and column wiring Receives the signal and a high level signal to the AND circuit, and outputs the signal after the AND operation by the AND circuit.
  • a semiconductor programmable device includes a plurality of switch fabrics that are provided at intersections of a plurality of row wirings and a plurality of column wirings laid on a chip and transfer input data signals And a plurality of circuit blocks that are directly connected to each of the plurality of switch fabrics and input / output data signals via the plurality of switch fabrics, and the switch fabric performs an OR operation on the plurality of input signals.
  • An OR circuit is provided for each bit. When the other circuit block outputs a data signal, the circuit block outputs a low level signal in which all bits are low level, and the switch fabric is directly connected.
  • a signal transfer method in a semiconductor programmable device is provided at intersections of a plurality of row wirings and a plurality of column wirings laid on a chip, and transfers input data signals.
  • a signal transfer method in a semiconductor programmable device having a plurality of switch fabrics and a plurality of circuit blocks that are directly connected to each of the plurality of switch fabrics and input / output data signals via the plurality of switch fabrics,
  • a block When a block outputs a data signal from another circuit block, a process for outputting a high-level signal in which all bits are high-level bits, a circuit block in which the switch fabric is directly connected, and row wiring Data signals input from adjacent switch fabrics on the top and column wiring And it performs an AND operation of the high-level signal for each bit, performs the processing of outputting a signal after the AND operation.
  • a signal transfer method in a semiconductor programmable device transfers an input data signal provided at an intersection of a plurality of row wirings and a plurality of column wirings laid on a chip.
  • a signal transfer method in a semiconductor programmable device having a plurality of switch fabrics and a plurality of circuit blocks that are directly connected to each of the plurality of switch fabrics and input / output data signals via the plurality of switch fabrics,
  • a block When a block outputs a data signal from another circuit block, a process for outputting a low level signal in which all bits are low level bits, a switch fabric connected to a directly connected circuit block, and row wiring Data signals input from adjacent switch fabrics on the top and column wiring And performs an OR operation of the low-level signal for each bit, it performs the processing of outputting a signal after the OR operation.
  • the present invention can be applied to a semiconductor programmable device in which a plurality of circuit blocks including processors and memories are integrated.

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Abstract

L'invention concerne un dispositif programmable à semi-conducteurs à surface de puce réduite et faible consommation. Ainsi, le dispositif programmable à semi-conducteurs possède une pluralité de pistes disposées en rangées et en colonnes sur la puce, une pluralité de matrices de commutation aux points d'intersection entre les pistes disposées en lignes et les pistes disposées en colonnes de façon à transférer les signaux de données reçus, et une pluralité de blocs de circuit directement connectés à chaque matrice de commutation de façon à assurer les opérations d'entrée/sortie des signaux de données via la pluralité de matrices de commutation, les blocs de circuit produisant des signaux de données fictives lorsqu'un autre bloc de circuit produit les signaux de données, et les matrices de commutation calculant les signaux de données et les signaux de données fictives pour produire les signaux de données.
PCT/JP2009/066578 2008-09-16 2009-09-15 Dispositif programmable à semi-conducteurs et procédé de transfert de signal dans un dispositif programmable à semi-conducteurs WO2010032865A1 (fr)

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CN108469963A (zh) * 2018-03-28 2018-08-31 天津中德应用技术大学 一种集成尺寸可调节放置机构的芯片编程器
CN108469963B (zh) * 2018-03-28 2023-05-26 天津中德应用技术大学 一种集成尺寸可调节放置机构的芯片编程器

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