WO2010029939A1 - 太陽電池モジュールの製造方法 - Google Patents
太陽電池モジュールの製造方法 Download PDFInfo
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- WO2010029939A1 WO2010029939A1 PCT/JP2009/065730 JP2009065730W WO2010029939A1 WO 2010029939 A1 WO2010029939 A1 WO 2010029939A1 JP 2009065730 W JP2009065730 W JP 2009065730W WO 2010029939 A1 WO2010029939 A1 WO 2010029939A1
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- electrode layer
- metal electrode
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- pinhole
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Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Definitions
- This invention relates to the manufacturing method of a solar cell module provided with a reverse voltage repair process.
- a thin-film solar cell module includes a transparent electrode, a semiconductor layer, and a metal electrode that are sequentially formed on a transparent substrate.
- reverse voltage a voltage opposite to the photovoltaic force generated in the semiconductor layer
- the microscopic short circuit occurs when a part of the semiconductor layer has a low resistance, or when a minute pinhole is formed as a result of the entry of a small foreign substance. Even if a reverse voltage is applied to the location where such a microscopic short circuit occurs, the metal electrode material is not heated to such a high temperature that it evaporates, so the microscopic short circuit cannot be removed.
- This invention is made
- the method for manufacturing a solar cell module includes a step of sequentially forming a transparent electrode layer, a semiconductor layer, and a metal electrode layer on a main surface of a transparent substrate, and a step of forming a resin layer on the metal electrode layer By applying a voltage opposite to the photovoltaic force generated in the semiconductor layer between the transparent electrode layer and the metal electrode layer, a part of the metal electrode layer is formed in the pinhole formed in the resin layer.
- the gist includes providing a step of exposing and a step of removing a part of the metal electrode layer by etching a part of the metal electrode layer using the resin layer as a mask.
- the metal electrode layer cannot be evaporated because the short circuit occurring between the transparent electrode layer and the metal electrode layer is microscopic. Even if it exists, it removes by evaporating a part of resin layer, and a pinhole is formed in the resin layer. Therefore, the part which has generated the microscopic short circuit among metal electrode layers can be exposed in a pinhole. By removing the exposed metal electrode layer, that is, the portion of the metal electrode layer that is causing the microscopic short-circuit by etching, the microscopic short-circuit between the transparent electrode and the metal electrode is generated. Can be suppressed.
- the step of sequentially forming a transparent electrode layer, a semiconductor layer, and a metal electrode layer on the main surface of the transparent substrate is opposite to the photovoltaic power generated in the semiconductor layer.
- a step of forming a first pinhole in the metal electrode layer by applying a voltage in a direction between the transparent electrode layer and the metal electrode layer, and forming a resin layer on the metal electrode layer and in the first pinhole A step of exposing a part of the metal electrode layer in the second pinhole formed in the resin layer by applying a reverse voltage between the transparent electrode layer and the metal electrode layer, and masking the resin layer and a step of removing a part of the metal electrode layer by etching a part of the metal electrode layer.
- the semiconductor layer includes a first semiconductor layer, a light-transmitting conductive layer, and a second semiconductor layer sequentially formed on the transparent electrode.
- One pinhole may penetrate at least the metal electrode layer and the second semiconductor layer.
- the present invention it is possible to provide a method for manufacturing a solar cell module that can suppress the occurrence of a microscopic short circuit between a transparent electrode and a metal electrode.
- FIG. 1 is a cross-sectional view of a solar cell module 10 according to the first embodiment of the present invention.
- FIG. 2 is an overview of the solar cell module 10 according to the first embodiment of the present invention.
- FIG. 3 is a view for explaining a manufacturing process of the solar cell module 10 according to the first embodiment of the present invention (No. 1).
- FIG. 4 is a view for explaining a manufacturing process of the solar cell module 10 according to the first embodiment of the present invention (No. 2).
- FIG. 5 is a view for explaining a manufacturing process of the solar cell module 10 according to the first embodiment of the present invention (No. 3).
- FIG. 6 is a cross-sectional view of a solar cell module 30 according to the second embodiment of the present invention.
- FIG. 1 is a cross-sectional view of a solar cell module 10 according to the first embodiment of the present invention.
- FIG. 2 is an overview of the solar cell module 10 according to the first embodiment of the present invention.
- FIG. 3 is a view for explaining a
- FIG. 7 is a view for explaining a manufacturing process of the solar cell module 30 according to the second embodiment of the present invention (No. 1).
- FIG. 8 is a view for explaining a manufacturing process of the solar cell module 30 according to the second embodiment of the present invention (No. 2).
- FIG. 9 is a diagram for explaining a manufacturing process for the solar cell module 30 according to the second embodiment of the present invention (No. 3).
- FIG. 1 is an enlarged cross-sectional view of a solar cell module 10 according to the first embodiment.
- the solar cell module 10 includes a transparent substrate 1, a transparent electrode layer 2, a semiconductor layer 3, a metal electrode layer 4, and a resin layer 5.
- the transparent electrode layer 2, the semiconductor layer 3, the metal electrode layer 4, and the resin layer 5 are sequentially formed on the main surface of the transparent substrate 1.
- the current generated in the semiconductor layer 3 flows through the solar cell module 10 in the first direction.
- the transparent substrate 1 is a single substrate of the solar cell module 10.
- the transparent electrode layer 2 is laminated on the main surface of the transparent substrate 1.
- the transparent electrode layer 2 is composed of a metal oxide having conductivity and translucency.
- indium oxide (In 2 O 3 ), zinc oxide (ZnO), titanium oxide (TiO 2 ), or tin oxide (SnO 2 ) can be used as the transparent electrode layer 2.
- the transparent electrode layer 2 may be doped with fluorine (F), tin (Sn), aluminum (Al), iron (Fe), gallium (Ga), niobium (Nb), or the like.
- the first separation groove H i is formed along a second direction substantially orthogonal to the first direction.
- the bottom surface of the first isolation trench H i is constituted by a transparent substrate 1.
- the semiconductor layer 3 is laminated on the transparent electrode layer 2.
- the semiconductor layer 3 has a pin junction (not shown) formed by stacking a p-type semiconductor layer, an i-type semiconductor layer as a power generation layer, and an n-type semiconductor layer from the transparent substrate 1 side. Accordingly, the photovoltaic current generated in the semiconductor layer 3 flows from the transparent electrode layer 2 toward the metal electrode layer 4 in the semiconductor layer 3.
- a silicon-based semiconductor material such as amorphous silicon or microcrystalline silicon can be used.
- the semiconductor layer 3 is separated on the transparent electrode layer 2 by the second separation groove Hii .
- the second separation groove H ii is formed along the second direction.
- the bottom surface of the second separation groove H ii is configured by the transparent electrode layer 2.
- the metal electrode layer 4 is laminated on the semiconductor layer 3.
- a metal material such as conductive silver (Ag) can be used.
- the metal electrode layer 4 is also formed inside the second separation groove Hii .
- the semiconductor layer 3 and the metal electrode layer 4 are separated on the transparent electrode layer 2 by the third separation groove Hiii .
- the third separation groove H iii is formed along the second direction.
- the bottom surface of the third separation groove H iii is constituted by the transparent electrode layer 2.
- the resin layer 5 is laminated on the metal electrode layer 4.
- the resin layer 5 is made of an insulating resin material.
- acrylic (PMMA), polycarbonate (PC), polyethylene (PE), polyethylene terephthalate (PET), polyvinyl chloride (PVC), polyester (ABS), epoxy (EP), or the like is used. it can.
- the resin layer 5 is preferably evaporated at a temperature lower than the temperature at which the metal electrode layer 4 is evaporated by heating.
- the resin layer 5 is also formed inside the third separation groove Hiii .
- the solar cell module 10 has a first pinhole PH i and a second pinhole PH ii as shown in FIG.
- the first pinhole PH i penetrates the semiconductor layer 3, the metal electrode layer 4, and the resin layer 5.
- the second pinhole PH ii penetrates the metal electrode layer 4 and the resin layer 5. The process of forming the first pinhole PH i and the second pinhole PH ii will be described later.
- the solar cell module 10 having the above configuration may constitute a sealed body sealed with a sealing material 6 and a back surface side protective material 7.
- the first pinhole PH i and the second pinhole PH ii are filled with the sealing material 6.
- resins such as EVA, EEA, PVB, silicone, urethane, acrylic, and epoxy can be used.
- the back surface side protective material 7 a resin film such as PET, a laminated film having a structure in which an Al foil is sandwiched between resin films, and the like can be used.
- the sealing body may be reinforced by fixing the outer peripheral portion with the elastic body 8 and the frame body 9.
- the elastic body 8 silicone rubber, butyl rubber, or the like can be used.
- the frame body 9 an Al frame, an iron frame, a SUS frame, or the like can be used.
- the transparent electrode layer 2 is laminated on the main surface of the transparent substrate 1.
- a part of the transparent electrode layer 2 is removed along the second direction.
- a first separation groove H i for separating the transparent electrode layer 2 is formed.
- the first isolation trench H i can also be formed by laminating a transparent electrode layer 2 using a mask.
- FIG. 3 (c) by using a CVD method to form a first semiconductor layer 3 inside the upper transparent electrode layer 2 and the first isolation trench H i.
- the semiconductor layer 3 is removed along the second direction by irradiating the formed semiconductor layer 3 with laser light.
- a second separation groove H ii for separating the semiconductor layer 3 is formed.
- pinholes PH i ′ are formed in the semiconductor layer 3.
- foreign matter B may adhere on the semiconductor layer 3 when the semiconductor layer 3 is formed.
- a pinhole PH ii ′ is formed in the semiconductor layer 3.
- the metal electrode layer 4 is formed on the semiconductor layer 3 and inside the second separation groove Hii . Specifically, sputtering silver in the semiconductor layer 3 and on the second isolation trench H ii. In this case, the metal electrode layer 4 is also formed inside the pinhole PH i ′ and inside the pinhole PH ii ′. Subsequently, the semiconductor layer 3 and the metal electrode layer 4 are removed along the second direction by irradiating the opposite side of the first separation groove H i with the second separation groove H ii interposed therebetween. Thereby, as shown in FIG. 4B, a third separation groove H iii for separating the semiconductor layer 3 and the metal electrode layer 4 is formed.
- the resin layer 5 is formed on the metal electrode layer 4 and inside the third separation groove Hiii .
- a resin material dissolved in an organic solvent is applied by a spray method, a spin coating method, a printing method, or the like.
- the thickness of the resin layer 5 formed on the metal electrode layer 4 can be appropriately set in consideration of easiness of evaporation in a reverse voltage repair process described later and etching resistance in an etching process described later.
- the first contact hole CH i and the second contact hole CH ii that penetrate the resin layer 5 are formed by using a mask. Specifically, as shown in FIG. 4C, the first contact hole CH i is formed so that a part of one metal electrode layer 4 is exposed. The second contact hole CH ii is formed so that a part of another adjacent metal electrode layer 4 is exposed.
- the resin layer 5 is cured by heating the resin layer 5 at about 100 ° C. for about 10 minutes.
- the first electrode 21 is inserted into the first contact hole CH i .
- the second electrode 22 is inserted into the second contact hole CH ii.
- a voltage opposite to the photovoltaic force generated in the semiconductor layer 3 is applied between the transparent electrode layer 2 and the metal electrode layer 4.
- the first electrode 21 is set to a high potential and the second electrode 22 is set to a low potential.
- the process of applying the reverse voltage is referred to as “reverse voltage repair process”.
- This reverse voltage repair process 'and the metal electrode layer 4 formed inside, the pinhole PH ii' pinhole PH i portion for generating a microscopic short circuit due to the metal electrode layer 4 formed inside (hereinafter, "Microscopic short-circuited part") and are heated.
- the metal electrode layer 4 formed inside the heated pinhole PH i ′ evaporates. As a result, the first pinhole PH i penetrating the semiconductor layer 3, the metal electrode layer 4, and the resin layer 5 is formed.
- the microscopic short-circuit portion of the metal electrode layer 4 is less likely to flow current than the metal electrode layer 4 formed inside the pinhole PH i ′, the micro-short-circuit portion of the metal electrode layer 4 is Hard to be heated. For this reason, the temperature of the microscopic short-circuit portion of the metal electrode layer 4 does not reach the temperature at which the metal electrode layer 4 evaporates. However, since the evaporation temperature of resin is lower than that of metal, the resin layer 5 formed on the pinhole PH ii ′ evaporates. As a result, as shown in FIG. 5B, a pinhole PH ii ′′ is formed on the pinhole PH ii ′ of the resin layer 5. A part of the metal electrode layer 4 is formed inside the pinhole PH ii ′′. Is exposed.
- the metal electrode layer 4 exposed inside the pinhole PH ii ′′ is removed by etching using the resin layer 5 as a mask.
- the metal electrode layer 4 exposed inside the pinhole PH ii ′′ is etched with a hydrochloric acid aqueous solution for about 3 minutes. As a result, the second pinhole PH ii penetrating the metal electrode layer 4 and the resin layer 5 is formed.
- the solar cell module 10 manufactured as described above is sealed with the sealing material 6 and the back surface side protective material 7.
- the first pinhole PH i and the second pinhole PH ii are filled with the sealing material 6.
- the manufacturing method of the solar cell module 10 according to the first embodiment of the present invention is formed in the resin layer 5 by applying a reverse voltage between the transparent electrode layer 2 and the metal electrode layer 4 in the reverse voltage repair process.
- a part of the resin layer 5 is evaporated by the microscopic short-circuit portion of the metal electrode layer 4 to form a pinhole PH ii ′′ in the resin layer 5. That is, the micro-short circuit portion of the metal electrode layer 4 is formed. Can be exposed in the pinhole PH ii ′′. Therefore, the microscopic short circuit between the transparent electrode layer 2 and the metal electrode layer 4 can be accurately removed by removing the micro short circuit part of the metal electrode layer 4 by etching.
- the resin layer 5 in which the pinhole PH ii ′′ is formed can be used as a mask. Therefore, the productivity of the solar cell module can be improved. .
- a metal material constituting the metal electrode layer 4 may enter between the microcrystalline silicon grains.
- the microcrystalline silicon semiconductor layer has a locally low resistance, which may reduce the output of the solar cell module.
- the semiconductor layer may be locally crystallized when the semiconductor layer is removed by laser light irradiation. In this case, the crystallized semiconductor layer has a low resistance and may reduce the output of the solar cell module.
- the present invention is also suitable for removing the metal electrode layer 4 on the semiconductor layer with reduced resistance. By removing the metal electrode layer 4, it is possible to suppress a decrease in the output of the solar cell module.
- FIG. 6 is a cross-sectional view of the solar cell module 30 according to the second embodiment. In the following, differences from the first embodiment will be mainly described.
- the resin layer 5 is filled in the first pinhole PH i ′ according to the present embodiment.
- the semiconductor layer 3 includes a first semiconductor layer 3a, a translucent conductive layer 3b, and a second semiconductor layer 3c.
- the first semiconductor layer 3a generates photogenerated carriers by light incident from the transparent electrode layer 2 side. In addition, the first semiconductor layer 3a generates photogenerated carriers by light reflected by a translucent conductive layer 3b described later.
- the first semiconductor layer 3a has a pin junction in which a p-type semiconductor, an i-type semiconductor, and an n-type semiconductor are stacked from the substrate 1 side (not shown).
- the i-type semiconductor constitutes a power generation layer in the first semiconductor layer 3a.
- an amorphous silicon semiconductor such as a-Si or a-SiC can be used.
- the first semiconductor layer 3a is filled in the first isolation trench H i.
- the translucent conductive layer 3b has translucency and conductivity.
- the translucent conductive layer 3b transmits part of the light transmitted through the first semiconductor layer 3a to the second semiconductor layer 3c side, and transmits part of the light transmitted through the first semiconductor layer 3a to the first semiconductor layer 3a. Reflect to the side.
- a metal oxide such as ZnO, ITO, or TiO 2 can be used.
- the translucent conductive layer 3b may be doped with a dopant such as Al.
- the second semiconductor layer 3c generates photogenerated carriers by light transmitted through the transparent electrode layer 2, the first semiconductor layer 3a, and the translucent conductive layer 3b among the light incident from the transparent electrode layer 2 side.
- the second semiconductor layer 3c has a pin junction in which a p-type semiconductor, an i-type semiconductor, and an n-type semiconductor are stacked from the transparent substrate 1 side (not shown).
- the i-type semiconductor constitutes a power generation layer in the second semiconductor layer 3c.
- a microcrystalline silicon-based semiconductor such as ⁇ c-Si or ⁇ c-SiGe can be used as the i-type semiconductor layer in the second semiconductor layer 3c.
- the transparent electrode layer 2 is laminated on the main surface of the transparent substrate 1.
- the transparent electrode layer 2 is removed along the second direction.
- a first separation groove H i for separating the transparent electrode layer 2 is formed.
- a first semiconductor layer 3a, a translucent conductive layer 3b, and a second semiconductor layer 3c are sequentially formed on the transparent electrode layer 2 by an RF plasma CVD method or the like. Thereby, the semiconductor layer 3 is formed.
- the first semiconductor layer 3a and the second semiconductor layer 3c are formed by a plasma CVD method.
- the translucent conductive layer 3b is formed by sputtering or the like.
- the semiconductor layer 3 By irradiating the formed semiconductor layer 3 with laser light, the semiconductor layer 3 is removed along the second direction. Thereby, as shown in FIG. 7D, a second separation groove H ii for separating the semiconductor layer 3 is formed.
- the pinhole PH i ′ is formed in the semiconductor layer 3 by removing the foreign matter A taken in the semiconductor layer 3 from the semiconductor layer 3 as in the first embodiment.
- foreign matter B may adhere on the semiconductor layer 3 when the second semiconductor layer 3 c is formed. As the foreign matter B comes off from the second semiconductor layer 3c, a pinhole PH ii ′ is formed in the second semiconductor layer 3c.
- the metal electrode layer 4 is formed on the semiconductor layer 3 in the second separation groove H ii and in the pinhole PH i ′. Subsequently, the semiconductor electrode 3 and the metal electrode layer 4 are removed along the second direction by irradiating the metal electrode layer 4 with laser light. As a result, as shown in FIG. 8B, a third separation groove H iii for separating the semiconductor layer 3 and the metal electrode layer 4 is formed.
- the first electrode 21 is set to a high potential and the second electrode 22 is set to a low potential.
- the metal electrode layer 4 formed inside the pinhole PH i ′ is heated and evaporated.
- the first pinhole PH i penetrating the semiconductor layer 3 and the metal electrode layer 4 is formed.
- the micro short circuit portion formed in the pinhole PH ii ′ is heated, the temperature of the micro short circuit portion formed in the pin hole PH ii ′ does not reach the evaporation temperature. Accordingly, the pinhole PH ii ′ remains covered with the metal electrode layer 4.
- the resin layer 5 is formed inside the third isolation groove H iii interior and first pinhole PH i.
- the first contact hole CH i and the second contact hole CH ii are formed in the resin layer 5.
- the resin layer 5 is cured by heating the resin layer 5 at about 100 ° C. for about 10 minutes.
- the first electrode 21 is inserted into the first contact hole CH i .
- the second electrode 22 is inserted into the second contact hole CH ii.
- a reverse voltage is applied between the transparent electrode layer 2 and the metal electrode layer 4.
- the microscopic short-circuit portion of the metal electrode layer 4 formed inside the pinhole PH ii ′ is heated to a temperature lower than the evaporation temperature.
- the resin layer 5 on the pinhole PH ii ′ of the resin layer 5 evaporates.
- a pinhole PH ii ′′ is formed on the pinhole PH ii ′ of the resin layer 5. A part of the metal electrode layer 4 is exposed inside the pinhole PH ii ′′.
- the metal electrode layer 4 exposed inside the pinhole PH ii ′′ is removed by etching the metal electrode layer 4 using the resin layer 5 as a mask.
- a second pinhole PH ii that penetrates the metal electrode layer 4 and the resin layer 5 is formed.
- the manufacturing method of the solar cell module 30 according to the second embodiment of the present invention includes a reverse voltage repair process as a pre-process of the process of forming the resin layer 5.
- the reliability of the solar cell module 30 can be improved by suppressing the translucent conductive layer 3b from being deteriorated by moisture.
- the metal electrode layer is formed by using a conductive metal material such as silver.
- a coating-type electrode can also be used as the metal electrode layer.
- any one of silver particles, aluminum particles (Al), and copper particles (Cu), or a metal paste in which two or more particles are mixed with a resin can be used. This metal paste is applied on the semiconductor layer.
- the coated electrode is formed by firing the coated metal paste. Examples of the application method include screen printing, spin coating, and spraying.
- the semiconductor layer 3 includes the pin junction, but is not limited thereto.
- the semiconductor layer 3 may include a pn junction formed by a p-type semiconductor and an n-type semiconductor.
- the semiconductor layer 3 includes one pin junction, but the present invention is not limited to this.
- the semiconductor layer 3 may include two or more pin junctions.
- the semiconductor layer 3 includes two pin junctions, but the present invention is not limited to this.
- the semiconductor layer 3 may include one or more pin junctions.
- the semiconductor layer 3 is mainly composed of an amorphous silicon semiconductor, but is not limited to this.
- the semiconductor layer 3 may contain a crystalline silicon semiconductor as a main component.
- crystalline silicon includes microcrystalline silicon and polycrystalline silicon.
- the first semiconductor layer 3a is mainly composed of an amorphous silicon semiconductor, but is not limited thereto.
- the first semiconductor layer 3a may contain a crystalline silicon semiconductor as a main component.
- the second semiconductor layer 3c is mainly composed of a microcrystalline silicon semiconductor, but is not limited thereto.
- the second semiconductor layer 3c may contain an amorphous silicon semiconductor as a main component.
- the solar cell module according to the present invention will be specifically described with reference to examples.
- the present invention is not limited to those shown in the following examples. In the range which does not change the gist, it can change suitably and can carry out.
- the solar cell module according to the example was manufactured as follows.
- An SnO 2 layer was formed on the glass substrate.
- a part of the SnO 2 layer was removed by irradiating Nd: YAG laser light from the SnO 2 layer side.
- Nd YAG laser light
- a fundamental wave having a wavelength of 1064 nm was used as the Nd: YAG laser light.
- the width of the first separation groove was 40 ⁇ m.
- a p-type amorphous silicon semiconductor layer, an i-type amorphous silicon semiconductor layer, and an n-type amorphous silicon semiconductor layer were sequentially stacked on the SnO 2 layer using an RF plasma CVD method.
- the thickness of the i-type amorphous silicon semiconductor was 300 nm.
- a ZnO layer containing Al as a dopant was formed on the n-type amorphous silicon semiconductor layer by using a DC sputtering method.
- the thickness of the ZnO layer was 50 nm.
- a p-type microcrystalline silicon semiconductor, an i-type microcrystalline silicon semiconductor, and an n-type microcrystalline silicon semiconductor were sequentially stacked on the ZnO layer by using an RF plasma CVD method.
- the thickness of the i-type microcrystalline silicon semiconductor was 2000 nm.
- Table 1 shows the conditions for forming each semiconductor layer by the RF plasma CVD method.
- Nd YAG laser light was irradiated from the glass substrate side to remove part of each semiconductor layer and ZnO layer. Thereby, the 2nd separation groove was formed.
- Nd YAG laser light
- a second harmonic having a wavelength of 532 nm was used as the Nd: YAG laser light.
- the width of the second separation groove was 50 ⁇ m.
- an Ag layer was formed on the n-type microcrystalline silicon semiconductor using a DC sputtering method.
- the thickness of the Ag layer was 200 nm.
- the Nd: YAG laser light is irradiated from the glass substrate side to the position on the opposite side of the first separation groove across the second separation groove, whereby a part of each of the Ag layer, each semiconductor layer, and the ZnO layer is formed. Removed. Thereby, the third separation groove was formed.
- the Nd: YAG laser light a second harmonic having a wavelength of 532 nm was used. The width of the third separation groove was 50 ⁇ m.
- an acrylic resin dissolved in an organic solvent was applied on the Ag layer by a spray method. Thereby, an acrylic resin layer having a thickness of about 15 ⁇ m was formed. At this time, a pair of contact holes for inserting a pair of electrodes was formed by using a mask.
- the Ag layer exposed inside the pinhole was etched with a 5% hydrochloric acid aqueous solution for about 3 minutes. As a result, pinholes penetrating the Ag layer and the acrylic resin layer were formed.
- the characteristic values of the solar cell modules according to the examples were better than the characteristic values of the solar cell modules according to Comparative Example 1 and Comparative Example 2.
- the method for manufacturing a solar cell module according to the present invention can provide a solar cell module capable of suppressing the occurrence of a microscopic short circuit between the transparent electrode and the metal electrode. Useful in the manufacture of battery modules.
- SYMBOLS 1 Transparent substrate, 2 ... Transparent electrode layer, 3 ... Semiconductor layer, 3a ... 1st semiconductor layer, 3b ... Translucent conductive layer, 3c ... 2nd semiconductor layer, 4 ... Metal electrode layer, 5 ... Resin layer, 6 DESCRIPTION OF SYMBOLS ... Sealing material, 7 ... Back surface side protective material, 8 ... Elastic body, 9 ... Frame, 21 ... 1st electrode, 22 ... 2nd electrode, 10, 30 ... Solar cell module, A, B ... Foreign material, Hi ... first separation groove, H ii ... second separation groove, H iii ... third separation groove
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Abstract
Description
(太陽電池モジュールの構成)
以下において、本発明の第1実施形態に係る太陽電池モジュールの構成について、図1を参照しながら説明する。図1は、第1実施形態に係る太陽電池モジュール10の拡大断面図である。
第1実施形態に係る太陽電池モジュール10の製造方法について、図3乃至図5を参照しながら説明する。
本発明の第1実施形態に係る太陽電池モジュール10の製造方法は、逆電圧リペア工程において、透明電極層2と金属電極層4との間に逆電圧を印加することによって、樹脂層5に形成されるピンホールPHii”内において金属電極層4の一部分を露出させる工程と、樹脂層5をマスクとしてエッチングすることによって金属電極層4の一部分を除去する工程とを備える。
(太陽電池モジュールの構成)
以下において、本発明の第2実施形態に係る太陽電池モジュールの構成について、図6を参照しながら説明する。図6は、第2実施形態に係る太陽電池モジュール30の断面図である。以下においては、上記第1実施形態との相違点について主に説明する。
第2実施形態に係る太陽電池モジュール30の製造方法について、図7乃至図9を参照しながら説明する。
本発明の第2実施形態に係る太陽電池モジュール30の製造方法は、樹脂層5を形成する工程の前工程として、逆電圧リペア工程を備える。
本発明は上記の実施形態によって記載したが、この開示の一部をなす論述及び図面はこの発明を限定するものであると理解すべきではない。この開示から当業者には様々な代替実施形態、実施例及び運用技術が明らかとなろう。
以下のようにして、実施例に係る太陽電池モジュールを作製した。
比較例1に係る太陽電池モジュールを作製した。上記実施例との相違点は、アクリル樹脂層の形成工程以降の工程を行わなかった点である。すなわち、比較例1では、逆電圧リペア工程を行わなかった。その他の工程は上記第1実施形態と同様とした。
比較例2に係る太陽電池モジュールを作製した。上記実施例との相違点は、アクリル樹脂層の形成工程及びエッチング工程を行わずに、一般的に行われる逆電圧リペア工程を行った点である。その他の工程は上記第1実施形態と同様とした。
Claims (3)
- 透明基板の主面上に透明電極層、半導体層及び金属電極層を順次形成する工程と、
前記金属電極層上に樹脂層を形成する工程と、
前記半導体層において発生される光起電力とは逆向きの電圧を、前記透明電極層と前記金属電極層との間に印加することによって、前記樹脂層に形成されるピンホール内において前記金属電極層の一部分を露出させる工程と、
前記樹脂層をマスクとして前記金属電極層の前記一部分をエッチングすることによって、前記金属電極層の前記一部分を除去する工程とを備えることを特徴とする太陽電池モジュールの製造方法。 - 透明基板の主面上に透明電極層、半導体層及び金属電極層を順次形成する工程と、
前記半導体層において発生される光起電力とは逆向きの電圧を、前記透明電極層と前記金属電極層との間に印加することによって、前記金属電極層に第1ピンホールを形成する工程と、
前記金属電極層上及び前記第1ピンホール内に樹脂層を形成する工程と、
前記逆電圧を前記透明電極層と前記金属電極層との間に印加することによって、前記樹脂層に形成される第2ピンホール内において前記金属電極層の一部分を露出させる工程と、
前記樹脂層をマスクとして前記金属電極層の前記一部分をエッチングすることによって、前記金属電極層の前記一部分を除去する工程とを備えることを特徴とする太陽電池モジュールの製造方法。 - 前記半導体層は、前記透明電極上に順次形成された第1半導体層、透光性導電層及び第2半導体層を有しており、
前記第1ピンホールを形成する工程において、前記第1ピンホールは、少なくとも前記金属電極層及び前記第2半導体層を貫通することを特徴とする請求項2に記載の太陽電池モジュールの製造方法。
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US12/740,092 US8158454B2 (en) | 2008-09-09 | 2009-09-09 | Method for manufacturing solar cell module |
JP2010528733A JPWO2010029939A1 (ja) | 2008-09-09 | 2009-09-09 | 太陽電池モジュールの製造方法 |
CN200980100613XA CN101809761B (zh) | 2008-09-09 | 2009-09-09 | 太阳能电池组件的制造方法 |
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JP (1) | JPWO2010029939A1 (ja) |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8158454B2 (en) | 2008-09-09 | 2012-04-17 | Sanyo Electric Co., Ltd. | Method for manufacturing solar cell module |
JP2016538722A (ja) * | 2013-11-12 | 2016-12-08 | ピーピージー・インダストリーズ・オハイオ・インコーポレイテッドPPG Industries Ohio,Inc. | 光起電システムおよび光起電システムを製造するためのスプレーコーティング方法 |
US10950391B2 (en) | 2017-09-15 | 2021-03-16 | Kabushiki Kaisha Toshiba | Photoelectric conversion device and manufacturing method and apparatus thereof |
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- 2009-09-09 WO PCT/JP2009/065730 patent/WO2010029939A1/ja active Application Filing
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US10950391B2 (en) | 2017-09-15 | 2021-03-16 | Kabushiki Kaisha Toshiba | Photoelectric conversion device and manufacturing method and apparatus thereof |
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US20100255631A1 (en) | 2010-10-07 |
CN101809761A (zh) | 2010-08-18 |
US8158454B2 (en) | 2012-04-17 |
JPWO2010029939A1 (ja) | 2012-02-02 |
CN101809761B (zh) | 2011-12-28 |
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