WO2010016312A1 - 液晶表示装置の試験方法および液晶表示装置 - Google Patents
液晶表示装置の試験方法および液晶表示装置 Download PDFInfo
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- WO2010016312A1 WO2010016312A1 PCT/JP2009/059714 JP2009059714W WO2010016312A1 WO 2010016312 A1 WO2010016312 A1 WO 2010016312A1 JP 2009059714 W JP2009059714 W JP 2009059714W WO 2010016312 A1 WO2010016312 A1 WO 2010016312A1
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- wiring
- signal
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- liquid crystal
- display panel
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
- H05K1/0268—Marks, test patterns or identification means for electrical inspection or testing
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
- G01R31/2812—Checking for open circuits or shorts, e.g. solder bridges; Testing conductivity, resistivity or impedance
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136254—Checking; Testing
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0404—Matrix technologies
- G09G2300/0408—Integration of the drivers onto the display substrate
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0404—Matrix technologies
- G09G2300/0417—Special arrangements specific to the use of low carrier mobility technology
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
- G09G3/3666—Control of matrices with row and column drivers using an active matrix with the matrix divided into sections
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/361—Assembling flexible printed circuits with other printed circuits
Definitions
- the present invention relates to a test method for a liquid crystal display device including a display panel to which a wiring mounting board for mounting a wiring for supplying a signal for driving the display panel is connected, and a liquid crystal display device using the same.
- Such a display device includes a display panel including a large number of pixels.
- a signal for driving the pixel is supplied from the driver circuit to the display panel.
- This drive circuit is integrated and is provided in a mounting structure such as COF (Chip On Film) and is externally attached to the display panel.
- the driving circuit is directly mounted on the glass substrate of the display panel in the form of COG (Chip On Glass).
- a driving signal mounted on the glass substrate is supplied with a driving signal through wiring mounted on an FPC (Flexible Printed Circuit) connected to the display panel.
- Patent Document 1 discloses a technique for structurally reinforcing an FPC.
- the outer end portions to which stress is applied are reinforced by arranging reinforcing members that are not involved in electrical connection.
- connection portion the reliability of connection is confirmed by inspection after connecting the COF or FPC to the display panel.
- an indentation inspection of a connection portion is mainstream.
- the state of the indentation portion due to thermocompression bonding is examined visually by an automatic machine using a microscope. Specifically, the state such as the depth of the indentation or the width of the indentation is analyzed with a captured image.
- Japanese Patent Publication Japanese Patent Laid-Open No. 5-183247 (published on July 23, 1993)”
- Flat-type display devices have come to be used as display units for various machines because of the advantage of being thin.
- the use of flat panel display devices for in-vehicle display devices or control device display devices has also been promoted.
- a mechanical device equipped with a flat panel display device is often placed in a harsh environment. Passenger cars are exposed to environments such as vibration, high temperature, and low temperature. Also, control devices used in factories and the like are often placed in a similar environment.
- the FPC can reduce damage due to stress.
- the display panel may not be able to display due to disconnection. In such a situation, the operation of the passenger car or the control device is hindered.
- the reliability of connection can be confirmed in the manufacturing process of the display device, but it cannot be confirmed after the display device is shipped as a product. For this reason, even if the COF or FPC is likely to be damaged by stress as a result of continuing to use the display device in the harsh environment as described above, it cannot be confirmed. Therefore, if the display device is continuously used in this state, the COF or FPC will eventually be damaged and the display panel cannot be displayed.
- the present invention has been made in view of the above-mentioned problems, and the object thereof is to provide a display panel and a wiring mounting board such as a flexible mounting board (COF, FPC, etc.) not only in the manufacturing process but also in use.
- An object of the present invention is to provide a test method for a liquid crystal display device and a liquid crystal display device which can confirm the connection state.
- the liquid crystal display device testing method of the present invention includes a display panel to which a wiring mounting board for mounting a signal supply wiring for supplying a signal for driving the display panel is connected.
- the wiring board having the first wiring and the second wiring extending to the display panel side, and the first terminal and the second terminal connected to the first wiring and the second wiring, respectively, and the display
- the display In a state in which the display panel having the first short-circuit wiring connected to the first and second wirings and short-circuiting the first and second wirings is connected to the connection portion between the panel and the wiring mounting substrate.
- a signal is applied to the first terminal, and a signal output from the second terminal is compared with a signal applied to the first terminal.
- a liquid crystal display device of the present invention includes a display panel to which a wiring mounting board for mounting a signal supply wiring for supplying a signal for driving the display panel is connected.
- the wiring mounting board has a first wiring and a second wiring extending to the display panel side, and a first terminal and a second terminal connected to the first wiring and the second wiring, respectively, and the display panel
- the liquid crystal display device has a first short-circuit wiring that is connected to the first and second wirings at a connection portion between the display panel and the wiring mounting substrate, respectively, and short-circuits the first and second wirings.
- the resistance of the first wiring or the second wiring is increased.
- the signal output from the second terminal monitored by the comparison means and the signal applied to the first terminal Will be different. Accordingly, it is possible to detect an abnormality in the first wiring or the second wiring.
- the comparison means monitors the connection state between the display panel and the wiring mounting board, and if the connection state becomes abnormal as a result of the monitoring, the display panel and the wiring mounting board are abnormally connected. It may be fed back to the control means.
- the control means is a signal source connected to the liquid crystal display device. On the control means side, by obtaining connection information between the display panel and the wiring mounting board of the liquid crystal display device, prevention of turning off the backlight or stopping power supply to the liquid crystal display device, etc. Control is possible.
- the signal applying means, the comparing means, and the control means operate when the liquid crystal display device is manufactured or when the liquid crystal display device is used, so that not only the manufacturing process of the liquid crystal display device but also the liquid crystal display device. Even in the use state, the connection state between the display panel and the wiring board can be confirmed.
- the wiring mounting board and the display panel are connected by interposing an intermediate board for mounting wiring for transmitting a signal between the wiring mounting board and the display panel,
- the third and fourth wirings of the intermediate substrate apply a signal to the first terminal in a state where the first and second wirings and the first short-circuiting wiring are connected to each other, and the second terminal And a signal applied to the first terminal may be compared.
- the intermediate board is connected to the wiring board by interposing an intermediate board for mounting wiring for transmitting a signal between the wiring board and the display panel.
- the first and second wirings and the first short-circuiting wiring may be connected to the third and fourth wirings, respectively.
- These methods and apparatuses can detect an abnormality in the third wiring or the fourth wiring in addition to the first wiring or the second wiring.
- the second short-circuit wiring of the intermediate substrate is connected to the fifth and sixth wirings at the connection portion between the intermediate substrate and the wiring mounting substrate, respectively.
- 6 wiring is short-circuited
- the wiring mounting substrate has a third terminal and a fourth terminal connected to the fifth and sixth wirings, respectively, and a signal is applied to the third terminal, A signal output from the fourth terminal may be compared with a signal applied to the third terminal.
- the wiring mounting board includes a fifth wiring and a sixth wiring extending to the intermediate board side, and a third terminal and a fourth terminal connected to the fifth wiring and the sixth wiring, respectively.
- the intermediate board includes a second short-circuit wiring that is connected to the fifth and sixth wirings at a connection portion between the intermediate board and the wiring mounting board and short-circuits the fifth and sixth wirings, respectively.
- the signal applying means may apply a signal to the third terminal
- the comparing means may compare a signal output from the fourth terminal with a signal applied to the third terminal.
- These methods and apparatuses can also detect an abnormality in the fifth wiring or the sixth wiring.
- the signal may be a pulse signal.
- the signal may be a DC signal.
- the resistance of the first wiring or the second wiring is increased, and the direct current output from the second terminal is increased.
- the level of the signal is lower than the level of the DC signal applied to the first terminal. Accordingly, it is possible to detect an abnormality in the first wiring or the second wiring.
- the first and second wirings may be provided at at least one side end of the wiring mounting board.
- the wiring board may be connected via a plurality of the intermediate boards.
- the connection state between the wiring mounting substrate and the intermediate substrate and the connection state between the display panel and the intermediate substrate can be predicted for each intermediate substrate.
- each intermediate substrate may have the pair of the fifth and sixth wirings at both end portions thereof.
- the wiring board may be a printed wiring board
- the intermediate board may be a mounting board on which an integrated circuit for driving a display panel is mounted on a film.
- the test method of the liquid crystal display device of the present invention includes the first wiring and the second wiring extending to the display panel side, and the first terminal and the second terminal connected to the first wiring and the second wiring, respectively.
- the wiring mounting board having a first shorting wiring connected to the first wiring and the second wiring at a connection portion between the display panel and the wiring mounting board, respectively.
- the wiring mounting substrate is connected to the first wiring and the second wiring extending to the display panel side and the first wiring and the second wiring, respectively.
- the display panel has a terminal and a second terminal, and the display panel is connected to the first and second wirings at a connection portion between the display panel and the wiring mounting board, respectively, and shorts the first and second wirings.
- a first short-circuit wiring is provided, and the liquid crystal display device compares signal applying means for applying a signal to the first terminal, a signal output from the second terminal, and a signal applied to the first terminal. Comparing means.
- connection state between the display panel and a wiring mounting board such as a flexible mounting board (COF, FPC, etc.) can be confirmed not only in the manufacturing process but also in use.
- FIG. 6 is a block diagram illustrating a configuration of a liquid crystal display device according to a third embodiment.
- FIGS. 1 to 6 An embodiment of the present invention will be described with reference to FIGS. 1 to 6 as follows.
- FIG. 1 shows a state in which the FPC 2 is connected to the display panel 1 in the liquid crystal display device 30 according to the present embodiment.
- 2A and 2B show the display panel 1 and the FPC 2 that are not connected to each other.
- the driver chip 3 is an integrated drive circuit, and supplies a drive signal to each pixel in order to drive a plurality of pixels included in the display panel 1.
- As the drive signal display data, a selection signal for selecting a scanning line, and the like are prepared.
- Each driver chip 3 is input with various signals according to a driving method such as a clock for controlling the timing of outputting display data and the timing of a selection signal.
- a wiring pattern 4 is formed on the mounting surface of the driver chip 3 in the display panel 1.
- the wiring pattern 4 includes a plurality of wirings (not shown) in order to supply a plurality of signals from the FPC 2 to the driver chip 3.
- short-circuit wirings 5 and 6 are formed at both ends of the portion where the driver chip 3 is disposed, respectively.
- the short-circuit wirings 5 and 6 will be described in detail later.
- the FPC 2 has a wiring pattern 7 formed on a film substrate made of polyimide or the like.
- the wiring pattern 7 is provided corresponding to each driver chip 3 in order to supply the above signals to the driver chip 3, and includes a plurality of wirings (not shown) like the wiring pattern 4. Yes.
- the FPC 2 is connected to the display panel 1 by an ACF (Anisotropic Conductive Film) in a state where the connection end portion is superimposed on the connection end portion of the display panel 1.
- ACF Application Chemical Vapor Deposition Film
- the FPC 2 has test wiring portions 8 and 9.
- the test wiring portions 8 and 9 are formed in the vicinity of both side edges of the FPC 2 so as to sandwich all the wiring patterns 7 from both sides.
- the test wiring unit 8 includes two wirings 8a and 8b arranged side by side.
- the test wiring unit 9 includes two wirings 9a and 9b arranged side by side. One end of each of the wirings 8a, 8b, 9a, 9b extends to the connection end of the FPC 2.
- the other ends of the wirings 8a, 8b, 9a, 9b are connected to terminals T1 to T4 provided at the input side end of the FPC 2, respectively.
- the terminals T1 and T3 are connected to the signal application circuit 31, and the terminals T2 and T4 are connected to the monitor circuit 32.
- the test circuit 33 includes a signal application circuit 31 and a monitor circuit 32, and is connected to a host system 34 described later.
- the aforementioned short-circuit wirings 5 and 6 are formed in a U-shape that forms a rectangle. Both ends of the short-circuit wires 5 and 6 extend to the connection end portion of the display panel 1. Then, as shown in FIG. 1, one end of the short-circuit wiring 5 and the wiring 8a are connected, and the other end of the short-circuit wiring 5 and the wiring 8b are connected. Further, one end of the short-circuit wiring 6 and the wiring 9a are connected, and the other end of the short-circuit wiring 6 and the wiring 9b are connected. In this state, the wires 8 a and 8 b are connected to one by the short-circuit wire 5, and the wires 9 a and 9 b are connected to one by the short-circuit wire 6.
- test wiring units 8 and 9 transmit the signal normally. Yes. Therefore, it is considered that the connection between the display panel 1 and the FPC 2 is normal and that at least the portion of the FPC 2 where the test wiring portions 8 and 9 are formed is not damaged.
- the waveform of the signal appearing at either one of the terminals T2 and T4 and monitored by the monitor circuit 32, or the waveform of the signal appearing at both the terminals T2 and T4 and monitored by the monitor circuit 32 is the signal applying circuit 31. If the waveform of the input signal input to the terminals T1 and T3 is dull compared to the test wiring sections 8 and 9, the resistance value of the test wiring sections 8 and 9 may be high. is there.
- the signal input to the terminals T1 and T3 from the signal application circuit 31 includes, for example, a pulse signal.
- the signal is not necessarily a pulse signal, and a DC level signal (direct current signal) is not necessarily required. It is good.
- the resistance of the test wiring portions 8 and 9 is changed to the test. It becomes higher than when the wiring parts 8 and 9 are normal. Accordingly, the input signal input to the terminals T1 and T3 from the signal applying circuit 31 and the signal appearing at the terminals T2 and T4 and monitored by the monitor circuit 32 are different, and therefore flow through the portion where the resistance is increased. The voltage drop at the termination portion with respect to the current value becomes large, and it is possible to detect an abnormality in the test wiring portions 8 and 9.
- the connection state between the display panel 1 and the FPC 2 is monitored, and if the connection state becomes abnormal as a result of the monitoring, the connection between the display panel 1 and the FPC 2 is determined to be abnormal.
- the host circuit 34 may be fed back from the test circuit 33 included in the liquid crystal display device 30.
- the host system 34 is a signal source connected to the liquid crystal display device 30.
- the backlight is turned off or the power supply to the liquid crystal display device 30 is stopped. Preventive control is possible.
- a signal is input to the terminals T1 and T3 from a signal source mounted on a drive circuit mounting board connected to the display panel 1, and the terminals T2 and T2 are connected.
- the signal output from T4 may be monitored, and all of the terminals T1 to T4 may be wired so as to be controlled from the host system 34 which is the signal source of the liquid crystal display device 30.
- control of turning off the backlight or turning on the backlight can be performed in the liquid crystal display device 30 without using the host system 34, there is no problem in performing the control based on the connection information.
- the resistance value of the wiring path composed of the test wiring unit 8 and the short-circuit wiring 5 and the resistance value of the wiring path composed of the test wiring unit 9 and the short-circuit wiring 6 are compared with the respective resistance values at normal times measured in advance. May be. Also by this comparison, it is possible to predict the breakage state of the FPC 2 or the connection state between the display panel 1 and the FPC 2. If the resistance value of each wiring path is significantly higher than the normal value, that is, the resistance value at the normal time, it can be considered that each wiring path is almost disconnected. Terminals T1 to T4 can be used for measuring the resistance value.
- the display panel 1 is provided with the short-circuit wirings 5 and 6, while the FPC 2 is provided with the test wiring portions 8 and 9, and the short-circuit wirings 5 and 6 are connected to the test wiring portions 8 and 9, respectively. is doing. Further, the terminals T 1 and T 2 are connected to the end of the test wiring section 8, while the terminals T 3 and T 4 are connected to the end of the test wiring section 9.
- connection state can be easily predicted by the use state of the display device on which the display panel 1 is mounted. Further, the same prediction can be made by comparing the resistance value between the terminals T1 and T2 and the resistance value between the terminals T3 and T4 with the resistance value at the normal time.
- test wiring portions 8 and 9 are provided in the vicinity of both side edges of the FPC 2 .
- the pin layout in the FPC 2 is restricted, only one of the test wiring portions 8 and 9 may be provided.
- dummy wirings 31 and 32 may be further added in the FPC 2 as indicated by a one-dot chain line in FIG.
- the dummy wiring 31 is disposed between the test wiring portion 8 and one side edge of the FPC 2.
- the dummy wiring 32 is disposed between the test wiring portion 9 and the other side edge of the FPC 2.
- the dummy wirings 31 and 32 are usually provided as independent wirings that are not electrically connected to the display panel 1 side or the external side. Such dummy wirings 31 and 32 have a function of reinforcing the FPC 2. Therefore, the strength of both side edges of the FPC 2 can be further increased.
- the dummy wirings 31 and 32 may be electrically connected to the display panel 1 side or the external side as necessary.
- FIG. 3 shows a state where a PWB (Printed Wiring Board) 16 is connected to the display panel 11 via the COF 12 in the liquid crystal display device 40 according to the present embodiment.
- 4A and 4B show the display panel 11 and the PWB 16 that are not connected to each other.
- a plurality of COFs 12 are connected side by side on one side of the display panel 11. Further, a short-circuit wiring 21 is formed at a connection portion of each COF 12 in the display panel 11. The short-circuit wiring 21 will be described in detail later.
- a driver chip 13 In the COF 12, a driver chip 13, an input wiring (not shown), and an output wiring (not shown) are mounted on a film base made of polyimide or the like.
- the input wiring is provided for transmitting an input signal from the PWB 16 to the driver chip 13, and the output wiring is provided for transmitting an input signal from the driver chip 13 to the display panel 11.
- the driver chip 13 is configured in the same manner as the driver chip 3 described above, and supplies a drive signal to each pixel in order to drive a plurality of pixels included in the display panel 11.
- SOF System On Chip
- TCP Transmission Carrier Package
- SOF has a structure in which a chip is mounted on a film substrate made of polyimide or the like, and in recent years, it has been widely used as a driving integrated circuit component such as a liquid crystal driver. With such a structure, the SOF can be provided with wiring at a portion where the chip is mounted, unlike the TCP where the chip is mounted in the opening of the film base. Also, unlike TCP, SOF does not have a slit that defines the bending position, and can be bent at a desired location.
- test wiring unit 14 and the short-circuit wiring 15 are provided in the COF 12.
- the test wiring unit 14 includes two wirings 14a and 14b arranged side by side.
- the wirings 14 a and 14 b are formed on one side of the driver chip 13 on the film base material of the COF 12 so as to connect the display panel 11 and the PWB 16.
- the short-circuit wiring 15 is formed in a rectangular U shape on the other side of the driver chip 13 in the film base material of the COF 12. Both ends of the short-circuit wiring 15 extend to the connection end portion on the PWB 16 side in the COF 12.
- the display panel 11 is connected to the COF 12 by the ACF at the connection portion 22 in a state where the connection end portion is superimposed on the connection end portion of the COF 12.
- the aforementioned output wiring in the COF 12 and the input wiring (not shown) in the display panel 11 are electrically connected.
- the above-described short-circuit wiring 21 is formed in a rectangular U-shape. Both ends of the short-circuit wiring 21 extend to the connection end of the display panel 11. As shown in FIG. 3, one end of the short-circuit wiring 21 and the wiring 14a are connected, and the other end of the short-circuit wiring 21 and the wiring 14b are connected. In this state, the wirings 14 a and 14 b are connected to one by the short-circuit wiring 21.
- the PWB 16 generates a timing signal necessary for driving the display panel 11 by a controller (not shown) mounted on the PWB 16.
- the PWB 16 has a wiring pattern (not shown) provided to face each COF 12. This wiring pattern includes a plurality of wirings (not shown) for transmitting a timing signal supplied to the driver chip 13 of each COF 12.
- the timing signal is prepared according to a driving method such as a clock for controlling the timing of outputting the display data or the timing of the selection signal, and is supplied from a controller (not shown) mounted on the PWB 16.
- the controller generates the timing signal based on an externally supplied clock or various pulse signals.
- controller may be provided outside the PWB 16.
- the PWB 16 has test wirings 18 and 19, terminals TA1, TA2, TB1, TB2 and intermediate terminals TX1, TX2, TY1, TY2.
- the test wiring 18 includes a plurality of wirings 18a and 18b, an input side wiring 18c, an output side wiring 18d, and a common wiring 18e.
- the test wiring 19 includes a plurality of wirings 19a and 19b, an input side wiring 19c, an output side wiring 19d, and a common wiring 19e.
- terminals TA1 and TB1 are connected to the signal application circuit 41, and the terminals TA2 and TB2 are connected to the monitor circuit 42.
- the test circuit 43 includes a signal application circuit 41 and a monitor circuit 42 and is connected to a host system 44 described later.
- a pair of wirings 18a, 18b is provided for each COF 12.
- One end of the wiring 18a is connected to the wiring 14a, and one end of the wiring 18b is connected to the wiring 14b.
- the input side wiring 18c connects the other end of the wiring 18b connected to the wiring 14b in the COF 12 arranged at one end (the left end in the figure) to the terminal TA1.
- the output side wiring 18d connects the other end of the wiring 18a connected to the wiring 14a in the COF 12 arranged at the other end (the right end in the drawing) to the terminal TA2.
- the common wiring 18e connects the adjacent wirings 18a and 18b between adjacent pairs.
- a pair of wirings 19a and 19b is also provided for each COF 12.
- One end of the wiring 19 a is connected to one end of the short-circuit wiring 15, and one end of the wiring 19 b is connected to the other end of the short-circuit wiring 15.
- the input-side wiring 19c connects the other end of the wiring 19b connected to one end of the short-circuit wiring 15 in the COF 12 arranged at one end (left end in the drawing) to the terminal TB1.
- the output-side wiring 19d connects the other end of the wiring 19a connected to the other end of the short-circuit wiring 15 in the COF 12 arranged at the other end (right end in the drawing) to the terminal TB2.
- the common wiring 19e connects the adjacent wirings 19a and 19b between adjacent pairs.
- terminals TX1 and TX2 are connected to the ends of the wirings 18a and 18b on the COF 12 side, respectively.
- terminals TY1 and TY2 are connected to the ends of the wirings 19a and 19b on the COF 12 side, respectively.
- the PWB 16 is connected to the COF 12 by the ACF at the connection portion 20 in a state where the connection end portion is superimposed on the connection end portion of the COF 12.
- the above-described input wiring in the COF 12 and the wiring pattern 17 are electrically connected.
- test wiring unit 14 in the COF 12 and the test wiring unit 18 in the PWB 16 are electrically connected. Specifically, the wirings 18a and 18b of the PWB 16 are connected to the wirings 14a and 14b of the corresponding COFs 12, respectively. Thereby, the test wiring part 18 forms the wiring connected with the test wiring part 14 and the short circuit wiring 21 between the terminals TA1 and TA2.
- each wiring 19a, 19b of the PWB 16 is connected to both ends of the corresponding short-circuit wiring 15 of each COF 12.
- the test wiring part 19 forms the wiring connected with one between the terminals TB1 and TB2 with the short circuit wiring 15.
- a signal having an arbitrary waveform for testing is input from the signal applying circuit 41 to the terminals TA1 and TB1, and the signal appearing at the terminals TA2 and TB2 is monitored by the monitor circuit 42, whereby the COF 12 and / or The damaged state of the PWB 16, the connection state between the display panel 11 and the COF 12, and the connection state between the COF 12 and the PWB 16 can be predicted.
- test wiring sections 14, 18, and 19 normally transmit signals. is doing. Therefore, it is considered that the connection between the display panel 11 and the COF 12 and the connection between the COF 12 and the PWB 16 are normal, and that at least the test wiring portions 14, 18, and 19 of the COF 12 and the PWB 16 are not damaged. .
- the test wiring portions 14 and 18 themselves are disconnected, the connection state between the test wiring portion 18 and the test wiring 14, or / and the connection between the test wiring portion 14 and the short wiring 21. It is likely that the condition has deteriorated. Therefore, in this case, the edge portion of the COF 12 (end portion on the arrangement side of the test wiring portion 14) is damaged, or the connection failure between the COF 12 and the PWB 16 or / and the connection failure between the display panel 11 and the COF 12 is suspected.
- test wiring portions 14 and 18 There is a possibility that the resistance values of the test wiring portions 14 and 18 are high due to damage or the like.
- the test wiring section 19 There is a possibility that the resistance value of the test wiring portion 19 is high due to breakage or the like.
- the signal input from the signal application circuit 41 to the terminals TA1 and TB1 is, for example, a pulse signal, but is not necessarily a pulse signal, and may be a DC level signal for simple implementation.
- the test wiring portions 14 and 18 are abnormal, that is, when a portion of the test wiring portions 14 and 18 is about to break, or when the test wiring portions 14 and 18 are broken, the resistances of the test wiring portions 14 and 18 are tested. It becomes higher than when the wiring parts 14 and 18 are normal. Accordingly, the input signal input to the terminals TA1 and TB1 from the signal applying circuit 41 and the signal appearing at the terminals TA2 and TB2 and monitored by the monitor circuit 42 are different, and therefore flow through the portion where the resistance is increased. The voltage drop at the termination portion with respect to the current value becomes large, and it is possible to detect an abnormality in the test wiring portions 14 and 18.
- connection state between the display panel 11 and the COF 12 is monitored, and if the connection state becomes abnormal as a result of the monitoring, it is confirmed that the display panel 11 and the COF 12 have a connection abnormality.
- the feedback may be fed back from the test circuit 43 included in the liquid crystal display device 40 to the host system 44.
- the host system 44 is a signal source connected to the liquid crystal display device 40.
- preventive control such as turning off the backlight or stopping the power supply to the liquid crystal display device 40 is performed. It becomes possible.
- signals are input to the terminals TA1 and TB1 from the signal source mounted on the COF 12 that is the drive circuit mounting board, and output from the terminals TA2 and TB2.
- the terminal TA1, the terminal TA2, the terminal TB1, and the terminal TB2 may all be wired so as to be controlled from the host system 44 that is a signal source of the liquid crystal display device 40.
- control such as backlight turn-off control or backlight turn-on control can be performed in the liquid crystal display device 40 without using the host system 44, the control is performed based on the monitoring result of the connection state. There is no problem.
- the resistance value of the wiring path composed of the test wiring sections 14 and 18 and the short-circuit wiring 21 and the resistance value of the wiring path composed of the test wiring section 19 and the short-circuit wiring 15 are respectively measured as normal resistance values. You may compare. Also by this comparison, it is possible to predict the damaged state of the COF 12, the connection state between the display panel 11 and the COF 12, and the connection state between the COF 12 and the PWB 16. If the resistance value of each wiring path is significantly higher than the normal value, that is, the resistance value at the normal time, it is considered that each wiring path is almost disconnected. Terminals TA1, TA2, TB1, and TB2 can be used for measuring the resistance value.
- each COF 12 may be damaged in each part as described above or may be defective in connection in each connection part. Sex can be confirmed.
- the short wiring 21 is provided on the display panel 11, the test wiring portion 14 and the short wiring 15 are provided on the COF 12, the test wiring portion 18 and the short wiring 21 are connected, and the test wiring portion is provided. 18 and the short-circuit wiring 15 are connected. Further, the terminals TA 1 and TA 2 are connected to the end of the test wiring section 18, while the terminals TB 1 and TB 2 are connected to the end of the test wiring section 19.
- the damaged state of the COF 12, the connection state between the display panel 11 and the COF 12, and the connection state between the COF 12 and the PWB 16 can be easily predicted in the usage state of the display device on which the display panel 11 is mounted. Further, the same prediction can be made by comparing the resistance value between the terminals TA1 and TA2 and the resistance value between the terminals TB1 and TB2 with the resistance value at the normal time.
- FIG. 5 is a plan view showing the modification.
- the liquid crystal display device 50 includes a display panel 23, a COF 24, and a PWB 25.
- the COF 24 has the same configuration as the COF 12 except that it further includes a test wiring unit 26.
- the test wiring portion 26 is arranged closer to the side end portion than the above-described short-circuit wiring 15 in the COF 12, and includes two wirings 26a and 26b arranged side by side.
- the display panel 23 has the same configuration as the display panel 11 except that the display panel 23 further includes a short-circuit wiring 27.
- the short-circuit line 27 is provided in the same manner as the short-circuit line 21 so as to short-circuit each of the lines 26a and 26b.
- the PWB 25 has the same configuration as the COF 12 except that it further includes a test wiring unit 28.
- the test wiring unit 28 includes wirings 28a and 28b and a wiring group 28c.
- the test wiring unit 28 is connected to the test wiring unit 26 so that the test wiring unit 18 has the same relationship as the connection to the test wiring unit 14. ing.
- the test wiring 26 has terminals TZ1 and TZ2 having functions equivalent to those of the terminals TX1 and TX2 described above for each COF 12.
- terminal TC1 is connected to the signal applying circuit 51 similarly to the terminals TA1 and TB1
- terminal TC2 is connected to the monitor circuit 52 similarly to the terminals TA2 and TB2.
- the test circuit 53 includes a signal application circuit 51 and a monitor circuit 52 and is connected to the host system 54.
- test wiring portion 14 and the short-circuit wiring 15 are provided in the vicinity of both side edges of the COFs 12 and 24 in the present embodiment.
- the pin layout in the COFs 12 and 24 only one of the test wiring unit 14 and the short-circuit wiring 15 may be provided.
- dummy wirings 41 and 42 may be further added in the COFs 12 and 24 as indicated by a one-dot chain line in FIGS.
- the dummy wiring 41 is disposed between the test wiring section 14 and one side edge of the COFs 12 and 24.
- the dummy wiring 42 is disposed between the short-circuit wiring 15 and the other side edge of the COFs 12 and 24.
- the dummy wirings 41 and 42 are usually provided as independent wirings that are not electrically connected to the display panels 11 and 23 or the external side. Such dummy wirings 41 and 42 have a function of reinforcing the COFs 12 and 24. Therefore, the strength of both side edges of the COFs 12 and 24 can be further increased.
- the dummy wirings 41 and 42 may be electrically connected to the display panels 11 and 23 side or the PWBs 16 and 25 side as necessary.
- FIG. 6 shows a configuration of the liquid crystal display device 101 according to the present embodiment.
- the liquid crystal display device 101 includes a liquid crystal display panel 102, a plurality of source drivers 103, a plurality of gate drivers 104, and a controller 105.
- the liquid crystal display panel 102 is connected to a test circuit 113 having a signal application circuit 111 and a monitor circuit 112, and the test circuit 113 is a host connected to the liquid crystal display device 101. Connected to system 114.
- the liquid crystal display panel 102 includes a plurality (m ⁇ i) of gate bus lines G11 to Gmi, a plurality (n ⁇ j) of source bus lines S11 to Snj, and a plurality of pixels PIX.
- gate bus lines G11 to Gmi will be referred to as the gate bus line G when appropriate.
- source bus lines S11 to Snj are described as a representative, they are appropriately referred to as source bus lines S.
- the pixel PIX is disposed in the vicinity where the gate bus line G and the source line S intersect.
- the pixel PIX includes a thin film transistor (hereinafter simply referred to as a transistor) on the glass substrate of the liquid crystal display panel 102 and a display element DE.
- the gate of the transistor is connected to the gate bus line G, the source is connected to the source bus line S, and the drain is connected to a pixel electrode (not shown).
- a common voltage is applied to a common electrode (not shown) arranged to face the pixel electrode.
- a display element is composed of the pixel electrode, the common electrode, and the liquid crystal between the two electrodes.
- the gate bus lines G11 to Gmi, the source bus lines S11 to Snj, the transistors and the pixel electrodes are formed on a glass substrate.
- the common electrode is formed on a glass substrate provided to face the glass substrate. A liquid crystal is filled between the glass substrates (between the pixel electrode and the common electrode).
- the n source drivers 103 are provided, transfer the start pulse SSP to the shift register at the timing of the source clock signal SCK, and correspond to the display data Dx at the timing of the timing pulse output from each output stage of the shift register.
- the position of the source bus line S is held.
- the source driver 103 takes in the held display data Dx into the latch at the timing of the latch signal LS and outputs it to the j source bus lines S.
- the gate driver 104 is provided with m pieces, and the start pulse GSP is transferred to the shift register at the timing of the gate clock signal GCK, and the gate pulse is generated by the timing pulse output from each output stage of the shift register to generate i gate pulses. Output to the gate bus line G.
- the controller 105 generates control signals such as a start pulse SSP, a source clock signal SCK, and a latch signal LS to be supplied to the source driver 103, and outputs the input display data Dx to the source driver 103.
- the controller 105 generates control signals such as a start pulse GSP and a gate clock signal GCK to be given to the gate driver 104.
- the liquid crystal display panel 102 is constituted by the display panel 1, 11 or 23 described above.
- the source driver 103 and the gate driver 104 are configured by the driver chip 3 in the display panel 1, the COF 12 in the display panel 11, or the COF 24 in the display panel 23. Therefore, when the liquid crystal display panel 102 is configured by the display panel 1, the FPC 2 is connected to the liquid crystal display panel 102. Further, when the liquid crystal display panel 102 is configured by the display panel 11, the PWB 16 is connected to the liquid crystal display panel 102. When the liquid crystal display panel 102 is configured by the display panel 23, the PWB 25 is connected to the liquid crystal display panel 102.
- the FPC 2 or the PWB 16 or 25 may be damaged particularly at both ends, the liquid crystal display panel 102, the FPC 2 or the PWB 16 or 25,
- the connection state of the liquid crystal display device 101 can be easily predicted.
- the display panel 1 of the first embodiment or the display panels 11 and 23 of the second embodiment are mounted on the liquid crystal display device 101.
- the display panels 1, 11, and 23 may be mounted on other display devices such as an organic LE display and a plasma display as long as they can be driven using a driver chip.
- the liquid crystal display device testing method and the liquid crystal display device according to the present invention can predict the state of breakage of the flexible substrate on which the signal wiring is mounted by checking the energization state of the signal wiring to the drive circuit even in the use state. Since it is possible, it can be suitably used for in-vehicle display devices.
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Abstract
Description
これにより、中間基板が複数存在しても、各中間基板について、配線実装基板と中間基板との接続状態および表示パネルと中間基板との接続状態を予測することができる。
図1は、本実施の形態に係る液晶表示装置30において表示パネル1にFPC2が接続されている状態を示している。また、図2の(a)および図2の(b)は、それぞれ接続されていない状態の、表示パネル1とFPC2とを示している。
図3は、本実施の形態に係る液晶表示装置40において表示パネル11にCOF12を介してPWB(Printed Wiring Board)16が接続されている状態を示している。また、図4の(a)および図4の(b)は、それぞれ接続されていない状態の表示パネル11とPWB16とを示している。
図6は、本実施の形態に係る液晶表示装置101の構成を示している。
2 FPC(配線実装基板)
3,13 ドライバチップ
4,7,17 配線パターン
5,6,21 短絡配線(第1短絡配線)
8,9 テスト配線部
8a,9a 配線(第1配線)
8b,9b 配線(第2配線)
12,24 COF
16,25 PWB(配線実装基板)
14 テスト配線部
14a 配線(第3配線)
14b 配線(第4配線)
18,28 テスト配線部
18a,28a 配線(第1配線)
18b,28b 配線(第2配線)
19 テスト配線部
19a 配線
19b 配線
30、40、50、101 液晶表示装置
31、41、51、111 信号印加回路(信号印加手段)
32、42、52、112 モニタ回路(比較手段)
33、43、53、113 試験回路
34、44、54、114 ホストシステム(制御手段)
102 液晶表示パネル(表示パネル)
T1,T3 端子(第1端子)
T2,T4 端子(第2端子)
TA1,TC1 端子(第1端子)
TA2,TC2 端子(第2端子)
TX1,TZ1 端子(第1端子)
TX2,TZ2 端子(第2端子)
TB1 端子(第3端子)
TB2 端子(第4端子)
TY1 端子(第3端子)
TY2 端子(第4端子)
Claims (12)
- 表示パネルを駆動するための信号を供給する信号供給配線を実装する配線実装基板が接続されている表示パネルを備える液晶表示装置の試験方法において、
前記表示パネル側に伸びる第1配線および第2配線、ならびに当該第1および第2配線にそれぞれ接続される第1端子および第2端子を有する前記配線実装基板と、前記表示パネルと前記配線実装基板との接続部分で前記第1および第2配線にそれぞれ接続されて前記第1および第2配線を短絡する第1短絡配線を有する前記表示パネルとを接続している状態で、
前記第1端子に信号を印加し、
前記第2端子から出力される信号と前記第1端子に印加される信号とを比較することを特徴とする液晶表示装置の試験方法。 - 前記配線実装基板と前記表示パネルとの間の信号を伝達する配線を実装する中間基板を介在させることにより、前記配線実装基板と前記表示パネルとを接続し、前記中間基板が有する第3および第4配線は、前記第1および第2配線と前記第1短絡配線とをそれぞれ接続している状態で、
前記第1端子に信号を印加し、
前記第2端子から出力される信号と前記第1端子に印加される信号とを比較することを特徴とする請求項1に記載の液晶表示装置の試験方法。 - 前記中間基板が有する第2短絡配線は、当該中間基板と前記配線実装基板との接続部分で第5および第6配線にそれぞれ接続されて当該第5および第6配線を短絡し、前記配線実装基板が、前記第5および第6配線にそれぞれ接続される第3端子および第4端子を有している状態で、
前記第3端子に信号を印加し、
前記第4端子から出力される信号と前記第3端子に印加される信号とを比較することを特徴とする請求項2に記載の液晶表示装置の試験方法。 - 前記信号は、パルス信号であることを特徴とする請求項1に記載の液晶表示装置の試験方法。
- 前記信号は、直流の信号であることを特徴とする請求項1に記載の液晶表示装置の試験方法。
- 表示パネルを駆動するための信号を供給する信号供給配線を実装する配線実装基板が接続されている表示パネルを備える液晶表示装置において、
前記配線実装基板が、前記表示パネル側に伸びる第1配線および第2配線と、当該第1および第2配線にそれぞれ接続される第1端子および第2端子とを有し、
前記表示パネルが、当該表示パネルと前記配線実装基板との接続部分で前記第1および第2配線にそれぞれ接続されて当該第1および第2配線を短絡する第1短絡配線を有し、
前記液晶表示装置が、
前記第1端子に信号を印加する信号印加手段と、
前記第2端子から出力される信号と前記第1端子に印加される信号とを比較する比較手段とを備えることを特徴とする液晶表示装置。 - 前記第1および第2配線が前記配線実装基板の少なくとも一方の側端部に設けられていることを特徴とする請求項6に記載の液晶表示装置。
- 前記配線実装基板と前記表示パネルとの間の信号を伝達する配線を実装する中間基板を介在させることにより、前記配線実装基板と接続されており、
前記中間基板が、前記第1および第2配線と前記第1短絡配線とをそれぞれ接続する第3および第4配線を有していることを特徴とする請求項6に記載の液晶表示装置。 - 前記配線実装基板が、前記中間基板側に伸びる第5配線および第6配線と、当該第5および第6配線にそれぞれ接続される第3端子および第4端子とを有し、
前記中間基板が、当該中間基板と前記配線実装基板との接続部分で前記第5および第6配線にそれぞれ接続されて当該第5および第6配線を短絡する第2短絡配線を有し、
前記信号印加手段は、前記第3端子に信号を印加し、
前記比較手段は、前記第4端子から出力される信号と前記第3端子に印加される信号とを比較することを特徴とする請求項8に記載の液晶表示装置。 - 複数の前記中間基板を介して前記配線実装基板と接続されていることを特徴とする請求項8に記載の液晶表示装置。
- 各中間基板が、その両側端部に前記第5および第6配線の対を有していることを特徴とする請求項9に記載の液晶表示装置。
- 前記配線実装基板がプリント配線基板であり、
前記中間基板が、フィルム上に表示パネルを駆動する集積回路が実装されている実装基板であることを特徴とする請求項8に記載の液晶表示装置。
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US13/057,189 US20110175800A1 (en) | 2008-08-06 | 2009-05-27 | Method for testing liquid crystal display device and liquid crystal display device |
EP09804799A EP2320270A4 (en) | 2008-08-06 | 2009-05-27 | METHOD FOR TESTING LIQUID CRYSTAL DISPLAY DEVICE AND LIQUID CRYSTAL DISPLAY DEVICE |
RU2011104246/28A RU2473104C2 (ru) | 2008-08-06 | 2009-05-27 | Жидкокристаллический дисплей и способ его проверки |
BRPI0917427A BRPI0917427A2 (pt) | 2008-08-06 | 2009-05-27 | método para testar dispositivo de exibição de cristal líquido e dispositivo de exibição de cristal líquido |
CN2009801297807A CN102112914A (zh) | 2008-08-06 | 2009-05-27 | 液晶显示装置的试验方法和液晶显示装置 |
JP2010523793A JPWO2010016312A1 (ja) | 2008-08-06 | 2009-05-27 | 液晶表示装置の試験方法および液晶表示装置 |
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CN112331118B (zh) * | 2020-11-30 | 2023-09-26 | 武汉天马微电子有限公司 | 一种显示面板和显示装置 |
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Also Published As
Publication number | Publication date |
---|---|
BRPI0917427A2 (pt) | 2015-12-01 |
CN102112914A (zh) | 2011-06-29 |
US20110175800A1 (en) | 2011-07-21 |
RU2011104246A (ru) | 2012-09-20 |
RU2473104C2 (ru) | 2013-01-20 |
EP2320270A4 (en) | 2012-03-28 |
JPWO2010016312A1 (ja) | 2012-01-19 |
EP2320270A1 (en) | 2011-05-11 |
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