WO2010013636A1 - Film de câblage, transistor en couches minces, cible, procédé de formation de film de câblage - Google Patents

Film de câblage, transistor en couches minces, cible, procédé de formation de film de câblage Download PDF

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Publication number
WO2010013636A1
WO2010013636A1 PCT/JP2009/063185 JP2009063185W WO2010013636A1 WO 2010013636 A1 WO2010013636 A1 WO 2010013636A1 JP 2009063185 W JP2009063185 W JP 2009063185W WO 2010013636 A1 WO2010013636 A1 WO 2010013636A1
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Prior art keywords
film
atomic
layer
barrier film
low resistance
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PCT/JP2009/063185
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English (en)
Japanese (ja)
Inventor
悟 高澤
石橋　暁
忠 増田
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株式会社アルバック
アルバックマテリアル株式会社
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Publication of WO2010013636A1 publication Critical patent/WO2010013636A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C19/00—Alloys based on nickel or cobalt
    • C22C19/03—Alloys based on nickel or cobalt based on nickel
    • C22C19/05—Alloys based on nickel or cobalt based on nickel with chromium
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/14—Metallic material, boron or silicon
    • C23C14/18—Metallic material, boron or silicon on other inorganic substrates
    • C23C14/185—Metallic material, boron or silicon on other inorganic substrates by cathodic sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • the present invention relates to a metal wiring film for electronic parts and a transistor using the metal wiring film.
  • low resistance materials such as Al and Cu, Mo, Cr, and the like are used for metal wiring films for electronic components.
  • TFT Thin Film Transistor
  • the demand for lower resistance of wiring electrodes is increasing as the panel size increases, and the need to use Al or Cu as low resistance wiring is increasing.
  • Cu is a material having a lower resistance than Al.
  • Al has a problem of deterioration of contact resistance with the ITO transparent electrode, but Cu has a good contact resistance because it is difficult to oxidize.
  • Cu has problems such as poor adhesion to a base material such as glass or Si as compared with other wiring materials, and Cu diffuses into the Si layer when used as a source or drain electrode.
  • a barrier layer for improving adhesion and preventing diffusion is required at the interface between the Cu wiring and other layers.
  • the present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a barrier film having high diffusion preventing ability and high adhesion.
  • the present invention provides a wiring film that contacts at least one film formation target layer selected from the group consisting of a glass substrate, a silicon layer, and an oxide semiconductor layer,
  • the film includes a barrier film disposed in close contact with the surface of the film formation target layer, and a metal low resistance layer disposed in close contact with the surface of the barrier film.
  • the metal low resistance layer includes 50 atomic% of Cu.
  • the barrier film contains Ni of 50 atomic% or more and an additive element of 7 atomic% or more and 50 atomic% or less, and the additive elements include V, Al, Mo, Ti,
  • the wiring film is selected from an additive element group consisting of Zr, Cr, Si, W, Ta, In, Sn, Zn, Mn, and Cu.
  • the present invention includes a gate electrode, a semiconductor layer disposed on the gate electrode, a gate insulating film disposed between the gate electrode and the semiconductor layer, and a connection electrode electrically connected to the semiconductor layer
  • the connection electrode includes a barrier film disposed in close contact with the semiconductor layer, and a metal low resistance layer disposed in close contact with a surface of the barrier film opposite to the semiconductor layer.
  • the metal low-resistance layer contains 50 atomic% or more of Cu
  • the barrier film has 50 atomic% or more of Ni and 7 atomic% or more and 50 atomic% or less of an additive element, , V, Al, Mo, Ti, Zr, Cr, Si, W, Ta, In, Sn, Zn, Mn, and Cu. It is a thin film transistor.
  • the present invention is a thin film transistor having a gate electrode disposed on a glass substrate, a semiconductor layer disposed on the gate electrode, and a gate insulating film disposed between the semiconductor layer and the gate electrode.
  • the gate electrode includes a barrier film disposed in close contact with the surface of the glass substrate, and a metal low resistance layer disposed in close contact with the surface of the barrier film opposite to the glass substrate, and the metal low resistance layer Contains 50 atomic% or more of Cu, the barrier film has 50 atomic% or more of Ni and 7 atomic% or more and 50 atomic% or less of additive elements, and the additive elements include V, Al,
  • the thin film transistor is selected from an additive element group consisting of Mo, Ti, Zr, Cr, Si, W, Ta, In, Sn, Zn, Mn, and Cu.
  • the present invention is a target that contains 50 atomic% or more of Ni, V, Al, Mo, Ti, Zr, Cr, Si, W, Ta, In, Sn, It is a target to which any one or more kinds of additive elements selected from the additive element group consisting of Zn, Mn, and Cu are added.
  • the present invention relates to a wiring film forming method for forming a wiring film on a surface of at least one film formation target layer selected from the group consisting of a glass substrate, a silicon layer, and an oxide semiconductor layer, comprising 50 atoms.
  • % Of Ni and 7 atomic% or more and 50 atomic% or less of an additive element, and the additive elements are V, Al, Mo, Ti, Zr, Cr, Si, W, and the like.
  • the present invention is a method of forming a wiring film, wherein after the barrier film and the metal low resistance layer are formed, the barrier film and the metal low resistance layer are patterned with the same etchant. .
  • the wiring film of the present invention is a film that adheres to a semiconductor layer (silicon layer, oxide semiconductor layer), a transparent conductive film, or a glass substrate, specifically, a TFT source electrode, drain electrode, gate electrode, storage capacitor electrode, etc. It is particularly suitable for these electrodes. It can also be used for barrier films and electrodes (wiring films) of other electronic components such as semiconductor elements and wiring boards.
  • the silicon layer includes a silicon layer doped with impurities (ohmic contact layer) in addition to a silicon-based material such as polysilicon or amorphous silicon.
  • the barrier film contains 50 atomic% or more of Ni, the adhesion to the glass substrate, the silicon layer, and the oxide semiconductor layer is higher than that of the metal low resistance layer. Since the adhesion between the barrier film and the metal low resistance layer is also high, the wiring film is difficult to peel off from the film formation target. The electrical resistance of the wiring film is lowered by laminating the metal low resistance layer on the barrier film. Since the barrier film and the metal low resistance layer can be etched with the same etchant, it is not necessary to separate the etching process, and the manufacturing time and manufacturing cost of the wiring film and the thin film transistor can be shortened.
  • Sectional drawing explaining an example of the film-forming apparatus used for this invention Sectional drawing explaining the process of forming a laminated film Sectional drawing explaining the process of forming a laminated film Sectional drawing explaining the process of forming a laminated film Sectional drawing explaining the manufacturing process of the thin-film transistor of a 1st example Sectional drawing explaining the manufacturing process of the thin-film transistor of a 1st example Sectional drawing explaining the manufacturing process of the thin-film transistor of a 1st example Sectional drawing explaining the manufacturing process of the thin-film transistor of a 1st example Sectional drawing explaining an example of a liquid crystal display device Sectional drawing explaining the thin-film transistor of a 2nd example Sectional drawing explaining the thin-film transistor of a 3rd example
  • Reference numeral 100 in FIG. 1 shows an example of a film forming apparatus used in the present invention.
  • the film forming apparatus 100 includes a carry-in / out chamber 102, a first film forming chamber 103a, and a second film forming chamber 103b.
  • the carry-in / out chamber 102 and the first film forming chamber 103a and the first film forming chamber 103a and the second film forming chamber 103b are connected to each other through gate valves 109a and 109b, respectively.
  • the evacuation systems 113, 114a, 114b are connected to the carry-in / out chamber 102 and the first and second film forming chambers 103a, 103b, respectively, and the gate valves 109a, 109b are closed, and the first and second components are formed.
  • the inside of the film chambers 103a and 103b is evacuated.
  • the door between the loading / unloading chamber 102 and the atmosphere is opened, the film formation target 21 is loaded into the loading / unloading chamber 102, the door is closed, the inside of the loading / unloading chamber 102 is evacuated, the gate valve 109 a is opened, The film formation target 21 is moved into the first film formation chamber 103 a and is held by the substrate holder 108.
  • a nickel target 111 of the present invention and a copper target (here, pure copper target made of copper) 112 are disposed on the bottom wall side inside the first and second film forming chambers 103a and 103b, respectively.
  • the object 21 is held by the substrate holder 108 so as to face each of the targets 111 and 112.
  • Gas introduction systems 115a and 115b are connected to the first and second film formation chambers 103a and 103b, respectively, and a sputtering gas is introduced from the gas introduction system 115a while evacuating the inside of the first film formation chamber 103a. Then, a voltage is applied to the nickel target 111 from a power source (not shown) to perform sputtering.
  • a magnet 105 (permanent magnet or electromagnet) is disposed on the surface (back surface) opposite to the substrate holder 108 of the nickel target 111. Magnetic field lines passing through the surface of the nickel target 111 are formed by the magnet 105, the plasma density on the surface of the nickel target 111 is increased, and the sputtering speed is increased compared to the case without the magnet 105 (magnetron sputtering).
  • the nickel target 111 of the present invention has a Ni content of 50% or more, and V, Al, Mo, Ti, Zr, Cr, Si, W, Ta, In, and Sn. And an alloy target to which any one or more kinds of nonmagnetic materials selected from the group consisting of Zn, Mn, and Cu are added as additive elements.
  • the target is composed only of a magnetic material such as Ni, it is difficult to generate a magnetic field suitable for film formation by magnetron sputtering, but the nickel target 111 of the present invention is non-added by adding an additive element. Since it is magnetized, the sputtering speed is faster than when magnetron sputtering is performed and the magnet 105 is not disposed.
  • nickel particles and additive element particles are released as sputtered particles. That is, nickel atoms and additive elements are released from the nickel target 111.
  • any one or more of a glass layer (glass substrate and the like), a silicon layer, and an oxide semiconductor layer are exposed on the surface (film formation surface) 19 of the film formation target 21.
  • the film formation target 21 is held by the substrate holder 108 with the film formation surface 19 facing the nickel target 111, the sputtered particles emitted from the nickel target 111 are incident on the film formation surface 19, and the barrier film 25 is formed on the film formation surface 19. (FIG. 2A).
  • the atomic composition of the barrier film 25 is substantially equal to the atomic composition of the nickel target 111.
  • the barrier film 25 has a Ni content of 50 atomic% or more, and V, Al, Mo, Ti, Zr, Cr, Si, W, Ta, In, Sn, and V.
  • One or more types of nonmagnetic materials selected from the group consisting of Zn, Mn, and Cu are added as additive elements.
  • Sputtering may be performed by supplying a reaction gas (for example, an oxidizing gas such as O 2 ) from the reaction gas supply system to the first film formation chamber 103a, and in this case, the barrier film 25 includes nickel and an additive element. In addition, it contains constituent atoms of the reaction gas.
  • a reaction gas for example, an oxidizing gas such as O 2
  • the barrier film 25 includes nickel and an additive element. In addition, it contains constituent atoms of the reaction gas.
  • the substrate holder 108 holding the film formation target 21 is moved to the second film formation chamber 103b. While evacuating the second film formation chamber 103b, a sputtering gas is introduced from the gas introduction system 115b, and a copper target (here, a pure copper target) 112 containing 50 atomic% or more of Cu is sputtered.
  • a sputtering gas is introduced from the gas introduction system 115b, and a copper target (here, a pure copper target) 112 containing 50 atomic% or more of Cu is sputtered.
  • the barrier film 25 and the metal A laminated film 22a of the low resistance layer 26 is formed (FIG. 2B).
  • the metal low resistance layer 26 is formed by sputtering a copper target to which another additive metal such as nickel is added at 50 atomic% or less. May be. In any case, the metal low resistance layer 26 has a higher copper content than the barrier film 25, and the electric resistance of the metal low resistance layer 26 is lower than the electric resistance of the barrier film 25.
  • the pure copper target 112 may be sputtered while supplying a reactive gas such as an oxidizing gas to the second film forming chamber 103b.
  • the laminated film 22a may be composed of only the barrier film 25. However, when the barrier film 25 is a thin film and the thick metal low resistance layer 26 is laminated rather than the barrier film 25, the overall electric resistance is lowered.
  • the laminated film 22 b may be configured by the resistance layer 26 and the barrier films 25 and 28 formed on the surface of the metal low resistance layer 26.
  • the film formation target 21 on which the laminated films 22 a and 22 b are formed is unloaded from the film formation apparatus 100.
  • a resist patterned in a predetermined shape is disposed on the laminated films 22a and 22b, and the laminated films 22a and 22b are etched with an etchant.
  • Nickel can be etched with the same etchant as copper (for example, an etchant containing nitric acid), and the difference between the nickel etching rate and the copper etching rate is small. Therefore, the metal low resistance layer 26 and the barrier films 25 and 28 can be continuously etched with the same etchant. Therefore, the laminated films 22a and 22b are patterned into a predetermined shape in one etching process, and an electrode is formed.
  • the barrier film 25 is located on the contact surface of the electrode that contacts the film formation target 21.
  • the barrier film 25 contains 50 atomic% or more of nickel, and adheres to a glass layer (glass substrate), a silicon layer (silicon semiconductor layer, ohmic contact layer), and an oxide semiconductor layer (ZnO, In—Ga—Zn—O). Is expensive.
  • the electrode is the surface of the film formation target 21. Hard to peel off.
  • the barrier film 25 containing 50 atomic% or more of nickel has a function of preventing copper atoms from diffusing from the metal low-resistance layer 26 to the semiconductor layer, so that a silicon semiconductor layer, When a semiconductor layer such as an oxide semiconductor layer is exposed, copper is prevented from diffusing into the semiconductor layer.
  • Nickel and an additive metal V were blended to form a nickel target 111, and the nickel target 111 was examined for magnetism and non-magnetism. The results are shown in Table 1 below together with the amount of V.
  • the nickel target 111 is magnetron sputtered in the first film formation chamber 103a of FIG. 1 to form a barrier film 25 having a film thickness of 50 nm on the surface of the film formation target 21, and then a pure copper target 112 is sputtered to form a barrier.
  • a laminated film 22a in which a 300 nm-thick metal low resistance layer 26 was laminated on the surface of the film 25 was formed, and a test piece having a structure shown in FIG. 2B was obtained.
  • the barrier film 25 and the metal low resistance layer 26 were formed while introducing only the sputtering gas (Ar gas) into the first and second film formation chambers 103a and 103b and heating the film formation target 21 to 100 ° C. .
  • Ar gas sputtering gas
  • the laminated film 22a of each test piece was etched with an etching solution (mixed solution of sulfuric acid, nitric acid and acetic acid), and the etching characteristics were examined.
  • etching solution mixed solution of sulfuric acid, nitric acid and acetic acid
  • a case where the difference in etching rate between the barrier film 25 and the metal low resistance layer 26 is small and etching is possible with the same etching solution is “ ⁇ ”, and a case where the etching rate is large and etching is not possible with the same etching solution. It was described in Table 1 as “ ⁇ ”.
  • the nickel target 111 was produced by changing the kind of the additive element, the laminated film 22a was formed using the nickel target 111, and a test piece was produced.
  • the formation conditions of the laminated film 22a other than the type of additive element were the same as described above.
  • the above “etching characteristics” and the following “adhesion” and “barrier properties” were examined.
  • a laminated film 22a was formed on the surface of the glass substrate to obtain a test piece.
  • On the surface on which the laminated film 22a of the test piece is formed put a 1mm square mass in 10 rows x 10 columns, a total of 100 notches, with a sharp knife at the tip, and stick adhesive tape (Scotch tape of model number 610) After the application, the number of films remaining when the adhesive tape was peeled off was evaluated. 0/100 when completely peeled, 100/100 when none peeled, and 90/100 or more is practically sufficient.
  • a laminated film 22a was formed on the surface of an amorphous silicon silicon substrate to obtain a test piece. After the laminated film 22a was removed by etching, the surface of the silicon substrate was observed with an electron microscope, and the surface having a smooth surface was defined as diffusion “ ⁇ ”, and the surface having irregularities formed thereon was defined as diffusion “x”. These test results are shown in Table 2 below together with the type of additive element added to the nickel target 111 and its content.
  • the experiment was conducted by changing the addition amounts of V, Al, Mo, Ti, Zr, Cr, Si, W, Ta, In, Sn, Zn, Mn, and Cu. As a result, even if the type of the additive element is changed, the etching characteristics are good if the content of the additive element is 50 atomic% or more, and the nickel target 111 is magnetized if the content of the additive element is less than 7 atomic%. The remaining magnetron sputtering was not performed normally.
  • a laminated film 22a is formed on the surface of the film formation target 21 (here, a glass substrate).
  • a resist (not shown) having an opening of a predetermined shape is disposed on the surface of the laminated film 22a, the laminated film 22a is exposed in the opening, and an etching solution is brought into contact therewith.
  • the metal low resistance layer 26 and the barrier film 25 are continuously etched away with the same etching solution, and the laminated film 22a is patterned into a predetermined shape.
  • reference numerals 12 and 15 denote electrodes made of the patterned laminated film 22a
  • reference numeral 12 denotes a storage capacitor electrode
  • reference numeral 15 denotes a gate electrode. Since the barrier film 25 containing Ni at 50 atomic% or less is disposed on the surface of the gate electrode 15 and the storage capacitor electrode 12 that is in close contact with the glass substrate 21, the gate electrode 15 and the storage capacitor electrode 12 are formed of a glass substrate. Adhesion to 21 is high.
  • the metal resistance layer 26 has an electric resistance lower than that of the barrier film 25, and the electric resistance of the gate electrode 15 and the storage capacitor electrode 12 is lower than that of an electrode constituted only by the barrier film 25. Resistance is low.
  • a gate insulating film 14 made of a silicon nitride thin film (SiN x ), a silicon layer 16 made of amorphous silicon, and an ohmic contact layer 17 are laminated in the order described, and a laminated film 22a is formed on the surface of the ohmic contact layer 17 in the steps of FIGS. 2A and 2B (FIG. 3B).
  • a resist (not shown) having an opening of a predetermined shape is disposed on the surface of the laminated film 22a, the laminated film 22a is exposed in the opening, and an etching solution is brought into contact therewith, so that the metal low resistance layer 26 and the barrier film 25 are exposed. Are continuously etched with the same etching solution, and the laminated film 22a is patterned. After the resist is removed, the ohmic contact layer 17 and the silicon layer 16 are patterned to obtain the thin film transistor 20 (FIG. 3C).
  • the gate insulating film 14 remains without being etched, the silicon layer 16 remains immediately above and on both sides of the gate electrode 15, and the other portions are removed by etching.
  • the ohmic contact layer 17 and the laminated film 22a remain on both sides of the gate electrode 15 and are separated by an opening formed directly above the gate electrode 15, and the first and second ohmic contact layers 31 and 32 and the source and drain electrodes 33 and 34 are formed.
  • the reference numeral 30 in the figure indicates a semiconductor layer composed of the remaining silicon layer 16 and the first and second ohmic contact layers 31 and 32.
  • the source and drain electrodes 33 and 34 are in close contact with the first and second ohmic contact layers 31 and 32 and are electrically connected to the semiconductor layer 30.
  • the silicon layer 16 has the same conductivity type (here, n-type) as the first and second ohmic contact layers 31 and 32, but has a low impurity concentration.
  • n-type conductivity type
  • the gate electrode 15 When a voltage is applied to the gate electrode 15, a low resistance storage layer is formed in a portion of the silicon layer 16 in contact with the gate electrode 15 via the gate insulating film 14, and the first and second ohmic contacts are formed via the storage layer.
  • Contact layers 31 and 32 are electrically connected.
  • the silicon layer 16 may have a conductivity type opposite to that of the first and second ohmic contact layers 31 and 32.
  • the inversion of the same conductivity type as that of the first and second ohmic contact layers 31 and 32 is applied to a portion of the silicon layer 16 in contact with the gate electrode 15 via the gate insulating film 14.
  • a layer is formed, and the first and second ohmic contact layers 31 and 32 are electrically connected by the inversion layer.
  • a passivation film 24 made of a silicon nitride thin film is formed on the surface of the glass substrate 21 on which the thin film transistor 20 is formed, and the drain electrode 34 of the passivation film 24 is formed.
  • a pixel electrode 27 made of a patterned transparent conductive film is disposed on the passivation film 24 (FIG. 3D).
  • the pixel electrode 27 is electrically connected to the drain electrode 34.
  • a current flows from the source electrode 33 to the drain electrode 34, and a voltage is applied to the pixel electrode 27.
  • the source electrode 33 and the drain electrode 34 are in close contact with the semiconductor layer 30 (first and second ohmic contact layers 31 and 32), respectively, but since the barrier film 25 is disposed in the close contact portion, the source, Copper does not diffuse from the drain electrodes 33 and 34 into the semiconductor layer 30.
  • the liquid crystal display device 50 is formed by arranging the liquid crystal 41 on the pixel electrode 27 of FIG. 3D and arranging the panel 40 on which the counter electrode 45 is formed on the surface of the glass substrate 42 on the liquid crystal 41. .
  • the voltage applied to the pixel electrode 27 and the counter electrode 45 can be controlled, and the light transmittance of the liquid crystal 41 can be controlled.
  • Reference numeral 60 in FIG. 5 shows a thin film transistor according to a second example of the present invention.
  • a single silicon layer 16 constitutes a semiconductor layer.
  • the source and drain electrodes 33 and 34 are in direct contact with and electrically connected to the silicon layer 16.
  • Reference numeral 70 in FIG. 6 shows a thin film transistor of the third example of the present invention.
  • This thin film transistor 70 is a top gate type (stagger type) thin film transistor, and has a semiconductor layer 71 disposed on the glass substrate 21.
  • a gate electrode 75 is disposed on the semiconductor layer 71 via a gate oxide film 72.
  • An interlayer insulating film 81 is disposed on the gate electrode 75, and the source and drain electrodes 73 and 74 are disposed on the interlayer insulating film 81.
  • the source and drain electrodes 73 and 74 are in contact with and electrically connected to the semiconductor layer 71 through through holes formed in the interlayer insulating film 81.
  • the source and drain electrodes 73 and 74 are covered with an interlayer insulating film 82.
  • a pixel electrode 85 is disposed on the interlayer insulating film 82, and the pixel electrode 85 is connected to the drain electrode 74 through a through hole formed in the interlayer insulating film 82.
  • At least one of the electrodes 73 to 75 among the gate electrode 75, the source electrode 73, and the drain electrode 74 is formed of the wiring film of the present invention, and the barrier film 25 is formed in a portion in close contact with the semiconductor layer 71. If the electrode is disposed, the electrodes 73 to 75 are difficult to peel off from the semiconductor layer 71 and copper diffusion into the semiconductor layer 71 is prevented.
  • the type and manufacturing method of the silicon layer 16 and the first and second ohmic contact layers 31 and 32 are not particularly limited.
  • a silicon layer amorphous silicon layer, polysilicon layer
  • those used for the silicon layer of the TFT can be widely used.
  • the constituent material of the semiconductor layers 30 and 71 is not limited to silicon, and an oxide semiconductor such as ZnO or In—Ga—Zn—O may be used as the main component of the semiconductor layers 30 and 71.
  • the wiring film manufactured by the target 111 of the present invention is not limited to the TFT electrode, and can be used for wiring films of other electronic components such as semiconductor elements and wiring boards.
  • the sputtering gas used for sputtering the nickel target 111 and the copper target 112 is not limited to Ar, and Ne, Xe, or the like can also be used.
  • the thickness of the metal low resistance layer 26 is not particularly limited. Since the specific resistance of the entire electrode becomes too high, the thickness of the barrier films 25 and 28 is preferably 1/3 or less of the total thickness of the electrode. Further, considering the adhesion to the semiconductor layer and the glass substrate and the diffusion preventing property, the film thickness of the barrier films 25 and 28 is preferably 10 nm or more.
  • An etchant (including an etchant and an etching gas) can etch the barrier films 25 and 28 and the metal low-resistance layer 26 and does not dissolve the silicon layer, the glass substrate, and the oxide semiconductor layer (or has an etching rate). It is not particularly limited as long as it is slow. As such an etchant, an etching solution for copper etching can be widely used.

Abstract

L'invention porte sur un transistor en couches minces hautement fiable. Le transistor en couches minces (20) comporte une électrode de grille (15) ; des électrodes de source/drain (33, 34) dont au moins une est munie d’un film de barrière (25). Le film de barrière (25) adhère à un substrat de verre (21) ou à une couche semi-conductrice (30) ; contient au moins 50 % atomique de Ni, ce qui assure son adhésion au substrat de verre (21) et à la couche semi-conductrice (30) ; de plus, lorsqu'une couche de résistance métallique (26) dont le contenu principal est Cu est formée sur la surface du film de barrière (25), Cu n’est pas diffusé dans la couche semi-conductrice (30).
PCT/JP2009/063185 2008-07-29 2009-07-23 Film de câblage, transistor en couches minces, cible, procédé de formation de film de câblage WO2010013636A1 (fr)

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