WO2009147719A1 - 試験システム - Google Patents

試験システム Download PDF

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Publication number
WO2009147719A1
WO2009147719A1 PCT/JP2008/060171 JP2008060171W WO2009147719A1 WO 2009147719 A1 WO2009147719 A1 WO 2009147719A1 JP 2008060171 W JP2008060171 W JP 2008060171W WO 2009147719 A1 WO2009147719 A1 WO 2009147719A1
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WO
WIPO (PCT)
Prior art keywords
wafer
semiconductor wafer
test
semiconductor
alignment mark
Prior art date
Application number
PCT/JP2008/060171
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
芳雄 甲元
芳春 梅村
康男 徳永
Original Assignee
株式会社アドバンテスト
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社アドバンテスト filed Critical 株式会社アドバンテスト
Priority to JP2010515689A priority Critical patent/JP5368440B2/ja
Priority to PCT/JP2008/060171 priority patent/WO2009147719A1/ja
Priority to TW098118028A priority patent/TW200952106A/zh
Publication of WO2009147719A1 publication Critical patent/WO2009147719A1/ja

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
    • G01R31/2891—Features relating to contacting the IC under test, e.g. probe heads; chucks related to sensing or controlling of force, position, temperature
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a test system for testing a semiconductor chip.
  • the present invention relates to a test system for testing a plurality of semiconductor chips formed on a semiconductor wafer.
  • the wafer under test and the probe card are unloaded from the inspection apparatus after the inspection is completed, and the wafer under test to be inspected next is adsorbed to the probe card. That is, not only the wafer to be tested but also the probe card must be unloaded from the inspection apparatus. For this reason, in the next test, both the alignment between the wafer under test and the probe card and the alignment of the probe card in the inspection apparatus must be adjusted. For this reason, the efficiency of a test will fall.
  • an object of the present invention is to provide a test system that can solve the above problems. This object is achieved by a combination of features described in the independent claims.
  • the dependent claims define further advantageous specific examples of the present invention.
  • a test system for testing a plurality of semiconductor chips formed on a semiconductor wafer, the chamber in which the semiconductor wafer is transferred, and the fixing in the chamber A test wafer provided with a plurality of bumps that are electrically connected to a plurality of semiconductor chip pads at once and a semiconductor wafer placed in the chamber and moved to test the semiconductor wafer
  • the semiconductor wafer is moved relative to the wafer stage so as to be placed on the wafer stage, the wafer stage being moved to a position opposite to the wafer, and the wafer stage.
  • the position of the alignment mark provided on the semiconductor wafer is determined.
  • a measuring unit for output, based on the position of the alignment mark measurement unit was measured, providing a test system comprising a position controller for adjusting the position of the placed semiconductor wafer on the wafer stage.
  • a test system for testing a plurality of semiconductor chips formed on a semiconductor wafer, a chamber in which the semiconductor wafer is transferred, and a pad of the plurality of semiconductor chips fixed in the chamber. And a test wafer provided with a plurality of bumps that are electrically connected together and a semiconductor wafer placed and moved in the chamber to move the semiconductor wafer to a position facing the test wafer A wafer stage to be moved, and a measurement unit that is provided in a movement path of the wafer stage and detects the position of the alignment mark provided on the semiconductor wafer by scanning at least a part of the surface of the semiconductor wafer placed on the wafer stage And position control to adjust the position of the semiconductor wafer based on the position of the alignment mark measured by the measurement unit Providing a test system comprising and.
  • FIG. 1 is a diagram showing an outline of a test system 400 according to one embodiment.
  • 2 is a diagram for explaining an outline of a test in a test system 400.
  • FIG. 5 is a diagram for explaining an example of a method for aligning a semiconductor wafer 300 at a predetermined position on a wafer stage 410.
  • FIG. A part of the image scanned by the measurement unit 406 is shown.
  • 2 is a diagram illustrating an example of an internal structure of a chamber 20.
  • FIG. It is a figure explaining the example which detects the alignment mark 226 while the wafer stage 410 is moving. It is a figure explaining the other example which detects the alignment mark 226 while the wafer stage 410 is moving.
  • 1 is an example of a cross-sectional view of a test wafer 100.
  • FIG. 3 is a diagram illustrating a configuration example of a circuit unit 110.
  • FIG. 2 is a diagram showing a configuration example in which a test wafer 100 and a semiconductor wafer
  • ⁇ Logic comparison unit 140 ⁇ Characteristic measurement unit, 142 ⁇ Power supply unit, 150 ⁇ Intermediate pad, 204 ⁇ Support unit, 212 ⁇ ⁇ ⁇ Device-side anisotropic conductive sheet, 213 ⁇ Penetration , 214... Device side seal portion, 218... Wafer side anisotropic conductive sheet, 219... Through hole, 220... Fixing ring, 222. 226 ... alignment mark, 230 ... intake path, 232 ... intake path, 234 ... decompression section, 236 ... decompressor, 238 ... decompressor, 240 ... through-hole, 242 ... through hole, 300 ... semiconductor wafer, 310 ... semiconductor chip, 400 ... test system, 402 ...
  • motherboard 404 ... performance board, 406 ... measurement unit, 407 ..Image sensor, 408... Wafer tray, 410... Wafer stage, 412... Horizontal stage, 416... Vertical stage, 418. Guide portion, wafer position detecting unit for 422 ... test, 450 ... position controller
  • FIG. 1 is a diagram showing an outline of a test system 400 according to one embodiment.
  • the test system 400 tests a plurality of semiconductor chips formed on the semiconductor wafer 300.
  • the test system 400 may test a plurality of semiconductor wafers 300 in parallel.
  • the test system 400 includes a control device 10, a plurality of chambers 20, a transfer unit 40, and a wafer cassette 60.
  • the control device 10 controls the test system 400.
  • the control device 10 may control the chamber 20, the transfer unit 40, and the wafer cassette 60.
  • the chamber 20 sequentially receives the semiconductor wafers 300 to be tested and tests the semiconductor wafers 300 inside the chamber 20.
  • Each chamber 20 may independently test the semiconductor wafer 300. That is, each chamber 20 may test the semiconductor wafer 300 without synchronizing with the other chambers 20.
  • the wafer cassette 60 stores a plurality of semiconductor wafers 300.
  • the transfer unit 40 sequentially transfers a plurality of semiconductor wafers 300 to be tested to the respective chambers 20. For example, the transfer unit 40 transfers each semiconductor wafer 300 stored in the wafer cassette 60 into one of the vacant chambers 20. Further, the transfer unit 40 may unload the semiconductor wafer 300 that has been tested from the chamber 20 and store it in the wafer cassette 60.
  • FIG. 2 is a diagram for explaining the outline of the test in the test system 400.
  • the test system 400 uses the test wafer 100 to test each semiconductor chip 310 of the semiconductor wafer 300.
  • the test wafer 100 is previously installed in each chamber 20 shown in FIG.
  • the test wafer 100 may be formed of the same semiconductor material as the semiconductor wafer 300 to be tested.
  • the semiconductor wafer 300 may be a disk-shaped semiconductor wafer. More specifically, the semiconductor wafer 300 may be silicon, a compound semiconductor, or other semiconductor wafers.
  • test wafer 100 may have substantially the same diameter as the semiconductor wafer 300 to be tested.
  • the semiconductor wafer 300 is aligned at a predetermined position facing the test wafer 100 in the chamber 20. Then, by moving the semiconductor wafer 300 so as to overlap the test wafer 100, the plurality of wafer-side connection pads 112 of the test wafer 100 and the inspection pads of the plurality of semiconductor chips 310 are collectively collected. Electrically connected.
  • the semiconductor wafer 300 is placed on a wafer stage in the chamber 20 and moved to a position facing the test wafer 100 by the wafer stage.
  • the relative positions of the test wafer 100 and the wafer stage are adjusted in advance.
  • the test system 400 may align the semiconductor wafer 300 at a predetermined position with respect to the test wafer 100 by placing the semiconductor wafer 300 at a predetermined position on the surface of the wafer stage.
  • a plurality of pads corresponding to the pads of the semiconductor chip 310 may be formed on the surface of the test wafer 100 facing the semiconductor wafer 300.
  • the test wafer 100 and the semiconductor wafer 300 may be electrically connected by direct contact, or may be electrically connected by non-contact coupling such as electrostatic coupling or inductive coupling. . Further, the test wafer 100 and the semiconductor wafer 300 may pass signals through the optical transmission path.
  • the test wafer 100 may be electrically connected to the semiconductor wafer 300 to be tested to transmit a signal between the control device 10 and the semiconductor wafer 300.
  • the semiconductor wafer 300 may supply the test signal generated by the control device 10 to each semiconductor chip 310 of the semiconductor wafer 300. Further, the test wafer 100 may transmit a signal output from each semiconductor chip 310 to the control device 10.
  • the test wafer 100 may include a plurality of circuit units 110 corresponding to the plurality of semiconductor chips 310.
  • the test wafer 100 may have a plurality of circuit units 110 in a one-to-one correspondence with the plurality of semiconductor chips 310.
  • Each circuit unit 110 may generate a signal to be supplied to the corresponding semiconductor chip 310, and may process a signal output from the corresponding semiconductor chip 310.
  • Each circuit unit 110 may independently test the corresponding semiconductor chip 310.
  • the control device 10 may supply power supply power, a control signal, and the like to each circuit unit 110.
  • FIG. 3 is a diagram for explaining an example of a method for aligning the semiconductor wafer 300 at a predetermined position on the wafer stage 410.
  • FIG. 3 shows a top view of the wafer stage 410 and the semiconductor wafer 300.
  • the test system 400 of this example includes a measurement unit 406 whose relative position with respect to the wafer stage 410 is predetermined.
  • An alignment mark 226 is formed at a predetermined position on the semiconductor wafer 300.
  • the measurement unit 406 scans at least a part of the surface of the semiconductor wafer 300 when the semiconductor wafer 300 is moving relative to the wafer stage 410 in order to place the semiconductor wafer 300 on the wafer stage 410.
  • the position of the alignment mark provided on the semiconductor wafer 300 is detected.
  • the measurement unit 406 is provided so as to image a predetermined fixed scan position in a region through which the semiconductor wafer 300 passes, and the semiconductor wafer 300 passes through the scan position, so that the surface of the semiconductor wafer 300 is detected. At least a portion may be scanned.
  • the measurement unit 406 may image the semiconductor wafer 300 that is provided on the wafer stage 410 and passes above.
  • the measurement unit 406 is provided above the wafer stage 410 and images the semiconductor wafer 300 that passes below. It's okay.
  • the transfer unit 40 controls in advance the relative position of the handler that holds and moves the semiconductor wafer 300 with respect to the semiconductor wafer 300. Therefore, before the semiconductor wafer 300 is transferred into the chamber 20, the relative position between the semiconductor wafer 300 and the wafer stage 410 is generally adjusted. Using 406, the position of the semiconductor wafer 300 is finely adjusted.
  • the measurement unit 406 is preferably provided at a position corresponding to the position of the alignment mark 226.
  • the test system 400 may be given in advance the position of the alignment mark 226 on the semiconductor wafer 300. As described above, the relative position between the semiconductor wafer 300 and the wafer stage 410 is generally adjusted before the semiconductor wafer 300 is transferred into the chamber 20.
  • the measurement unit 406 has an imaging range in a direction (hereinafter referred to as X direction) perpendicular to the traveling direction of the semiconductor wafer 300 (hereinafter referred to as Y direction). It may be provided to be smaller than the diameter.
  • the imaging range in the X direction of the measurement unit 406 may be about 2 to 3 times the alignment mark 226.
  • the measurement unit 406 includes a plurality of image sensors arranged at a predetermined pitch along the X direction so that the position of the alignment mark 226 in the X direction can be detected.
  • the measurement unit 406 may be provided so that the position in the X direction can be changed.
  • the test system 400 may change the position of the measurement unit 406 in the X direction based on position data of the alignment mark 226 given in advance.
  • a plurality of measuring units 406 may be provided at different positions on the X-direction axis. In this case, since the positions of the plurality of alignment marks 226 can be detected, the position of the semiconductor wafer 300 can be detected with higher accuracy.
  • FIG. 4 shows a part of an image scanned by the measurement unit 406.
  • the measurement unit 406 since the measurement unit 406 includes the plurality of image sensors 407 along the X direction, the position of the alignment mark 226 in the X direction can be detected with a resolution corresponding to the pitch of the image sensors 407.
  • the pitch of the imaging elements 407 is preferably smaller than the width of the alignment mark 226 in the X direction. Further, it is preferable that the pitch of the image pickup elements 407 is smaller than the allowable range of alignment errors determined according to the terminal widths of the semiconductor wafer 300 and the test wafer 100.
  • the test system 400 detects the position of each alignment mark 226 in the X direction from the image captured by each measurement unit 406.
  • the position control unit of the test system 400 may calculate the position in the Y direction of each alignment mark 226 based on the timing at which each measurement unit 406 detects each alignment mark 226. For example, the position control unit may detect the wafer stage based on how much the handler moves the semiconductor wafer 300 in the Y direction and places it on the wafer stage 410 after each measurement unit 406 detects the alignment mark 226. The position in the Y direction of the alignment mark 226 after the semiconductor wafer 300 is placed on 410 may be detected.
  • the position control unit of the test system 400 may calculate the rotation amount of the semiconductor wafer 300 based on the position in the X direction and the position in the Y direction of each alignment mark 226 detected by the method described above. .
  • the amount of rotation of the semiconductor wafer 300 indicates the amount of rotation of the semiconductor wafer 300 from its normal position around the center in a plane parallel to the wafer stage 410.
  • the position control unit of the test system 400 may calculate the rotation angle between the detected position of each alignment mark 226 and the normal position of the alignment mark 226 given in advance.
  • the rotation angle can be obtained from the difference between the detection position of the alignment mark 226 and the normal position of the alignment mark 226 in the X direction and the Y direction, and the distance from the center of the semiconductor wafer 300 to the alignment mark 226.
  • the position controller of the test system 400 may be given a distance between the center of the semiconductor wafer 300 and the alignment mark 226 in advance.
  • the position control unit of the test system 400 may control the wafer stage 410 based on the position in the X direction, the position in the Y direction, and the rotation amount of the alignment mark 226 detected by the method described above.
  • Wafer stage 410 has a horizontal stage that can adjust the X direction, the Y direction, and the amount of rotation with semiconductor wafer 300 placed thereon. Further, the position control unit of the test system 400 controls the horizontal stage based on the position of the alignment mark 226 measured by the measurement unit 406, so that the X direction and Y direction of the semiconductor wafer 300 placed on the wafer stage 410 are controlled. The position and the amount of rotation may be adjusted.
  • FIG. 5 is a diagram showing an example of the internal structure of the chamber 20.
  • the semiconductor wafer 300 to be tested is sequentially transferred to the chamber 20 and is electrically connected to the test wafer 100 fixed in the chamber 20.
  • a test wafer 100 Inside the chamber 20, a test wafer 100, a performance board 404, a mother board 402, a wafer tray 408, a wafer stage 410, a guide unit 420, a stage support unit 418, a measurement unit 406, and a position control unit 450 are provided.
  • the test wafer 100 is fixed in the chamber 20.
  • the test wafer 100 is fixed to the performance board 404 in the chamber 20.
  • the performance board 404 may be a printed board on which wiring is formed, for example.
  • the performance board 404 may be fixed to the mother board 402 in the chamber 20.
  • the mother board 402 transmits a signal between the control device 10 and the test wafer 100 via the performance board 404.
  • a membrane having a plurality of bumps is provided on the surface of the test wafer 100 that faces the semiconductor wafer 300.
  • the test wafer 100 is electrically connected collectively to the pads of the plurality of semiconductor wafers 300 formed on the semiconductor wafer 300 by the plurality of bumps.
  • the wafer stage 410 places and moves the semiconductor wafer 300 in the chamber 20.
  • the semiconductor wafer 300 is fixed to the wafer tray 408 by suction or the like, and the wafer stage 410 places the wafer tray 408 thereon.
  • Wafer stage 410 is connected to guide unit 420 via stage support unit 418 and moves along guide unit 420.
  • the guide unit 420 moves the wafer stage 410 along a predetermined path between a receiving position A where the semiconductor wafer 300 is received from the transfer unit 40 and a predetermined position B facing the test wafer 100.
  • the guide part 420 may be a rail provided along the predetermined route.
  • the wafer stage 410 moves to a predetermined position B facing the test wafer 100, and then moves the semiconductor wafer 300 in the vertical direction so as to be electrically connected to the test wafer 100.
  • the wafer stage 410 has a horizontal stage 412 and a vertical stage 416.
  • the horizontal stage 412 mounts the wafer tray 408 and adjusts the position of the semiconductor wafer 300 in a plane parallel to the surface of the semiconductor wafer 300.
  • the horizontal stage 412 adjusts the position of the semiconductor wafer 300 in the X and Y directions in the plane and the amount of rotation of the semiconductor wafer 300 in the plane. Thereby, the position of the semiconductor wafer 300 can be adjusted so that each pad of the semiconductor wafer 300 is electrically connected to each bump of the test wafer 100.
  • the vertical stage 416 mounts the horizontal stage 412 and controls the position of the horizontal stage 412 in the vertical direction.
  • the vertical stage 416 causes the semiconductor wafer 300 and the test wafer 100 to be electrically connected by bringing the horizontal stage 412 on which the semiconductor wafer 300 is placed close to the test wafer 100 at a position facing the test wafer 100. You may connect to.
  • the vertical stage 416 brings the semiconductor wafer 300 close to the test wafer 100 to a predetermined distance, the space between the semiconductor wafer 300 and the test wafer 100 is depressurized, thereby the semiconductor wafer 300.
  • the test wafer 100 may be electrically connected.
  • a stage support 418 may be fixed to the vertical stage 416.
  • the position control unit 450 controls the position of the wafer stage 410 based on the image captured by the measurement unit 406 as described with reference to FIG.
  • the position controller 450 controls the position of the horizontal stage 412 to adjust the position of the semiconductor wafer 300 so that each pad of the semiconductor wafer 300 is disposed at a position corresponding to each bump of the test wafer 100. To do.
  • the test wafer position detector 422 is fixed to the wafer stage 410 and measures the position of the test wafer 100 in advance.
  • the test wafer position detection unit 422 may measure in advance the relative position in the horizontal plane of the alignment mark of the test wafer 100 with respect to the wafer stage 410 arranged at the predetermined position B. Since the position of the horizontal stage 412 varies in the horizontal plane, the test wafer position detection unit 422 is preferably provided on the vertical stage 416.
  • the position controller 450 controls the horizontal stage 412 further based on the position of the test wafer 100 measured by the test wafer position detector 422 in order to connect the terminals of the test wafer 100 and the semiconductor wafer 300 with high accuracy. It's okay.
  • the position of the semiconductor wafer 300 with respect to the test wafer 100 can be adjusted, and the plurality of terminals of the semiconductor wafer 300 and the plurality of terminals of the test wafer 100 can be electrically connected.
  • the test wafer position detection unit 422 measures the position of the test wafer 100 every time the semiconductor wafer 300 is replaced. Not necessary.
  • the test wafer position detection unit 422 may measure the position of the test wafer 100 for each predetermined period. For this reason, a plurality of semiconductor wafers 300 can be efficiently tested.
  • the measurement unit 406 detects the position of the alignment mark 226 on the semiconductor wafer 300 while moving the semiconductor wafer 300 to place it on the wafer stage 410.
  • the measurement unit 406 places the semiconductor wafer 300 on the wafer stage 410 and moves the position of the alignment mark 226 on the semiconductor wafer 300 while the wafer stage 410 is moving from position A to position B. It may be detected.
  • the measurement unit 406 is provided on the moving path of the wafer stage 410 and scans at least a part of the surface of the semiconductor wafer 300 placed on the moving wafer stage 410.
  • FIG. 6 is a diagram illustrating an example in which the alignment mark 226 is detected while the wafer stage 410 is moving.
  • the measurement unit 406 of this example is fixed at a predetermined position with respect to the mother board 402 and images a part of the semiconductor wafer 300 passing below.
  • the traveling direction of the wafer stage 410 is the Y direction
  • the direction perpendicular to the traveling direction is the X direction.
  • the measurement unit 406 detects an image similar to that of the measurement unit 406 described with reference to FIGS. Further, the position control unit 450 controls the horizontal stage 412 based on the image detected by the measurement unit 406.
  • the position control unit 450 may detect the position of the alignment mark 226 in the Y direction based on the position of the wafer stage 410 in the Y direction when the measurement unit 406 detects the alignment mark 226.
  • the position of the alignment mark 226 in the Y direction can be detected from the difference between the position in the Y direction of the wafer stage 410 when the measurement unit 406 detects the alignment mark 226 and the position B in the Y direction shown in FIG. it can.
  • the position controller 450 adjusts the position of the horizontal stage 412 in the X direction and the Y direction and the amount of rotation based on the positions of the alignment marks 226 detected in this way in the X direction and the Y direction. As described above, even while the wafer stage 410 is moving, the position of the alignment mark 226 in the X direction and the Y direction can be detected and the position of the semiconductor wafer 300 can be adjusted.
  • FIG. 7 is a diagram for explaining another example of detecting the alignment mark 226 while the wafer stage 410 is moving.
  • the test system 400 of this example includes one measurement unit 406.
  • the alignment mark 226 is similarly used using the single measuring unit 406. May be detected.
  • the semiconductor wafer 300 may be provided with a plurality of alignment marks 226 at substantially the same position on the axis in the X direction, as shown in FIG.
  • the measurement unit 406 is arranged so that the positions of these alignment marks 226 can be detected. Even with such a configuration, it is possible to detect a positional shift and a rotation amount of the semiconductor wafer 300 in the X direction and the Y direction.
  • FIGS. 3 to 7 show the rectangular alignment mark 226 as an example, the shape of the alignment mark 226 is not limited to the shape.
  • the alignment mark 226 may have a predetermined shape such as a cross. Further, the alignment mark 226 may have a plurality of pads arranged along a predetermined shape.
  • FIG. 8 is an example of a cross-sectional view of the test wafer 100.
  • the test wafer 100 of this example transmits signals between the control device 10 and the semiconductor wafer 300.
  • the test wafer 100 includes a wafer side connection pad 112, an apparatus side connection pad 114, a through hole 116, an intermediate pad 150, and a wiring 117.
  • the test wafer 100 has a wafer connection surface 102 and an apparatus connection surface 104 formed on the back surface of the wafer connection surface 102.
  • Wafer connection surface 102 may refer to the surface facing semiconductor wafer 300.
  • the device connection surface 104 may refer to a surface that is electrically connected to the control device 10.
  • the plurality of wafer side connection pads 112 are formed on the wafer connection surface 102 of the test wafer 100. Further, at least one wafer side connection pad 112 is provided for each semiconductor chip 310. For example, one wafer side connection pad 112 may be provided for each input / output terminal of each semiconductor chip 310. That is, when each semiconductor chip 310 has a plurality of input / output terminals, a plurality of wafer side connection pads 112 may be provided for each semiconductor chip 310.
  • the respective wafer side connection pads 112 are provided at the same intervals as the respective input / output terminals in the semiconductor wafer 300 and are electrically connected to the corresponding input / output terminals of the semiconductor chip 310.
  • “electrically connected” may refer to a state in which an electric signal can be transmitted between two members.
  • the wafer side connection pads 112 and the input / output terminals of the semiconductor chip 310 may be electrically connected by direct contact or indirectly through other conductors.
  • the wafer side connection pads 112 of this example are electrically connected to the input / output terminals of the semiconductor chip 310 via a membrane described later in FIG. Bumps are formed on the membrane at positions corresponding to the pads.
  • the input / output terminals of the wafer side connection pads 112 and the semiconductor chip 310 may be electrically connected in a non-contact state, such as capacitive coupling (electrostatic coupling) or inductive coupling (magnetic coupling). Further, a part of the transmission line between the wafer side connection pad 112 and the input / output terminal of the semiconductor chip 310 may be an optical transmission line.
  • the plurality of device side connection pads 114 are formed on the device connection surface 104 of the test wafer 100 and are electrically connected to the performance board 404.
  • the device side connection pads 114 are provided in one-to-one correspondence with the plurality of wafer side connection pads 112.
  • the device side connection pads 114 are provided at the same intervals as the terminals of the performance board 404. Therefore, as shown in FIG. 8, the apparatus side connection pads 114 may be provided at a different interval from the wafer side connection pads 112.
  • the through hole 116, the intermediate pad 150, and the wiring 117 are formed on the test wafer 100, and electrically connect the corresponding wafer side connection pad 112 and the apparatus side connection pad 114.
  • the intermediate pad 150 is provided at a position facing the wafer side connection pad 112 on the apparatus connection surface 104.
  • the through hole 116 is formed through the test wafer 100 so that one end is connected to the wafer side connection pad 112 and the other end is connected to the intermediate pad 150.
  • the wiring 117 electrically connects the intermediate pad 150 and the device-side connection pad 114 on the device connection surface 104. With such a configuration, the apparatus side connection pads 114 and the wafer side connection pads 112 having different arrangement intervals are electrically connected.
  • the wafer side connection pads 112 are arranged at the same intervals as the input terminals so as to be electrically connected to the input terminals of the semiconductor chip 310. For this reason, as shown in FIG. 2, for example, the wafer side connection pads 112 are provided in a predetermined region for each semiconductor chip 310 at a minute interval.
  • the device-side connection pads 114 may be provided at intervals wider than the intervals between the plurality of wafer-side connection pads 112 corresponding to one semiconductor chip 310.
  • the device side connection pads 114 may be arranged at equal intervals in the surface of the device connection surface 104 so that the distribution of the device side connection pads 114 is substantially uniform.
  • test wafer 100 of this example is formed of the same semiconductor material as that of the semiconductor wafer 300, the electrical connection between the test wafer 100 and the semiconductor wafer 300 can be achieved even when the ambient temperature varies. Connection can be maintained well. For this reason, for example, even when the test is performed by heating the semiconductor wafer 300, the semiconductor wafer 300 can be accurately tested.
  • the test wafer 100 is formed of a semiconductor material, a large number of wafer side connection pads 112 and the like can be easily formed on the test wafer 100.
  • the wafer-side connection pad 112, the device-side connection pad 114, the through hole 116, and the wiring 117 can be easily formed by a semiconductor process using exposure or the like. Therefore, a large number of wafer side connection pads 112 corresponding to a large number of semiconductor chips 310 can be easily formed on the test wafer 100.
  • the terminals of the test wafer 100 may be formed by plating, evaporating, or the like on the test wafer 100 with a conductive material.
  • FIG. 9 is a diagram illustrating a configuration example of the circuit unit 110.
  • the circuit unit 110 includes a pattern generation unit 122, a waveform shaping unit 130, a driver 132, a comparator 134, a timing generation unit 136, a logic comparison unit 138, a characteristic measurement unit 140, and a power supply unit 142.
  • the circuit unit 110 may have the configuration shown in FIG. 9 for each input / output pin of the semiconductor chip 310 to be connected.
  • the pattern generator 122 generates a logic pattern of the test signal.
  • the pattern generation unit 122 of this example includes a pattern memory 124, an expected value memory 126, and a fail memory 128.
  • the pattern generator 122 may output a logical pattern stored in advance in the pattern memory 124.
  • the pattern memory 124 may store a logical pattern given from the control device 10 before starting the test.
  • the pattern generator 122 may generate the logical pattern based on an algorithm given in advance.
  • the waveform shaping unit 130 shapes the waveform of the test signal based on the logical pattern given from the pattern generation unit 122.
  • the waveform shaping unit 130 may shape the waveform of the test signal by outputting a voltage corresponding to each logic value of the logic pattern for each predetermined bit period.
  • the driver 132 outputs a test signal corresponding to the waveform given from the waveform shaping unit 130.
  • the driver 132 may output a test signal in accordance with the timing signal given from the timing generator 136.
  • the driver 132 may output a test signal having the same cycle as the timing signal.
  • the test signal output from the driver 132 is supplied to the corresponding semiconductor chip 310 via a switching unit or the like.
  • the comparator 134 measures the response signal output from the semiconductor chip 310.
  • the comparator 134 may measure the logical pattern of the response signal by sequentially detecting the logical value of the response signal in accordance with the strobe signal supplied from the timing generator 136.
  • the logic comparison unit 138 functions as a determination unit that determines the quality of the corresponding semiconductor chip 310 based on the logic pattern of the response signal measured by the comparator 134. For example, the logic comparison unit 138 may determine the quality of the semiconductor chip 310 based on whether or not the expected value pattern given from the pattern generation unit 122 matches the logic pattern detected by the comparator 134.
  • the pattern generation unit 122 may supply the expected value pattern stored in advance in the expected value memory 126 to the logic comparison unit 138.
  • the expected value memory 126 may store a logic pattern given from the control device 10 before the test is started.
  • the pattern generation unit 122 may generate the expected value pattern based on an algorithm given in advance.
  • the fail memory 128 stores the comparison result in the logical comparison unit 138.
  • the fail memory 128 may store the pass / fail judgment result in the logic comparison unit 138 for each address of the semiconductor chip 310.
  • the control device 10 may read the pass / fail judgment result stored in the fail memory 128.
  • the apparatus-side connection pad 114 may output the pass / fail determination result stored in the fail memory 128 to the control apparatus 10 outside the test wafer 100.
  • the characteristic measurement unit 140 measures the voltage or current waveform output by the driver 132.
  • the characteristic measurement unit 140 may function as a determination unit that determines whether the semiconductor chip 310 is good or not based on whether a waveform of a current or voltage supplied from the driver 132 to the semiconductor chip 310 satisfies a predetermined specification. .
  • the power supply unit 142 supplies power for driving the semiconductor chip 310.
  • the power supply unit 142 may supply power to the semiconductor chip 310 according to the power supplied from the control device 10 during the test. Further, the power supply unit 142 may supply driving power to each component of the circuit unit 110.
  • the test system 400 in which the scale of the control device 10 is reduced can be realized.
  • a general-purpose personal computer or the like can be used as the control device 10.
  • FIG. 10 is a diagram illustrating a configuration example in which the test wafer 100 and the semiconductor wafer 300 are electrically connected.
  • the test system 400 of this example places the test wafer 100 and the semiconductor wafer 300 in a sealed space, and depressurizes the sealed space, thereby bringing the test wafer 100 and the semiconductor wafer 300 close to each other and making electrical Connect to.
  • a sealed space is formed between the performance board 404 to which the test wafer 100 is fixed and the wafer tray 408 on which the semiconductor wafer 300 is placed.
  • An anisotropic conductive sheet is provided between the performance board 404, the test wafer 100, and the semiconductor wafer 300. Then, by reducing the pressure in the sealed space, the anisotropic conductive sheet is pressed by the test wafer 100 or the like, and the test wafer 100 or the like is electrically connected. Therefore, the test wafer 100 is fixed to the performance board 404 so as to be movable in the vertical direction.
  • the range in which the test wafer 100 can be moved in the horizontal direction is preferably within an allowable range of alignment error between the test wafer 100 and the semiconductor wafer 300.
  • the range in which the test wafer 100 can move in the horizontal direction is preferably sufficiently smaller than the pad width of the test wafer 100 and the semiconductor wafer 300.
  • the test wafer 100 is fixed to the performance board 404 by the support unit 204.
  • the support unit 204 fixes the device-side anisotropic conductive sheet 212, the device-side seal 214, the test wafer 100, the wafer-side anisotropic conductive sheet 218, the membrane 222, and the fixing ring 220 to the performance board 404.
  • the apparatus-side anisotropic conductive sheet 212 is provided between the test wafer 100 and the performance board 404 and is electrically pressed to electrically connect the electrode of the test wafer 100 and the electrode of the performance board 404. .
  • the test wafer 100 presses the apparatus-side anisotropic conductive sheet 212 so that the position in the vertical direction with respect to the lower surface of the performance board 404 can be displaced within a predetermined range to the extent that it can be electrically connected to the performance board 404. Supported.
  • the device-side seal 214 is provided along the periphery of the surface of the membrane 222 on the performance board 404 side, and seals between the periphery of the surface of the membrane 222 on the performance board 404 side and the performance board 404.
  • the device-side seal portion 214 may be formed of an elastic material having elasticity to the extent that the membrane 222 can be electrically connected to the performance board 404 via the device-side anisotropic conductive sheet 212.
  • the wafer side anisotropic conductive sheet 218 is provided between the test wafer 100 and the membrane 222.
  • the wafer side anisotropic conductive sheet 218 is pressed, the wafer side connection terminal provided on the surface of the test wafer 100 on the semiconductor wafer 300 side and the bump terminal of the membrane 222 are electrically connected.
  • the membrane 222 is provided between the wafer side anisotropic conductive sheet 218 and the semiconductor wafer 300.
  • the membrane 222 may have bump terminals that electrically connect the terminals of the semiconductor wafer 300 and the wafer-side connection terminals of the test wafer 100.
  • the fixing ring 220 fixes the membrane 222 to the device-side seal portion 214.
  • the fixing ring 220 may be provided in an annular shape along the peripheral edge of the surface of the membrane 222 on the semiconductor wafer 300 side.
  • the inner diameter of the fixing ring 220 may be larger than the diameters of the wafer side anisotropic conductive sheet 218 and the semiconductor wafer 300.
  • the membrane 222 has a circular shape having substantially the same diameter as that of the fixing ring 220, and an end portion thereof is fixed to the fixing ring 220.
  • the apparatus-side anisotropic conductive sheet 212, the test wafer 100, and the wafer-side anisotropic conductive sheet 218 are disposed between the membrane 222 and the performance board 404. Held in position. As shown in FIG. 10, a gap may be provided between the apparatus-side anisotropic conductive sheet 212, the test wafer 100, the wafer-side anisotropic conductive sheet 218, and the apparatus-side seal portion 214. . With such a configuration, the semiconductor wafer 300 and the test wafer 100 can be electrically connected by pressing the membrane 222 with the semiconductor wafer 300.
  • the support unit 204 may support the membrane 222 and the like by supporting the fixing ring 220.
  • the support unit 204 supports the test wafer 100 so that the membrane 222 can approach the lower surface of the performance board 404 within a predetermined range.
  • the support unit 204 supports the lower end of the fixing ring 220 at a position away from the lower surface of the performance board 404 by a predetermined distance so that the lower end of the fixing ring 220 cannot exceed a predetermined distance from the lower surface of the performance board 404. You can do it.
  • the wafer tray 408 is provided so as to form a sealed space with the performance board 404 when placed at a predetermined position.
  • the wafer tray 408 of this example forms a sealed space with the performance board 404, the apparatus-side seal 214, and the wafer-side seal 224.
  • the wafer tray 408 places the semiconductor wafer 300 on the surface of the sealed space side.
  • the wafer side seal portion 224 is provided along the region corresponding to the peripheral portion of the membrane 222 on the surface of the wafer tray 408, and seals between the peripheral portion of the surface of the membrane 222 on the wafer tray side and the wafer tray 408.
  • the wafer side seal portion 224 may be formed in an annular shape on the surface of the wafer tray 408.
  • the wafer-side seal portion 224 may be formed in a lip shape in which the annular diameter increases as the distance from the surface of the wafer tray 408 increases.
  • the tip of the wafer-side seal portion 224 bends according to the pressing force, thereby bringing the distance between the membrane 222 and the semiconductor wafer 300 closer.
  • the wafer-side seal portion 224 is formed so that the height from the surface of the wafer tray 408 is higher than the height of the semiconductor wafer 300 when not pressed against the membrane 222.
  • the vertical stage 416 described with reference to FIG. 5 moves the wafer tray 408 to a position where the upper end portion of the wafer-side seal portion 224 is in close contact with the membrane 222.
  • the performance board 404, the wafer tray 408, the apparatus-side seal portion 214, and the wafer-side seal portion 224 can form a sealed space in which the test wafer 100 and the semiconductor wafer 300 are stored.
  • the horizontal stage 412 preferably adjusts the position and inclination of the semiconductor wafer 300 in the horizontal plane before the vertical stage 416 moves the wafer tray 408 in the vertical direction.
  • the decompression unit 234 decompresses the sealed space between the performance board 404 and the wafer tray 408, which is formed by the performance board 404, the wafer tray 408, the apparatus side seal unit 214, and the wafer side seal unit 224.
  • the decompression unit 234 decompresses the sealed space after the wafer stage 410 moves the wafer tray 408 to form the sealed space.
  • the decompression unit 234 moves the wafer tray 408 closer to the performance board 404 to a predetermined position.
  • the wafer tray 408 is disposed at the predetermined position, thereby applying a pressing force to the apparatus-side anisotropic conductive sheet 212 and the wafer-side anisotropic conductive sheet 218 to electrically connect the performance board 404 and the test wafer 100.
  • the test wafer 100 and the semiconductor wafer 300 are electrically connected.
  • the wafer side seal portion 224 may contact the membrane 222 inside the fixing ring 220.
  • the membrane 222 divides the sealed space into a space on the performance board 404 side and a space on the wafer tray 408 side. For this reason, it is preferable that the membrane 222 is provided with a through hole 242 connecting these spaces.
  • the test wafer 100, the apparatus-side anisotropic conductive sheet 212, and the wafer-side anisotropic conductive sheet 218 are also provided with a through hole 240, a through hole 213, and a through hole 219.
  • the through-holes provided in the membrane 222, the test wafer 100, the apparatus-side anisotropic conductive sheet 212, and the wafer-side anisotropic conductive sheet 218 are preferably distributed substantially uniformly in each plane. With such a configuration, the air sucked in the process of depressurizing the sealed space flows in a dispersed manner through the many through holes.
  • the through hole 242, the through hole 240, the through hole 213, and the through hole 219 may be provided at corresponding positions, or may be provided at different positions.
  • the pressing force applied to the apparatus-side anisotropic conductive sheet 212 and the wafer-side anisotropic conductive sheet 218 is distributed substantially evenly in the respective planes. Stress strain can be greatly reduced. For this reason, it is possible to prevent cracking of the test wafer 100, distortion of the anisotropic conductive sheet, and the like.
  • the space between the performance board 404 and the membrane 222 and the space between the membrane 222 and the semiconductor wafer 300 can be decompressed with a single decompression unit 234.
  • the decompression unit 234 may adsorb the semiconductor wafer 300 to the wafer tray 408.
  • the decompression unit 234 of this example includes a decompressor 236 for a sealed space and a decompressor 238 for a semiconductor wafer.
  • the wafer tray 408 is formed with an air intake path 232 for a sealed space and an air intake path 230 for a semiconductor wafer.
  • the test wafer 100 fixed to the performance board 404 and the semiconductor wafer 300 can be electrically connected. As described above, since the test wafer 100 is fixed to the performance board 404, alignment between the test wafer 100 and the semiconductor wafer 300 can be easily performed.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
PCT/JP2008/060171 2008-06-02 2008-06-02 試験システム WO2009147719A1 (ja)

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TW098118028A TW200952106A (en) 2008-06-02 2009-06-01 Test system

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JP2019087720A (ja) * 2017-10-31 2019-06-06 合同会社Ｐｌｅｓｏｎ 半導体ウエハーの試験ユニット
CN114779034A (zh) * 2022-04-13 2022-07-22 苏州晶睿半导体科技有限公司 一种基于半导体晶圆的测试设备和map图偏移检测方法

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JP6308639B1 (ja) * 2017-08-07 2018-04-11 株式会社テクノホロン プロービングステーション

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JPS6394653A (ja) * 1986-10-09 1988-04-25 Tatsumo Kk 基板の自動位置合せ方法及び装置
JPH11274252A (ja) * 1998-03-19 1999-10-08 Mitsubishi Electric Corp 半導体装置の検査装置及びその検査方法
JP2000164655A (ja) * 1998-11-24 2000-06-16 Matsushita Electric Ind Co Ltd アライメント装置及びアライメント方法
JP2007027302A (ja) * 2005-07-14 2007-02-01 Denso Corp 検査装置及び検査装置の位置決め方法

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JPS6394653A (ja) * 1986-10-09 1988-04-25 Tatsumo Kk 基板の自動位置合せ方法及び装置
JPH11274252A (ja) * 1998-03-19 1999-10-08 Mitsubishi Electric Corp 半導体装置の検査装置及びその検査方法
JP2000164655A (ja) * 1998-11-24 2000-06-16 Matsushita Electric Ind Co Ltd アライメント装置及びアライメント方法
JP2007027302A (ja) * 2005-07-14 2007-02-01 Denso Corp 検査装置及び検査装置の位置決め方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019087720A (ja) * 2017-10-31 2019-06-06 合同会社Ｐｌｅｓｏｎ 半導体ウエハーの試験ユニット
WO2019176238A1 (ja) * 2017-10-31 2019-09-19 合同会社Ｐｌｅｓｏｎ 半導体ウエハーの試験ユニット
CN114779034A (zh) * 2022-04-13 2022-07-22 苏州晶睿半导体科技有限公司 一种基于半导体晶圆的测试设备和map图偏移检测方法

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JPWO2009147719A1 (ja) 2011-10-20
TW200952106A (en) 2009-12-16
TWI379369B (enrdf_load_stackoverflow) 2012-12-11
JP5368440B2 (ja) 2013-12-18

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