WO2009130822A1 - 多層配線、半導体装置、表示装置用基板及び表示装置 - Google Patents
多層配線、半導体装置、表示装置用基板及び表示装置 Download PDFInfo
- Publication number
- WO2009130822A1 WO2009130822A1 PCT/JP2008/072665 JP2008072665W WO2009130822A1 WO 2009130822 A1 WO2009130822 A1 WO 2009130822A1 JP 2008072665 W JP2008072665 W JP 2008072665W WO 2009130822 A1 WO2009130822 A1 WO 2009130822A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- conductor
- substrate
- wiring
- layer
- insulating film
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 184
- 239000004065 semiconductor Substances 0.000 title claims abstract description 70
- 239000004020 conductor Substances 0.000 claims abstract description 136
- 239000010408 film Substances 0.000 claims description 225
- 230000002093 peripheral effect Effects 0.000 claims description 12
- 239000010409 thin film Substances 0.000 claims description 9
- 238000009413 insulation Methods 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract description 29
- 230000006866 deterioration Effects 0.000 abstract description 16
- 239000010410 layer Substances 0.000 description 278
- 239000011229 interlayer Substances 0.000 description 87
- 239000000463 material Substances 0.000 description 58
- 239000012535 impurity Substances 0.000 description 55
- 238000000034 method Methods 0.000 description 25
- 230000008569 process Effects 0.000 description 15
- 229910052751 metal Inorganic materials 0.000 description 13
- 239000002184 metal Substances 0.000 description 13
- 238000000206 photolithography Methods 0.000 description 13
- 238000004544 sputter deposition Methods 0.000 description 12
- 239000011347 resin Substances 0.000 description 9
- 229920005989 resin Polymers 0.000 description 9
- 239000010936 titanium Substances 0.000 description 9
- 239000000956 alloy Substances 0.000 description 8
- 229910052719 titanium Inorganic materials 0.000 description 8
- 229910004298 SiO 2 Inorganic materials 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 7
- 150000001875 compounds Chemical class 0.000 description 7
- 238000002425 crystallisation Methods 0.000 description 7
- 230000006870 function Effects 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 239000010949 copper Substances 0.000 description 6
- 239000011521 glass Substances 0.000 description 6
- 238000002844 melting Methods 0.000 description 6
- 230000008018 melting Effects 0.000 description 6
- 229910052750 molybdenum Inorganic materials 0.000 description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000004973 liquid crystal related substance Substances 0.000 description 5
- 150000002739 metals Chemical class 0.000 description 5
- 229910052698 phosphorus Inorganic materials 0.000 description 5
- 239000011574 phosphorus Substances 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 230000009471 action Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 230000001934 delay Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000004528 spin coating Methods 0.000 description 3
- 239000004925 Acrylic resin Substances 0.000 description 2
- 229920000178 Acrylic resin Polymers 0.000 description 2
- 206010034972 Photosensitivity reaction Diseases 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000002585 base Substances 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 239000003054 catalyst Substances 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000005401 electroluminescence Methods 0.000 description 2
- 230000001747 exhibiting effect Effects 0.000 description 2
- 238000005984 hydrogenation reaction Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 230000036211 photosensitivity Effects 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 239000003870 refractory metal Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 239000004952 Polyamide Substances 0.000 description 1
- 229910018540 Si C Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910052783 alkali metal Inorganic materials 0.000 description 1
- 150000001340 alkali metals Chemical class 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 150000001408 amides Chemical class 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005499 laser crystallization Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- -1 or Mo Substances 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920000052 poly(p-xylylene) Polymers 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 229920001690 polydopamine Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/13606—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit having means for reducing parasitic capacitance
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/13629—Multilayer wirings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
Definitions
- the present invention relates to a multilayer wiring, a semiconductor device, a display device substrate, and a display device. More specifically, the present invention relates to a multilayer wiring, a semiconductor device, a display device substrate, and a display device that are suitable for mobile devices such as mobile phones.
- a peripheral circuit region (frame region) is increased by forming a pixel driving circuit on the display device substrate.
- a technique for advancing the narrowing of the frame a multi-layer wiring that multi-layers the wiring configuring the peripheral circuit has been developed.
- FIG. 2 is a schematic cross-sectional view showing a conventional display device substrate.
- a conventional display device substrate 1100a includes a semiconductor layer 1102 having a channel region 1102a and high-concentration impurity regions 1102b and 1102c on one main surface side of a substrate 1101, a gate insulating film 1103, A wiring layer 1121, an interlayer insulating film 1131 having contact holes 1141a and 1141b, a wiring layer 1122, an interlayer insulating film 1132 having a through hole 1142, a wiring layer 1123, and an interlayer insulating film 1133 having a through hole 1143;
- This is a multilayer wiring board having a structure in which the pixel electrode 1105 is laminated in this order from the substrate 1101 side.
- the display device substrate 1100a includes a top gate type (planar type) including a semiconductor layer 1102, a gate insulating film 1103, and a gate electrode 1104 formed over the channel region 1102a by a wiring layer 1121.
- a pixel transistor 1110 which is a thin film transistor (TFT) is provided.
- the contact hole 1141a penetrates the interlayer insulating film 1131 and the gate insulating film 1103, and is a connection provided to electrically connect the lower layer connection wiring (lower layer wiring) 1107 located in the wiring layer 1122 to the high concentration impurity region 1102b. It is a hole.
- the contact hole 1141b is a connection hole provided to electrically connect the source wiring 1106 located in the wiring layer 1122 to the high-concentration impurity region 1102c.
- the through hole 1142 is a connection hole that penetrates the interlayer insulating film 1132 and is provided to electrically connect the upper layer connection wiring (upper layer wiring) 1108 located in the wiring layer 1123 to the lower layer connection wiring 1107.
- the through hole 1143 is a connection hole provided to penetrate the interlayer insulating film 1133 and electrically connect the pixel electrode 1105 to the upper layer connection wiring 1108.
- the first wiring formed over the substrate having an insulating surface A first interlayer insulating film formed over the first wiring; a second wiring formed over the first interlayer insulating film; and a second formed over the second wiring.
- the width of the third wiring is wider than the width of the first and second wirings, and the second wiring A wiring board is disclosed in which the width is wider than the width of the first wiring and the diameter or area of the second contact hole is larger than the diameter or area of the first contact hole (see, for example, Patent Document 1). .) JP 2005-72573 A
- the lower layer connection wiring 1107 and the upper layer connection wiring 1108 are stacked outside the pixel transistor 1110.
- the layout area of the wiring layer is large, there is room for improvement in that the area of the non-opening portion h is large and the aperture ratio is low.
- FIG. 3 is a schematic cross-sectional view showing a modified example of a conventional display device substrate.
- FIG. 3 only members used for explanation are denoted by reference numerals.
- the lower layer connection wiring 1107 connected to the upper layer connection wiring 1108 through the through hole 1142 is connected to the gate electrode 1104 side.
- the lower layer connection wiring 1107 and the upper layer connection wiring 1108 are stacked above the pixel transistor 1110.
- Patent Document 1 there is room for improvement in that a fine pattern cannot be formed by the upper layer wiring, and the arrangement area of the wiring layer is increased.
- the present invention has been made in view of the above-described situation, and a multilayer wiring, a semiconductor device, a display device substrate, and a display capable of reducing the layout area of a wiring layer while suppressing deterioration in characteristics due to parasitic capacitance.
- the object is to provide an apparatus.
- the present inventors have conducted various studies on multilayer wiring, semiconductor devices, display device substrates, and display devices that can reduce the layout area of the wiring layer while suppressing deterioration in characteristics due to parasitic capacitance. Attention was paid to the arrangement of the wiring layers.
- the multilayer wiring includes at least a conductor, a first insulating film, a first conductor, a second insulating film, a second conductor, a third insulating film, and a third conductor in order from the substrate side (here Each of the layers mentioned above may be a laminate composed of a plurality of layers.) In the first and second insulating films for electrically connecting the conductor and the second conductor.
- the layout area of the wiring layer I found that I can narrow down. It has also been found that an increase in parasitic capacitance can be prevented by arranging the first conductor and the second conductor without overlapping. Furthermore, for the third conductor, since the second insulating film and the third insulating film are provided between the first conductor, it is possible to sufficiently prevent an increase in parasitic capacitance with the first conductor. Thus, it has been found that the arrangement area of the wiring layer can be reduced while preventing an increase in parasitic capacitance if it is arranged on the first conductor side from the second connection hole. Based on the above findings, the inventors have conceived that the above problems can be solved brilliantly, and have reached the present invention.
- the present invention is a multilayer wiring having a structure in which a plurality of insulating films each having a connection hole and a plurality of conductor layers are alternately stacked on one main surface side of a substrate
- the multilayer wiring includes a first conductor located in the (n + 1) th (n + 1) th conductor layer from the substrate side, and an (n + 2) th (n + 2) th conductor layer from the substrate side, where n is an arbitrary natural number And electrically connected to a conductor located below the (n + 1) th conductor layer through at least the first connection hole of the (n + 1) th insulating film immediately below the (n + 2) th conductor layer.
- the second conductive material does not overlap the first conductive material, and the (n + 3) th (n + 3) conductive layer from the substrate side is located, and the main surface of the substrate is When viewed in plan, the first layer directly below the (n + 3) -th conductor layer that overlaps the first connection hole n + 2)
- a third conductor that is electrically connected to the second conductor through the second connection hole of the insulating film and that is disposed on the first conductor side from the second connection hole when the substrate main surface is viewed in plan view.
- a multilayer wiring comprising a body.
- the second conductor does not overlap the first conductor, and the third conductor is arranged on the first conductor side from the second connection hole, so that the layout area of the wiring layer can be reduced while suppressing parasitic capacitance. It can be made narrower. As a result, it is possible to further reduce the layout area of the wiring layer while suppressing deterioration in characteristics caused by parasitic capacitance such as signal delay, signal writing failure, and power consumption increase in the wiring.
- a 3rd conductor is arrange
- the (n + 2) insulating film and the (n + 1) insulating film are laminated between the third conductor and the first conductor.
- the parasitic capacitance between the body and the first conductor can be suppressed.
- the configuration of the multilayer wiring of the present invention is not particularly limited as long as such components are formed as essential, and other components may or may not be included. .
- the present invention is described in detail below.
- the material of the conductor is not particularly limited as long as it is a conductive member, and may be, for example, a metal, a semiconductor to which impurities are added, or the like. Further, the conductor may have a stacked structure of different materials. As described above, the conductor may be a wiring or a source / drain region of a MOS transistor.
- the insulating film may be a film formed of an insulator, may be a gate insulating film of a MOS transistor, or may be an interlayer insulating film provided between upper and lower wiring layers. Further, a laminated structure of different materials may be used.
- n is an integer of 1 or more.
- connection hole is a hole provided to electrically connect the upper conductor of the insulating film provided with the connection hole to the conductor immediately below.
- connection hole may be a through-hole (via hole) for electrically connecting the upper layer wiring of the interlayer insulating film provided with the connection hole to the lower layer wiring. It may be a contact hole for electrically connecting the upper wiring of the interlayer insulating film provided with the hole to the source / drain region of the lower MOS transistor.
- “upper” means the one farther from the substrate, while “lower” means the one closer to the substrate.
- the second conductor does not overlap the first conductor when the substrate main surface is viewed in plan.
- the second conductor does not overlap the first conductor when the substrate main surface is viewed in plan.
- the second connection hole overlaps the first connection hole.
- all regions of the first connection hole are the second connection holes. It is preferable that the second connection hole substantially overlaps the first connection hole when the substrate main surface is viewed in plan, and at least the first connection hole when the substrate main surface is viewed in plan view. It suffices if a part thereof overlaps the second connection hole.
- the third conductor may overlap the first conductor when the substrate main surface is viewed in plan. Thereby, the arrangement area of the wiring layer can be further reduced.
- the third conductor may not overlap the first conductor when the substrate main surface is viewed in plan. Thereby, the parasitic capacitance (fringe capacitance) between the third conductor and the first conductor can be further suppressed, and deterioration of characteristics due to the parasitic capacitance can be further suppressed.
- the multilayer wiring is located in the (n + 4) th (n + 4) conductor layer from the substrate side, and directly below the (n + 4) conductor layer from the second connection hole when the substrate main surface is viewed in plan view. It is preferable to include a fourth conductor that is electrically connected to the third conductor through a third connection hole disposed on the first conductor side of the (n + 3) insulating film. Thereby, a conductor layer can be further laminated
- the residue of the (n + 3) insulating film remains in the third connection hole due to the patterning failure of the (n + 3) insulating film, and the third conductor and the fourth conductor are left.
- a contact failure that is not electrically connected to the body may occur. From the viewpoint of suppressing the occurrence of such contact failure, it is preferable that the third connection hole does not overlap the second connection hole when the substrate main surface is viewed in plan.
- the size of the region where the third conductor and the first conductor overlap when the main surface of the substrate is viewed in plan is not particularly limited as long as it is within the range where the above effect is achieved, but in the form including the fourth conductor Is preferably overlapped to such an extent that at least a part of the third connection hole can be disposed, and more preferably overlapped to the extent that all regions of the third connection hole can be disposed when the substrate main surface is viewed in plan. preferable.
- the potentials of the first conductor and the third conductor may be different from each other. As described above, when the parasitic capacitance is generated between the first conductor and the third conductor, the multilayer wiring of the present invention can be suitably used.
- the present invention also provides a semiconductor device comprising the multilayer wiring of the present invention and a MOS transistor, wherein the first conductor is a gate electrode of a MOS transistor, and the second conductor has a first connection hole. It is a lower layer wiring electrically connected to the source / drain region of the MOS transistor located at least below the gate electrode through the gate electrode, and the third conductor is electrically connected to the lower layer wiring through the second connection hole.
- This is a semiconductor device which is a connected upper layer wiring. Since the semiconductor device of the present invention includes a multilayer wiring in which the layout area of the wiring layer is reduced while suppressing deterioration in characteristics due to parasitic capacitance, it is small in size and has few signal delays and signal writing defects in the wiring. A high-performance semiconductor device excellent in power saving and the like can be realized.
- the configuration of the semiconductor device of the present invention is not particularly limited as long as such a component is formed as an essential component, and may or may not include other components. .
- the MOS transistor may be formed in an integrated circuit.
- the integrated circuit can be reduced in size while suppressing deterioration in characteristics due to parasitic capacitance, so that the degree of integration of the integrated circuit is increased, and there are few signal delays and signal writing defects in the wiring, resulting in power savings and the like.
- An excellent high-performance semiconductor device can be realized.
- the present invention is also a display device substrate including the semiconductor device of the present invention, wherein the MOS transistor is a thin film transistor used in a pixel portion.
- the non-opening portion of the pixel portion can be narrowed and the aperture ratio can be improved while suppressing the deterioration of characteristics due to the parasitic capacitance.
- the present invention further provides a display device substrate including the semiconductor device of the present invention, wherein the MOS transistor is a thin film transistor used in a peripheral circuit portion.
- the peripheral circuit portion can be narrowed while suppressing characteristic deterioration due to parasitic capacitance, and a frame can be formed. Therefore, the display device substrate of the present invention can be suitably applied to a fully monolithic display device substrate in which peripheral circuits such as a power supply circuit and a driver necessary for driving the display device are formed on the substrate.
- the present invention is also a semiconductor device of the present invention or a display device including the display device substrate of the present invention.
- the aperture ratio can be improved while suppressing deterioration in characteristics due to parasitic capacitance, and the display device can be narrowed.
- a display device such as a liquid crystal display device or an organic electroluminescence display device including the semiconductor device of the present invention or the display device substrate of the present invention can be suitably used for a mobile device such as a mobile phone.
- the multilayer wiring, the semiconductor device, the display device substrate, and the display device of the present invention the multilayer wiring, the semiconductor device, and the display capable of reducing the layout area of the wiring layer while suppressing the deterioration of the characteristics due to the parasitic capacitance.
- An apparatus substrate and a display device can be provided.
- FIG. 1A and 1B are schematic views illustrating a display device substrate according to Embodiment 1, in which FIG. 1A is a plan view and FIG. 1B is a cross-sectional view taken along line X1-Y1 in FIG.
- the display device substrate 100 is a display device substrate applied to a display device such as a liquid crystal display device.
- the display device substrate 100 includes a semiconductor layer 102, a gate insulating film 103, a wiring layer 121, an interlayer insulating film 131, and wiring on one main surface side of the substrate 101.
- the layer 122, the interlayer insulating film 132, the wiring layer 123, the interlayer insulating film 133, and the pixel electrode 105 are stacked in this order from the substrate 101 side.
- the semiconductor layer 102 is the first first conductor layer from the substrate 101 side, and includes a channel region 102a and high-concentration impurity regions 102b and 102c.
- the gate insulating film 103 is the first insulating film first from the substrate 101 side.
- the wiring layer 121 is a second conductor layer that is second from the substrate 101 side.
- the interlayer insulating film 131 is the second insulating film second from the substrate 101 side, and has contact holes 141a and 141b.
- the wiring layer 122 is a third third conductor layer from the substrate 101 side.
- the interlayer insulating film 132 is a third insulating film third from the substrate 101 side, and has a through hole 142.
- the wiring layer 123 is the fourth fourth conductor layer from the substrate side.
- the interlayer insulating film 133 is a fourth insulating film that is the fourth from the substrate 101 side, and has a through hole 143.
- the pixel electrode 105 is located in the fifth fifth conductor layer from the substrate 101 side.
- the display device substrate 100 is a top gate type (planar type) TFT including a semiconductor layer 102, a gate insulating film 103, and a gate electrode 104 formed on the channel region 102 a by the wiring layer 121.
- a pixel transistor 110 is provided.
- the pixel transistor 110 has a single drain structure. From the viewpoint of reducing off-state current, the pixel transistor 110 may have an LDD (Liighly Doped Domain) structure or a GOLD (Gate Overlapped LDD) structure.
- a gate electrode 104 and a gate wiring 109 are formed by the wiring layer 121.
- the gate electrode 104 corresponds to the first conductor of the present invention. Further, the gate electrode 104 is electrically connected to the gate wiring 109, and part of the gate wiring 109 functions as the gate electrode 104. As described above, the gate electrode 104 and the gate wiring 109 are integrally formed by the wiring layer 121. Note that the width of the gate electrode 104 in the channel length direction is about 2 to 5 ⁇ m (preferably 3 to 4 ⁇ m). On the other hand, the width of the gate wiring 109 is about 5 to 15 ⁇ m (preferably 6 to 10 ⁇ m).
- the gate electrode 104 is a region facing the channel region 102 a included in the pixel transistor 110 in the wiring layer 121.
- the gate wiring 109 is a wiring for transmitting a scanning signal, and may be a wiring called a gate line, a scanning line, a scanning signal line, or the like.
- a lower layer connection wiring (lower layer wiring) 107 and a source wiring 106 are formed by the wiring layer 122.
- the lower layer connection wiring 107 corresponds to the second conductor of the present invention.
- the lower layer connection wiring 107 is electrically connected to the drain region (high-concentration impurity region 102b) of the pixel transistor 110 through the contact hole 141a.
- the source wiring 106 is electrically connected to the source region (high-concentration impurity region 102c) of the pixel transistor 110 through the contact hole 141b.
- An upper layer connection wiring (upper layer wiring) 108 is formed by the wiring layer 123.
- the upper layer connection wiring 108 corresponds to the third conductor of the present invention.
- the upper layer connection wiring 108 is electrically connected to the drain region (high-concentration impurity region 102 b) of the pixel transistor 110 through the through hole 142 and the lower layer connection wiring 107.
- the pixel electrode 105 corresponds to the fourth conductor of the present invention.
- the pixel electrode 105 is electrically connected to the drain region (high concentration impurity region 102 b) of the pixel transistor 110 through the through hole 143, the upper layer connection wiring 108, the through hole 142, and the lower layer connection wiring 107. That is, the lower layer connection wiring 107 and the upper layer connection wiring 108 function as the drain wiring of the pixel transistor 110.
- the contact hole 141a is a connection hole that penetrates the interlayer insulating film 131 and the gate insulating film 103 and electrically connects the lower layer connection wiring 107 to the high concentration impurity region 102b.
- the contact hole 141b is a connection hole for electrically connecting the source wiring 106 to the high concentration impurity region 102c.
- the through hole 142 is a connection hole that penetrates the interlayer insulating film 132 and electrically connects the upper layer connection wiring 108 to the lower layer connection wiring 107.
- the through hole 143 is a connection hole that penetrates the interlayer insulating film 133 and electrically connects the pixel electrode 105 to the upper layer connection wiring 108.
- the contact hole 141a corresponds to the first connection hole of the present invention
- the through hole 142 corresponds to the second connection hole of the present invention
- the through hole 143 corresponds to the first connection hole of the present invention. Corresponds to three connection holes.
- an image signal transmitted by the source wiring 106 is transmitted.
- the pixel transistor 110 (the channel region 102a and the high-concentration impurity regions 102b and 102c), the lower layer connection wiring 107, and the upper layer connection wiring 108 are stored in the pixel electrode 105 through this order.
- the image signal accumulated in the pixel electrode 105 is output from the pixel electrode 105, the lower layer connection wiring 107 and the upper layer connection wiring 108 which are electrically connected to the pixel electrode 105 until the pixel transistor 110 is turned on again. Therefore, the potential of the gate electrode 104 is usually different from the potentials of the lower layer connection wiring 107, the upper layer connection wiring 108, and the pixel electrode 105.
- the substrate 101 is prepared.
- the substrate 101 is preferably a transparent and / or insulating substrate.
- the substrate 101 is preferably a transparent and insulating substrate.
- the material of the substrate 101 is not particularly limited, and examples thereof include a glass substrate, a quartz substrate, a silicon substrate, a metal plate, a plastic substrate, a flexible organic substrate, and a substrate in which an insulating film is formed on the surface of a stainless steel plate. From this point of view, a glass substrate can be preferably used.
- an island-shaped semiconductor layer 102 with a thickness of 30 to 100 nm (preferably 40 to 50 nm) is formed. More specifically, the semiconductor layer 102 is formed by forming an amorphous semiconductor film having an amorphous structure by a known means (sputtering method, LPCVD method, plasma CVD method, etc.), and then performing a known crystallization process (laser A crystalline semiconductor film obtained by performing a crystallization method, a thermal crystallization method, a thermal crystallization method using a catalyst such as nickel) is patterned by a photolithography process into a desired shape.
- the material of the semiconductor layer 102 is not particularly limited, but preferably silicon, silicon germanium (SiGe) alloy, or the like.
- an insulating film containing silicon (eg, a SiO 2 film, a SiN film, or a SiNO film) may be formed over the substrate 101 as a base layer before the semiconductor layer 102 is formed. Accordingly, even when a glass substrate is used as the substrate 101, diffusion of impurities such as an alkali metal element from the substrate 101 can be prevented, and variation in electrical characteristics of the pixel transistor 110 can be reduced.
- a gate insulating film 103 with a thickness of 30 to 100 nm (preferably 50 to 70 nm) is formed.
- an insulating film containing silicon eg, a SiO 2 film, a SiN film, or a SiNO film
- the gate insulating film 103 may have a structure in which two or more insulating films are stacked in addition to a single-layer structure of an insulating film.
- the gate insulating film 103 is preferably an SiO 2 film.
- the layer in contact with the semiconductor layer 102 is preferably an SiO 2 film.
- the interface state at the interface between the gate insulating film 103 and the semiconductor layer 102 preferably a silicon layer
- the electrical characteristics of the pixel transistor 110 can be improved.
- an impurity element such as boron (B) is ion-implanted over the entire surface of the semiconductor layer 102 at 50 kV, 5 ⁇ 10 12 to 3 ⁇ 10 13 cm ⁇ 2 . Doping with conditions. At this time, the concentration of the impurity element in the semiconductor layer 102 is about 5 ⁇ 10 16 to 5 ⁇ 10 17 cm ⁇ 3 .
- the conductive layer is patterned into a desired shape by a photolithography process, thereby forming the wiring layer 121.
- the gate electrode 104 and the gate wiring 109 are formed.
- the material of the wiring layer 121 is preferably a refractory metal such as Ta, W, Ti, or Mo, or an alloy material or a compound material containing these refractory metals as main components.
- a nitride is preferable as a compound which has a high melting point metal as a main component.
- the wiring layer 121 may have a structure in which conductive films formed using these materials are stacked.
- the pixel transistor 110 may be a TFT having a dual gate structure or a triple gate structure.
- an impurity such as phosphorus (P) is self-aligned to the semiconductor layer 102 using the wiring layer 121 as a mask by an ion implantation method to 70 kV, 1 ⁇ 10 13 to 3 Doping (low concentration doping) is performed under conditions of ⁇ 10 13 cm -2 . At this time, the concentration of the impurity element in the semiconductor layer 102 is about 1 ⁇ 10 13 to 3 ⁇ 10 13 cm ⁇ 3 .
- the concentration of the impurity element in the semiconductor layer 102 is about 1 ⁇ 10 19 to 1 ⁇ 10 20 cm ⁇ 3 .
- a high concentration impurity region 102b that functions as a drain region and a high concentration impurity region 102c that functions as a source region are formed.
- a low concentration impurity region that functions as an LDD region is formed by masking a region to be an LDD region with a resist when doping (high concentration doping) is performed. Is done. Thereafter, the resist is removed.
- an interlayer insulating film 131 having a thickness of 0.5 to 1.5 ⁇ m (preferably 0.7 to 1.0 ⁇ m) is formed.
- the interlayer insulating film 131 is preferably an inorganic insulating film, and an insulating film containing silicon (eg, a SiO 2 film, a SiN film, or a SiNO film) formed by a plasma CVD method or a sputtering method can be used.
- the interlayer insulating film 131 may have a structure in which two or more insulating films are stacked in addition to a single-layer structure of an insulating film.
- the interlayer insulating film 131 includes a silicon nitride (SiN: H) film containing hydrogen having a thickness of 0.2 to 0.4 ⁇ m and a SiO film having a thickness of 0.4 to 0.6 ⁇ m from the wiring layer 121 side.
- SiN: H silicon nitride
- a laminated film in which two films are laminated is preferable.
- the semiconductor substrate 102 is hydrogenated and activated by heating the entire substrate 101 including the members formed through the above steps at 400 to 450 ° C. for about 0.5 to 1.0 hour. At this time, hydrogen contained in the silicon nitride film can be effectively used for hydrogenation of the semiconductor layer 102.
- contact holes 141 a and 141 b are formed in the interlayer insulating film 131 and the gate insulating film 103 by a photolithography process. As a result, a part of the high-concentration impurity regions 102b and 102c is exposed.
- the size of the contact holes 141a and 141b can be set as appropriate. However, when the planar shape of the contact holes 141a and 141b (the shape when the main surface of the substrate 101 is viewed in plan) is a substantially rectangular shape, it is usually 1 to 3 ⁇ m. It is a corner, preferably a 2 ⁇ m square.
- the conductive layer is patterned into a desired shape by a photolithography process, thereby forming the wiring layer 122.
- the source wiring 106 and the lower layer connection wiring 107 are formed, the source wiring 106 is electrically connected to the high concentration impurity region 102c through the contact hole 141b, and the lower layer connection wiring 107 is connected through the contact hole 141a. It is electrically connected to the high concentration impurity region 102b.
- the lower layer connection wiring 107 is arranged so as not to overlap the gate electrode 104 when the main surface of the substrate 101 is viewed in plan.
- the wiring layer 122 can be formed using a low melting point material. Therefore, as a material of the wiring layer 122, a low-resistance metal such as aluminum (Al), titanium (Ti), molybdenum (Mo), copper (Cu), silver (Ag), or these low-resistance metals as a main component. An alloy material or a compound material is preferable.
- the wiring layer 122 may have a structure in which conductive films formed using these materials are stacked, for example, a structure in which Ti, Al, and Ti are stacked in this order from the substrate 101 side. Such a conductive film is stacked in view of barrier properties of upper layer wiring and lower layer wiring, compatibility with etching, prevention of hillock generation, prevention of migration, and the like.
- an interlayer insulating film 132 having a thickness of 1.0 to 3.0 ⁇ m (preferably 1.5 to 2.5 ⁇ m) is formed.
- the interlayer insulating film 132 is formed by applying an insulating film material by a spin coating method or the like and then baking it as appropriate.
- a material of the interlayer insulating film 132 a resin material, a spin-on-glass material (SOG material), or the like is preferable. Thereby, the surface of the interlayer insulating film 132 can be planarized.
- the interlayer insulating film 132 is preferably a planarizing film having a planarizing action.
- the resin material examples include polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), parylene, and the like. Among them, acrylic resin and photosensitive acrylic resin are preferable.
- the SOG material is a material that can form a glass film (silica-based film) by a coating method such as a spin coating method, and more specifically, as the SOG material, a Si—O—C bond is used as a skeleton.
- the SOG material to be used and the SOG material having a Si—C bond as a skeleton are preferable.
- the resin material and the SOG material preferably have photosensitivity.
- the connection hole (specifically, the through hole 142) can be formed only by performing exposure and development processing. Can be formed.
- the interlayer insulating film 132 may have a structure in which a plurality of insulating films formed using a resin material and / or an SOG material are stacked.
- the interlayer insulating film 132 includes an insulating film (planarization film) formed using at least one of a resin material and an SOG material, and an insulating film (for example, an inorganic insulating film) formed by a CVD method, a sputtering method, or the like. A structure in which is stacked may be used.
- the planarization is performed by the CVD method or the sputtering method for the purpose of improving the adhesion of the wiring layer formed on the planarizing film and protecting the planarizing film when the wiring layer is etched.
- An insulating film (for example, an inorganic insulating film such as a SiO 2 film, a SiN film, or a SiNO film) may be formed over the film.
- the film thickness of the interlayer insulating film 132 is set to be larger than the film thickness of the interlayer insulating film 131.
- the surface of the interlayer insulating film 132 is preferably substantially flat, but may have a step of about 500 nm (preferably 200 nm) or less.
- the curvature radius of the stepped portion is preferably larger than the height of the stepped portion, thereby forming an upper wiring layer (specifically, the wiring layer 123). Therefore, it is possible to effectively suppress the generation of etching residues during etching.
- a through hole 142 is formed in the interlayer insulating film 132 by a photolithography process. As a result, a part of the lower layer connection wiring 107 is exposed. At this time, the through hole 142 is disposed so as to overlap the contact hole 141a when the main surface of the substrate 101 is viewed in plan.
- the size of the through hole 142 can be set as appropriate, but when the planar shape of the through hole 142 (the shape when the main surface of the substrate 101 is viewed in plan) is a substantially square, it is usually 2 to 5 ⁇ m square, Preferably it is 4 ⁇ m square.
- the conductive layer is patterned into a desired shape by a photolithography process, thereby forming the wiring layer 123.
- the upper layer connection wiring 108 is formed in a shape extending from the through hole 142 to the gate electrode 104 side, and the upper layer connection wiring 108 is electrically connected to the lower layer connection wiring 107 through the through hole 142.
- the upper layer connection wiring 108 is disposed so as to overlap the gate electrode 104 through the interlayer insulating film 132 and the interlayer insulating film 131 when the main surface of the substrate 101 is viewed in plan.
- the wiring layer 123 can be formed using a material having a low melting point, like the wiring layer 122. Therefore, the material of the wiring layer 123 is preferably a low-resistance metal such as Al, Ti, Mo, Cu, or Ag, or an alloy material or a compound material containing these low-resistance metals as a main component. Note that the wiring layer 123 may have a structure in which conductive films formed using these materials are stacked, for example, a structure in which Al and Mo are stacked in this order from the substrate 101 side.
- an interlayer insulating film 133 having a thickness of 1.0 to 3.0 ⁇ m (preferably 1.5 to 2.5 ⁇ m) is formed.
- the interlayer insulating film 133 is formed by appropriately baking after applying an insulating film material by spin coating or the like.
- a resin material, a spin-on-glass material (SOG material), or the like is preferable.
- the surface of the interlayer insulating film 133 can be planarized.
- the interlayer insulating film 133 is preferably a planarizing film having a planarizing action.
- the resin material and the SOG material preferably have photosensitivity from the viewpoint of easily forming the connection hole (specifically, the through hole 143).
- the interlayer insulating film 133 may have a structure in which a plurality of insulating films formed using a resin material and / or an SOG material are stacked.
- the interlayer insulating film 133 is formed by an insulating film (planarizing film) formed using at least one of a resin material and an SOG material, a CVD method, a sputtering method, or the like.
- the surface of the interlayer insulating film 133 is preferably substantially flat. However, like the interlayer insulating film 132, the surface may have a height difference of about 500 nm (preferably 200 nm) or less. The radius of curvature of the step portion is preferably larger than the height of the step.
- a through hole 143 is formed in the interlayer insulating film 133 by a photolithography process. As a result, a part of the upper layer connection wiring 108 is exposed. At this time, the through hole 143 is disposed so as to overlap the gate electrode 104.
- the size of the through-hole 143 can be set as appropriate. However, when the planar shape of the through-hole 143 (the shape when the main surface of the substrate 101 is viewed in plan) is generally square, it is usually 2 to 5 ⁇ m square, Preferably it is 4 ⁇ m square.
- a transparent conductive film having a film thickness of 80 to 120 nm (preferably 100 to 110 nm) is formed by sputtering, and then the pixel electrode 105 is formed by patterning the transparent conductive film into a desired shape by a photolithography process. Accordingly, the pixel electrode 105 is electrically connected to the upper layer connection wiring 108 through the through hole 143.
- the material of the pixel electrode 105 is preferably indium tin oxide (ITO).
- the through hole 142 overlaps the contact hole 141a, whereby the layout area of the wiring layer can be reduced. Thereby, the area of the non-opening part h becomes small and an aperture ratio can be improved. Further, when the main surface of the substrate 101 is viewed in plan, the lower layer connection wiring 107 does not overlap the gate electrode 104 and the upper layer connection wiring 108 is arranged in a shape extending from the through hole 142 to the gate electrode 104 side. The arrangement area of the wiring layer can be reduced while suppressing parasitic capacitance between conductors having different potentials.
- the display device substrate 100 includes the pixel electrode 105, a conductor layer can be further stacked while exhibiting the above effects.
- FIG. 4 is a schematic cross-sectional view showing another display device substrate according to the first embodiment. In FIG. 4, reference symbols are omitted for members that are not used in the description.
- the wiring layer is arranged so as not to overlap the gate electrode 104 located on the wiring layer 121 when the main surface of the substrate 101 is viewed in plan.
- the upper layer connection wiring 108 positioned at 123 may be arranged.
- parasitic capacitance (fringe capacitance) between the upper-layer connection wiring 108 and the gate electrode 104 can be further suppressed, so that characteristic deterioration caused by parasitic capacitance such as signal delay, signal writing failure, and power consumption increase in the wiring. It is possible to reduce the layout area of the wiring layer while further suppressing the above.
- FIG. 5A and 5B are schematic diagrams illustrating a display device substrate according to Embodiment 2, in which FIG. 5A is a plan view, and FIG. 5B is a cross-sectional view taken along line X2-Y2 in FIG.
- the display device substrate 200 is a display device substrate applied to a display device such as a liquid crystal display device.
- the display device substrate 200 includes semiconductor layers 202 n and 202 p, a gate insulating film 203, a wiring layer 221, and an interlayer insulating film 231 on one main surface side of the substrate 201.
- the interlayer insulating film 232, the wiring layer 223, the interlayer insulating film 233, and the wiring layer 224 are stacked in this order from the substrate 201 side.
- the semiconductor layers 202n and 202p are the first first conductor layers from the substrate 201 side.
- the gate insulating film 203 is the first first insulating film from the substrate 201 side.
- the wiring layer 221 is a second conductor layer that is second from the substrate 201 side.
- the interlayer insulating film 231 is the second insulating film second from the substrate 201 side, and has contact holes 241a, 241b, 241c, and 241d.
- the wiring layer 222 is a third third conductor layer from the substrate 201 side.
- the interlayer insulating film 232 is a third third insulating film from the substrate 201 side, and has through holes 242a and 242b.
- the wiring layer 223 is a third third conductor layer from the substrate 201 side.
- the interlayer insulating film 233 is a fourth insulating film fourth from the substrate 201 side, and has a through hole 243.
- the wiring layer 224 is the fourth fourth conductor layer from the substrate 201 side.
- the display device substrate 200 includes a CMOS transistor 211 composed of an N-channel thin film transistor (Nch-TFT) 210n and a P-channel thin film transistor (Pch-TFT) 210p.
- the CMOS transistor 211 constitutes an inverter circuit included in the peripheral circuit portion.
- the Nch-TFT 210n includes a semiconductor layer 202n, a gate insulating film 203, and a gate electrode 204n formed on the channel region 202na by the wiring layer 221.
- the Pch-TFT 210p includes a semiconductor layer 202p, a gate insulating film 203, and a gate electrode 204p formed on the channel region 202pa by the wiring layer 221.
- the Nch-TFT 210n and the Pch-TFT 210p are top gate type (planar type) TFTs having a single drain structure. Note that, from the viewpoint of reducing off-state current, the Nch-TFT 210n and the Pch-TFT 210p may have an LDD structure or a GOLD structure.
- the wiring layer 221 forms gate electrodes 204n and 204p and an input signal line 209.
- the gate electrodes 204n and 204p correspond to the first conductor of the present invention.
- the gate electrodes 204n and 204p are electrically connected by the input signal line 209.
- the gate electrodes 204 n and 204 p and the input signal line 209 are integrally formed by the wiring layer 221. Note that the width of the gate electrodes 204n and 204p in the channel length direction is about 1 to 10 ⁇ m.
- the width of the input signal line 209 is about 1 to 100 ⁇ m.
- the gate electrode 204n is a region in the wiring layer 221 facing the channel region 202na constituting the Nch-TFT 210n. Further, the gate electrode 204n is a region facing the channel region 202pa constituting the Pch-TFT 210p in the wiring layer 221.
- the wiring layer 222 forms lower layer connection wirings (lower layer wirings) 206n and 206p and an output signal line 251.
- the lower layer connection wirings 206n and 206p correspond to the second conductor of the present invention.
- Lower layer connection wiring 206n is electrically connected to high concentration impurity region 202nc through contact hole 241a.
- the lower layer connection wiring 206p is electrically connected to the high concentration impurity region 202pc through the contact hole 241d.
- the wiring layer 223 forms a low voltage power supply wiring (upper layer wiring) Vss and an upper layer connection wiring (upper layer wiring) 208.
- the low voltage power supply wiring Vss and the upper layer connection wiring 208 correspond to the third conductor of the present invention.
- the low voltage power supply wiring Vss is electrically connected to the source region (high concentration impurity region 220nc) of the Nch-TFT 210n through the through hole 242a, the lower layer connection wiring 206n, and the contact hole 241a.
- the width of the low voltage power supply wiring Vss is about 5 to 200 ⁇ m (preferably 8 to 100 ⁇ m).
- the upper layer connection wiring 208 is electrically connected to the source region (high-concentration impurity region 220pc) of the Pch-TFT 210p through the through hole 242b, the lower layer connection wiring 206p, and the contact hole 241d.
- the wiring layer 224 forms a high voltage power supply wiring Vdd.
- the high voltage power supply wiring Vdd corresponds to the fourth conductor of the present invention.
- the high voltage power supply wiring Vdd is electrically connected to the source region (high concentration impurity region 202pc) of the Pch-TFT 210p through the through hole 243, the upper layer connection wiring 208, the through hole 242b, the lower layer connection wiring 206p, and the contact hole 241d. Connected.
- the width of the high voltage power supply wiring Vdd is about 5 to 200 ⁇ m (preferably 8 to 100 ⁇ m).
- the drain region (high-concentration impurity region 202nb) of the Nch-TFT 210n is electrically connected to the output signal line 251 through the contact hole 241b.
- the drain region (high concentration impurity region 202pb) of the Pch-TFT 210p is electrically connected to the output signal line 251 through the contact hole 241c. In this manner, the drain region (high concentration impurity region 202nb) of the Nch-TFT 210n is electrically connected to the drain region (high concentration impurity region 202pb) of the Pch-TFT 210p via the output signal line 251.
- the contact hole 241a is a connection hole that penetrates the interlayer insulating film 231 and the gate insulating film 203 and electrically connects the lower layer connection wiring 206n to the high concentration impurity region 202nc.
- the contact holes 241b and 241c pass through the interlayer insulating film 231 and the gate insulating film 203, and are connection holes for electrically connecting the high-concentration impurity region 202nb to the high-concentration impurity region 202pb through the output signal line 251. It is.
- the contact hole 241d is a connection hole that penetrates the interlayer insulating film 231 and the gate insulating film 203 and electrically connects the lower layer connection wiring 206p to the high concentration impurity region 202pc.
- the through hole 242a is a connection hole that penetrates the interlayer insulating film 232 and electrically connects the low voltage power supply wiring Vss to the lower layer connection wiring 206n.
- the through hole 242b is a connection hole that penetrates the interlayer insulating film 232 and electrically connects the upper layer connection wiring 208 to the lower layer connection wiring 206p.
- the through hole 243 is a connection hole that penetrates the interlayer insulating film 233 and electrically connects the high voltage power supply wiring Vdd to the upper layer connection wiring 208.
- the contact holes 241a and 241d correspond to the first connection holes of the present invention
- the through holes 242a and 242b correspond to the second connection holes of the present invention
- the through holes 243 This corresponds to the third connection hole of the present invention.
- one of the Nch-TFT 210n and the Pch-TFT 210p is turned on by a signal input to the input signal line 209.
- signals transmitted from the low voltage power supply wiring Vss are transferred to the lower layer connection wiring 206n, the Nch-TFT 210n (the channel region 202na and the high concentration impurity regions 202nb and 202nc), the output signal line 251, Are transmitted in this order. Therefore, normally, the potential of the gate electrode 204n electrically connected to the input signal line 209 is different from the potential of the low voltage power supply wiring Vss, the lower layer connection wiring 206n, and the output signal line 251.
- a substrate 201 similar to the substrate 101 of Embodiment 1 is prepared.
- a base layer may be formed as in the first embodiment.
- island-shaped semiconductor layers 202n and 202p with a thickness of 30 to 100 nm (preferably 40 to 50 nm) are formed. More specifically, the semiconductor layers 202n and 202p are formed by forming an amorphous semiconductor film having an amorphous structure by a known means (sputtering method, LPCVD method, plasma CVD method, etc.), and then performing a known crystallization process. It is formed by patterning a crystalline semiconductor film obtained by performing (a laser crystallization method, a thermal crystallization method, a thermal crystallization method using a catalyst such as nickel) into a desired shape by a photolithography process.
- the material of the semiconductor layers 202n and 202p is not particularly limited, but is preferably silicon, a silicon germanium (SiGe) alloy, or the like.
- an impurity element such as boron (B) is doped on the entire surface of the semiconductor layers 202n and 202p by ion implantation under conditions of 50 kV and 5 ⁇ 10 12 to 3 ⁇ 10 13 cm ⁇ 2 .
- the concentration of the impurity element in the semiconductor layers 202n and 202p is about 5 ⁇ 10 16 to 5 ⁇ 10 17 cm ⁇ 3 .
- an impurity element such as phosphorus (P) is added to the semiconductor layer 202n in a state where the channel region 202na of the semiconductor layer 202n and the semiconductor layer 202p are masked with a resist.
- Doping low concentration doping
- the concentration of the impurity element in the semiconductor layer 202n is about 1 ⁇ 10 17 to 1 ⁇ 10 18 cm ⁇ 3 .
- the resist is removed.
- a wiring layer 221 having a thickness of 200 to 600 nm (preferably 300 to 400 nm) is formed.
- gate electrodes 204n and 204p and an input signal line 209 are formed.
- impurities such as phosphorus (P) in Nch and boron (B) in Pch are ion-implanted in a self-aligned manner to the semiconductor layers 202n and 202p by ion implantation at 50 kV, 5 ⁇ 10 15 to 1 ⁇ 10.
- Doping high concentration doping
- the concentration of the impurity element in the semiconductor layers 202n and 202p is about 1 ⁇ 10 19 to 1 ⁇ 10 20 cm ⁇ 3 .
- high-concentration impurity regions 202nb, 202nc, 202pb, and 202pc functioning as a source region or a drain region are formed.
- the semiconductor layer 202n before performing high-concentration doping, the semiconductor layer 202n is doped with an impurity such as phosphorus (P) at a low concentration using the wiring layer 221 as a mask, and a low function that functions as an LDD region
- the concentration impurity region is formed, the low concentration impurity region is masked with a resist. Thereafter, the resist is removed after performing high concentration doping.
- an interlayer insulating film 231 having a film thickness of 0.5 to 1.5 ⁇ m (preferably 0.7 to 1.0 ⁇ m) and hydrogenation and activation of the semiconductor layers 202n and 202p are performed. And do.
- the interlayer insulating film 231 similarly to the interlayer insulating film 131 of the first embodiment, a stacked film in which a silicon nitride (SiN: H) film containing hydrogen and a SiO 2 film are stacked from the wiring layer 221 side is suitable. .
- contact holes 241a, 241b, 241c, and 241d are formed in the interlayer insulating film 231 and the gate insulating film 203 by a photolithography process. As a result, the source and drain regions of the Nch-TFT 210n and Pch-TFT 210p are partially exposed.
- a wiring layer 222 having a thickness of 400 to 1000 nm (preferably 600 to 800 nm) is formed.
- lower layer connection wirings 206n and 206p and an output signal line 251 are formed.
- the lower layer connection wiring 206n is electrically connected to the source region (high concentration impurity region 202nb) of the Nch-TFT 210n through the contact hole 241a.
- the lower layer connection wiring 206n is arranged so as not to overlap the gate electrode 204n when the main surface of the substrate 201 is viewed in plan.
- the lower layer connection wiring 206p is electrically connected to the source region (high concentration impurity region pc) of the Pch-TFT 210p through the contact hole 241d. At this time, the lower layer connection wiring 206p is arranged so as not to overlap the gate electrode 204p when the main surface of the substrate 201 is viewed in plan. Further, the output signal line 251 is electrically connected to the drain region (high-concentration impurity region 202nb) of the Nch-TFT 210n through the contact hole 241b, and the output signal line 251 is connected to the drain of the Pch-TFT 210p through the contact hole 241c.
- the wiring layer 222 can be formed using a low melting point material. Therefore, as the material of the wiring layer 222, as in the first embodiment, a low-resistance metal such as Al, Ti, Mo, Cu, or Ag, or an alloy material or a compound material mainly composed of these low-resistance metals is used. preferable. Note that the wiring layer 222 may have a structure in which conductive films formed using these materials are stacked.
- an interlayer insulating film 232 having a film thickness of 1.0 to 3.0 ⁇ m (preferably 1.5 to 2.5 ⁇ m) is formed.
- the interlayer insulating film 232 is a planarizing film having a planarizing action similar to the interlayer insulating film 132 of the first embodiment.
- the film thickness of the interlayer insulating film 232 is set to be larger than the film thickness of the interlayer insulating film 231.
- through holes 242a and 242b are formed in the interlayer insulating film 232 by a photolithography process. As a result, a part of the lower layer connection wirings 206n and 206p is exposed.
- the through holes 242a are arranged so that the through holes 242a and 242b overlap the contact holes 241a and 241d, respectively, when the main surface of the substrate 201 is viewed in plan.
- a wiring layer 223 having a thickness of 400 to 1000 nm (preferably 600 to 800 nm) is formed.
- the low voltage power supply wiring Vss and the upper layer connection wiring 208 are formed.
- the low voltage power supply wiring Vss is electrically connected to the lower layer connection wiring 206n through the through hole 242a
- the upper layer connection wiring 208 is electrically connected to the lower layer connection wiring 206p through the through hole 242b.
- the low voltage power supply wiring Vss is arranged in a shape extending from the through hole 242b to the gate electrode 104 side.
- the wiring layer 223 can be formed using a low melting point material, similarly to the wiring layer 222.
- the material of the wiring layer 223 is preferably a low-resistance metal such as Al, Ti, Mo, Cu, or Ag, or an alloy material or a compound material mainly composed of these low-resistance metals, as in the first embodiment.
- the wiring layer 223 may have a structure in which conductive films formed using these materials are stacked.
- an interlayer insulating film 233 with a film thickness of 1.0 to 3.0 ⁇ m (preferably 1.5 to 2.0 ⁇ m) is formed.
- the interlayer insulating film 233 is a planarizing film having the same planarizing action as the interlayer insulating film 133 of the first embodiment. Further, the film thickness of the interlayer insulating film 233 is set to be larger than the film thickness of the interlayer insulating film 231.
- a through hole 243 is formed in the interlayer insulating film 233 by a photolithography process. As a result, a part of the upper layer connection wiring 208 is exposed. At this time, the through hole 243 is disposed so as to overlap the gate electrode 204p when the main surface of the substrate 201 is viewed in plan.
- a conductive film having a thickness of 400 to 1000 nm (preferably 600 to 800 nm) is formed by sputtering, and then the conductive layer is patterned into a desired shape by a photolithography process, thereby forming the wiring layer 224.
- the high voltage power supply wiring Vdd is formed.
- the high voltage power supply wiring Vdd is electrically connected to the upper layer connection wiring 208 through the through hole 243.
- the wiring layer 224 can be formed using a low melting point material, similarly to the wiring layer 222. Therefore, the material of the wiring layer 224 is preferably a low resistance metal such as Al, Ti, Mo, Cu, or Ag, or an alloy material or a compound material containing these low resistance metals as a main component. Note that the wiring layer 224 may have a structure in which conductive films formed using these materials are stacked.
- the through holes 242a and 242b overlap the contact holes 241a and 241d, respectively, thereby reducing the layout area of the wiring layer. be able to. Thereby, the area of a peripheral circuit part becomes small and a narrow frame is attained. Further, when the main surface of the substrate 201 is viewed in plan, the lower layer connection wirings 206n and 206p do not overlap the gate electrodes 204n and 204p, respectively, and the low voltage power supply wiring Vss extends from the through hole 242a to the gate electrode 204n side.
- the upper layer connection wiring 208 is disposed on the gate electrode 204p side from the through hole 242b, so that the layout area of the wiring layer can be reduced while suppressing parasitic capacitance between conductors having different potentials. As a result, it is possible to further reduce the layout area of the wiring layer while suppressing deterioration in characteristics caused by parasitic capacitance such as signal delay, signal writing failure, and power consumption increase in the wiring. Thereby, the area of a peripheral circuit part becomes smaller and it can advance a narrower frame. Further, when the main surface of the substrate 201 is viewed in plan, the high voltage power supply wiring Vss and the upper layer connection wiring 208 overlap the gate electrodes 204n and 204p, respectively, so that the layout area of the wiring layer can be further reduced.
- the display device substrate 200 of the present embodiment can be suitably applied to a full monolithic display device substrate.
- the display device substrate 200 includes the high-voltage power supply wiring Vdd, so that a wiring layer can be further laminated while exhibiting the above effects.
- the present invention has been described using the pixel portion and the peripheral circuit portion of the display device substrate.
- the present invention is not limited to this, for example, a MOS transistor is formed in an integrated circuit.
- the Nch-TFT 210n and the Pch-TFT 210p are MOS transistors included in the integrated circuit, and the other members are configured similarly to the display device substrate 200.
- the integrated circuit can be reduced in size while suppressing deterioration in characteristics due to parasitic capacitance, so that the degree of integration of the integrated circuit can be increased.
- FIG. 1 is a schematic view showing a display device substrate of Embodiment 1, wherein (a) is a plan view and (b) is a cross-sectional view taken along line X1-Y1 in (a). It is a cross-sectional schematic diagram which shows the conventional board
- FIG. FIG. 3 is a schematic diagram illustrating a display device substrate according to Embodiment 2, wherein (a) is a plan view and (b) is a cross-sectional view taken along line X2-Y2 in (a).
- 100, 200, 1100a, 1100b Display device substrates 101, 201, 1101: Substrates 102, 202n, 202p, 1102: Semiconductor layers 102a, 202na, 202pa, 1102a: Channel regions 102b, 102c, 202nb, 202nc, 202pb, 202pc 1102b, 1102c: High-concentration impurity regions 103, 203, 1103: Gate insulating films 104, 204n, 204p, 1104: Gate electrodes 105, 205, 1105: Pixel electrodes 106, 1106: Source wirings 107, 206n, 206p, 1107: Lower layer connection wiring (lower layer wiring) 108, 208, 1108: Upper layer connection wiring (upper layer wiring) 109: Gate wiring 209: Input signal line 110, 1110: Pixel transistor 210n: N-channel type thin film transistor (Nch-TFT) 210p: P-channel type thin film transistor (Pch-
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Nonlinear Science (AREA)
- Geometry (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
以下、本発明を詳述する。
図1は、実施形態1の表示装置用基板を示す模式図であり、(a)は平面図であり、(b)は(a)中のX1-Y1線における断面図である。
まず、基板101を準備する。基板101は、透明及び/又は絶縁性の基板であることが好ましく、表示装置用基板100を透過型液晶表示装置に用いる場合には、透明かつ絶縁性の基板であることが好ましい。基板101の材質としては特に限定されず、ガラス基板、石英基板、シリコン基板、金属板、プラスチック基板、フレキシブル有機基板及びステンレス板の表面に絶縁膜が形成された基板等が挙げられるが、コスト等の観点からは、ガラス基板を好適に用いることができる。
図5は、実施形態2の表示装置用基板を示す模式図であり、(a)は平面図であり、(b)は(a)中のX2-Y2線における断面図である。
まず、実施形態1の基板101と同様の基板201を準備する。ここで、実施形態1と同様に、下地層を形成してもよい。
101、201、1101:基板
102、202n、202p、1102:半導体層
102a、202na、202pa、1102a:チャネル領域
102b、102c、202nb、202nc、202pb、202pc、1102b、1102c:高濃度不純物領域
103、203、1103:ゲート絶縁膜
104、204n、204p、1104:ゲート電極
105、205、1105:画素電極
106、1106:ソース配線
107、206n、206p、1107:下層接続配線(下層配線)
108、208、1108:上層接続配線(上層配線)
109:ゲート配線
209:入力信号線
110、1110:画素トランジスタ
210n:Nチャネル型の薄膜トランジスタ(Nch-TFT)
210p:Pチャネル型の薄膜トランジスタ(Pch-TFT)
211:CMOSトランジスタ
121、122、123、221、222、223、224、1121、1122、1123:配線層
131、132、133、231、232、233、1131、1132、1133:層間絶縁膜
141a、141b、241a、241b、241c、241d、1141:コンタクトホール
142、143、242a、242b、243、1142、1143:スルーホール
251:出力信号線
h:非開口部
Vdd:高電圧電源配線
Vss:低電圧電源配線(上層配線)
Claims (11)
- 基板の一方の主面側に、接続孔をそれぞれ有する複数層の絶縁膜と、複数層の導電体層とが交互に積層された構造を有する多層配線であって、
該多層配線は、nを任意の自然数として、
基板側から(n+1)番目の第(n+1)導電体層に位置する第一導電体と、
基板側から(n+2)番目の第(n+2)導電体層に位置し、かつ第(n+2)導電体層の直下の第(n+1)絶縁膜の第一接続孔を少なくとも介して第(n+1)導電体層よりも下層に位置する導電体に電気的に接続されるとともに、基板主面を平面視したときに第一導電体に重ならない第二導電体と、
基板側から(n+3)番目の第(n+3)導電体層に位置し、かつ基板主面を平面視したときに第一接続孔に重なる第(n+3)導電体層の直下の第(n+2)絶縁膜の第二接続孔を介して第二導電体に電気的に接続されるとともに、基板主面を平面視したときに第二接続孔から第一導電体側に配置された第三導電体とを備えることを特徴とする多層配線。 - 前記第三導電体は、基板主面を平面視したときに第一導電体に重なることを特徴とする請求項1記載の多層配線。
- 前記第三導電体は、基板主面を平面視したときに第一導電体に重ならないことを特徴とする請求項1記載の多層配線。
- 前記多層配線は、基板側から(n+4)番目の第(n+4)導電体層に位置し、かつ基板主面を平面視したときに第二接続孔よりも第(n+4)導電体層の直下の第(n+3)絶縁膜の第一導電体側に配置された第三接続孔を介して第三導電体に電気的に接続される第四導電体を備えることを特徴とする請求項1~3のいずれかに記載の多層配線。
- 前記多層配線は、第一導電体及び第三導電体の電位が互いに異なることを特徴とする請求項1~4のいずれかに記載の多層配線。
- 請求項1~5のいずれかに記載の多層配線と、MOSトランジスタとを備える半導体装置であって、
前記第一導電体は、MOSトランジスタのゲート電極であり、
前記第二導電体は、第一接続孔を少なくとも介してゲート電極よりも下層に位置するMOSトランジスタのソース・ドレイン領域に電気的に接続された下層配線であり、
前記第三導電体は、第二接続孔を介して下層配線に電気的に接続された上層配線であることを特徴とする半導体装置。 - 請求項6記載の半導体装置を備える表示装置用基板であって、
前記MOSトランジスタは、画素部に用いられる薄膜トランジスタであることを特徴とする表示装置用基板。 - 請求項6記載の半導体装置を備える表示装置用基板であって、
前記MOSトランジスタは、周辺回路部に用いられる薄膜トランジスタであることを特徴とする表示装置用基板。 - 請求項7又は8記載の表示装置用基板を含んで構成されることを特徴とする表示装置。
- 前記MOSトランジスタは、集積回路に形成されることを特徴とする請求項6記載の半導体装置。
- 請求項10記載の半導体装置を含んで構成されることを特徴とする表示装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/988,588 US8446010B2 (en) | 2008-04-25 | 2008-12-12 | Multilayer wiring, semiconductor device, substrate for display device, and display device |
CN2008801282440A CN101978480B (zh) | 2008-04-25 | 2008-12-12 | 多层配线、半导体装置、显示装置用基板和显示装置 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008-116177 | 2008-04-25 | ||
JP2008116177 | 2008-04-25 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2009130822A1 true WO2009130822A1 (ja) | 2009-10-29 |
Family
ID=41216567
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2008/072665 WO2009130822A1 (ja) | 2008-04-25 | 2008-12-12 | 多層配線、半導体装置、表示装置用基板及び表示装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US8446010B2 (ja) |
CN (1) | CN101978480B (ja) |
WO (1) | WO2009130822A1 (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102714138A (zh) * | 2010-01-22 | 2012-10-03 | 夏普株式会社 | 半导体装置及其制造方法 |
JP2013003200A (ja) * | 2011-06-13 | 2013-01-07 | Japan Display Central Co Ltd | 液晶表示装置及びその製造方法 |
US20160013264A1 (en) * | 2013-03-06 | 2016-01-14 | Seiko Epson Corporation | Electro-optical device, electronic apparatus, and drive circuit |
CN108269810A (zh) * | 2016-12-30 | 2018-07-10 | 三星显示有限公司 | 导电图案和具有其的显示装置 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5352333B2 (ja) * | 2009-04-23 | 2013-11-27 | 株式会社ジャパンディスプレイ | アクティブマトリクス型表示装置 |
JP2012253125A (ja) * | 2011-06-01 | 2012-12-20 | Sumitomo Electric Ind Ltd | 半導体装置及び配線基板 |
TWI626497B (zh) | 2017-02-15 | 2018-06-11 | 友達光電股份有限公司 | 主動元件陣列基板及應用其之顯示裝置 |
US11107845B2 (en) * | 2017-03-29 | 2021-08-31 | Sharp Kabushiki Kaisha | TFT substrate, TFT substrate production method, and display device |
CN115830996A (zh) * | 2019-11-12 | 2023-03-21 | 群创光电股份有限公司 | 显示装置 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH118196A (ja) * | 1997-06-13 | 1999-01-12 | Semiconductor Energy Lab Co Ltd | 半導体薄膜および半導体装置 |
JP2000002890A (ja) * | 1998-06-17 | 2000-01-07 | Semiconductor Energy Lab Co Ltd | 反射型半導体表示装置 |
JP2002110988A (ja) * | 2000-09-26 | 2002-04-12 | Toshiba Corp | 半導体装置 |
JP2006332603A (ja) * | 2005-04-28 | 2006-12-07 | Semiconductor Energy Lab Co Ltd | 薄膜トランジスタの作製方法及び薄膜トランジスタ |
JP2007005583A (ja) * | 2005-06-24 | 2007-01-11 | Semiconductor Energy Lab Co Ltd | 半導体装置及びその作製方法 |
JP2007043118A (ja) * | 2005-07-08 | 2007-02-15 | Semiconductor Energy Lab Co Ltd | 配線基板の作製方法及び半導体装置の作製方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6861670B1 (en) * | 1999-04-01 | 2005-03-01 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having multi-layer wiring |
JP2005072573A (ja) | 2003-08-05 | 2005-03-17 | Semiconductor Energy Lab Co Ltd | 配線基板及びその作製方法、並びに半導体装置及びその作製方法 |
US7410839B2 (en) * | 2005-04-28 | 2008-08-12 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistor and manufacturing method thereof |
US7685706B2 (en) * | 2005-07-08 | 2010-03-30 | Semiconductor Energy Laboratory Co., Ltd | Method of manufacturing a semiconductor device |
KR101198127B1 (ko) * | 2005-09-30 | 2012-11-12 | 엘지디스플레이 주식회사 | 액정표시장치와 그 제조방법 |
-
2008
- 2008-12-12 CN CN2008801282440A patent/CN101978480B/zh not_active Expired - Fee Related
- 2008-12-12 WO PCT/JP2008/072665 patent/WO2009130822A1/ja active Application Filing
- 2008-12-12 US US12/988,588 patent/US8446010B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH118196A (ja) * | 1997-06-13 | 1999-01-12 | Semiconductor Energy Lab Co Ltd | 半導体薄膜および半導体装置 |
JP2000002890A (ja) * | 1998-06-17 | 2000-01-07 | Semiconductor Energy Lab Co Ltd | 反射型半導体表示装置 |
JP2002110988A (ja) * | 2000-09-26 | 2002-04-12 | Toshiba Corp | 半導体装置 |
JP2006332603A (ja) * | 2005-04-28 | 2006-12-07 | Semiconductor Energy Lab Co Ltd | 薄膜トランジスタの作製方法及び薄膜トランジスタ |
JP2007005583A (ja) * | 2005-06-24 | 2007-01-11 | Semiconductor Energy Lab Co Ltd | 半導体装置及びその作製方法 |
JP2007043118A (ja) * | 2005-07-08 | 2007-02-15 | Semiconductor Energy Lab Co Ltd | 配線基板の作製方法及び半導体装置の作製方法 |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102714138A (zh) * | 2010-01-22 | 2012-10-03 | 夏普株式会社 | 半导体装置及其制造方法 |
JP2013003200A (ja) * | 2011-06-13 | 2013-01-07 | Japan Display Central Co Ltd | 液晶表示装置及びその製造方法 |
US8885129B2 (en) | 2011-06-13 | 2014-11-11 | Japan Display Inc. | Liquid crystal display device and method of manufacturing the same |
US9395587B2 (en) | 2011-06-13 | 2016-07-19 | Japan Display Inc. | Liquid crystal display device and method of manufacturing the same |
US9921437B2 (en) | 2011-06-13 | 2018-03-20 | Japan Display Inc. | Display device |
US20160013264A1 (en) * | 2013-03-06 | 2016-01-14 | Seiko Epson Corporation | Electro-optical device, electronic apparatus, and drive circuit |
CN108269810A (zh) * | 2016-12-30 | 2018-07-10 | 三星显示有限公司 | 导电图案和具有其的显示装置 |
JP2018112737A (ja) * | 2016-12-30 | 2018-07-19 | 三星ディスプレイ株式會社Samsung Display Co.,Ltd. | 導電パターン及びこれを備える表示装置 |
JP7181687B2 (ja) | 2016-12-30 | 2022-12-01 | 三星ディスプレイ株式會社 | 導電パターン及びこれを備える表示装置 |
CN108269810B (zh) * | 2016-12-30 | 2023-10-03 | 三星显示有限公司 | 导电图案和具有其的显示装置 |
Also Published As
Publication number | Publication date |
---|---|
CN101978480B (zh) | 2012-05-02 |
US8446010B2 (en) | 2013-05-21 |
US20110037072A1 (en) | 2011-02-17 |
CN101978480A (zh) | 2011-02-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2009130822A1 (ja) | 多層配線、半導体装置、表示装置用基板及び表示装置 | |
US8421944B2 (en) | Display device substrate, display device, and wiring substrate | |
JP5600762B2 (ja) | 半導体装置 | |
US10564494B2 (en) | Array substrate circuit, array substrate, and display device | |
US8148730B2 (en) | Semiconductor device and method for manufacturing semiconductor device | |
US8049255B2 (en) | Display device and method of manufacturing the same | |
JP4485078B2 (ja) | 半導体装置の作製方法 | |
WO2015052991A1 (ja) | 半導体装置およびその製造方法 | |
JP5409024B2 (ja) | 表示装置 | |
WO2013137045A1 (ja) | 半導体装置およびその製造方法 | |
US8865533B2 (en) | Thin film transistor array panel and method of manufacturing the same | |
US20090224257A1 (en) | Thin film transistor panel and manufacturing method of the same | |
JP5284538B2 (ja) | 電子基板の製造方法、液晶表示装置の製造方法、電子基板、及び、液晶表示装置 | |
WO2013005604A1 (ja) | 半導体装置およびその製造方法 | |
US10254612B2 (en) | Display panel and method of fabricating the same | |
JP2006072355A (ja) | 薄膜トランジスタ表示板及びその製造方法 | |
US20100117155A1 (en) | Semiconductor device and production method thereof | |
JP2009224589A (ja) | 表示装置およびその製造方法 | |
WO2011151955A1 (ja) | 半導体素子、薄膜トランジスタ基板及び表示装置 | |
JP4531923B2 (ja) | 半導体装置 | |
US7939829B2 (en) | Semiconductor device and display device | |
US8946004B2 (en) | Contact portion of wire and manufacturing method thereof | |
JP2019078862A (ja) | アクティブマトリクス基板およびその製造方法 | |
KR20060128271A (ko) | 액정표시장치용 기판 및 그 제조방법 | |
JP6403478B2 (ja) | 液晶表示装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 200880128244.0 Country of ref document: CN |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 08874055 Country of ref document: EP Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 12988588 Country of ref document: US |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 08874055 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: JP |