WO2009123090A1 - Circuit intégré reconfigurable - Google Patents

Circuit intégré reconfigurable Download PDF

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Publication number
WO2009123090A1
WO2009123090A1 PCT/JP2009/056451 JP2009056451W WO2009123090A1 WO 2009123090 A1 WO2009123090 A1 WO 2009123090A1 JP 2009056451 W JP2009056451 W JP 2009056451W WO 2009123090 A1 WO2009123090 A1 WO 2009123090A1
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WIPO (PCT)
Prior art keywords
circuit
reconfigurable integrated
integrated circuit
signal
wiring
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Application number
PCT/JP2009/056451
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English (en)
Japanese (ja)
Inventor
崇 河並
帆平 小池
Original Assignee
独立行政法人産業技術総合研究所
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Priority to JP2010505888A priority Critical patent/JP5046142B2/ja
Publication of WO2009123090A1 publication Critical patent/WO2009123090A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17784—Structural details for adapting physical parameters for supply voltage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17792—Structural details for adapting physical parameters for operating speed

Definitions

  • the present invention provides a reconfiguration that achieves both high speed and low power consumption by appropriately controlling the operating characteristics of the field effect transistors that constitute the circuit during circuit operation when the reconfigurable circuit is manufactured by an integrated circuit. It relates to possible integrated circuits.
  • operation mode data threshold voltage level
  • Analyzing design data net list
  • Patent Document 2 discloses a prior control method for optimizing the body potential of a subsequent circuit by a previous circuit.
  • a circuit that is divided into a pre-stage circuit and a post-stage circuit at the time of designing a semiconductor integrated circuit by changing the body potential of the post-stage circuit according to the output signal of the pre-stage circuit, for example, when the output signal of the pre-stage circuit is at a low level,
  • the post-stage circuit is set to the low power consumption mode and the output signal of the pre-stage circuit is at the high level, the post-stage circuit is controlled to the high speed mode.
  • the body voltage can be optimized.
  • Non-Patent Document 1 As a technique for reducing power consumption in a microprocessor, as proposed in Non-Patent Document 1, for example, in terms of operating speed, based on a design policy that only a typical signal input needs to satisfy timing constraints. A critical subcircuit designed to guarantee correct values for typical signal inputs (but not for all signal inputs), and to ensure that the results are correct for all signal inputs Two error detection units are prepared, and during typical signal input, the power voltage of the main unit is lowered to reduce power consumption, and there is an atypical signal input. If a violation occurs, the process is recovered using the result of the error detection unit. This achieves low power consumption while ensuring normal operation. JP 2007-082017 A JP 2007-201236 A Daniel Ernst etal. “Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation” ACM / IEEE International Symposium on Microarchitecture (MICRO), pp.7-18, November, 2003.
  • MICRO Microarchitecture
  • the operation mode data is static (does not change during circuit operation) for each circuit configuration information.
  • wasteful power is consumed when a partial circuit whose threshold voltage is set low is inactive.
  • the present invention has been made to solve such problems, and the object of the present invention is to provide an operational characteristic of a field effect transistor constituting a circuit when a reconfigurable circuit is manufactured by an integrated circuit. It is an object of the present invention to provide a reconfigurable integrated circuit that achieves both high speed and low power consumption by adopting a configuration that allows appropriate control during circuit operation.
  • a reconfigurable integrated circuit includes a plurality of circuit configuration circuits constituting a circuit that calculates a logical function based on circuit configuration information, and a circuit that connects between the circuit configuration circuits.
  • a wiring circuit; a signal state detection circuit for detecting a change in an internal signal of the circuit configuration circuit or the circuit wiring circuit; and a state change signal detected by the signal state detection circuit in the circuit configuration circuit or the circuit wiring circuit A state change wiring circuit for transmission and an operation speed setting circuit for setting operation characteristics of the field effect transistor based on the state change signal for each of the circuit configuration circuit or the partial circuit of the circuit wiring circuit are provided.
  • the circuit configuration circuit or the circuit wiring circuit is a field programmable gate array (FPGA) including an operation speed setting circuit that sets operation characteristics of a transistor for each partial circuit.
  • the signal state detection circuit is generated by a circuit configuration circuit.
  • the signal state detection circuit is mounted in advance in the reconfigurable integrated circuit, and activation of the signal state detection circuit is controlled by a program.
  • the generation position of the signal state detection circuit or where the signal state detection circuit is activated is set by the setting software of the reconfigurable integrated circuit.
  • the generation position of the signal state detection circuit or where to activate the signal state detection circuit is set based on a logic function designed by the user.
  • the operating characteristics of the field effect transistor are configured to be controlled by changing the threshold voltage of the field effect transistor.
  • the operational characteristics of the field effect transistor are configured to be controlled by the power supply voltage.
  • the state change wiring circuit may be configured to be provided independently of the circuit wiring circuit, or the state change wiring circuit may be configured using the circuit wiring circuit.
  • the state change signal output from the signal state detection circuit is a pulse signal
  • the operation speed setting circuit has an operation mode storage device that can hold one or more operation characteristics of the transistor.
  • the operation mode storage device is configured to determine the operation speed and power consumption of the partial circuit according to the contents of the operation mode storage device.
  • the output of the operation mode storage device of the operation speed power consumption setting circuit is composed of one or more flip-flop circuits that are switched by a pulse-like state change signal, and the output of the operation mode storage device of the operation speed power consumption setting circuit. Is switched by a pulse-like state change signal, and is configured to switch operation modes stored in two or more random access memories or two or more shift registers by pulses.
  • the reconfigurable integrated circuit of the present invention in a reconfigurable integrated circuit in which the operation characteristics of the transistor can be adjusted in a programmable manner, an approach that focuses on typical signal input is applied to the signal input during circuit operation.
  • the operating speed and power consumption can be adjusted dynamically, and the transistor operating characteristics based on the operating speed and power consumption, which were always static in the conventional method (does not change during circuit operation), are It becomes possible to set appropriately.
  • the reconfigurable integrated circuit can be further reduced in power consumption or speed.
  • CLB reconfigurable logic circuit block
  • NULL general empty circuit block
  • SBLE basic logic circuit element
  • SB general switch block
  • FIG. 1 is a diagram for explaining the configuration of a reconfigurable integrated circuit according to an embodiment of the present invention.
  • 10 is a reconfigurable integrated circuit
  • 11 is a region where a logic function is realized by circuit configuration information
  • 12 is a signal state detection circuit
  • 13 is a state change signal.
  • Reference numeral 14 denotes a driven control area in which the operation speed is dynamically controlled. The driven control area 14 is controlled not only for the operation speed but also for the power consumption.
  • FIG. 2 is a diagram for explaining an example of a setting method for configuring a circuit in the reconfigurable integrated circuit of the present invention.
  • An embodiment of the configuration of the reconfigurable integrated circuit of the present invention will be described with reference to FIGS.
  • the circuit designer uses a CAD (Computer Aided Design) system to create a user design, puts critical paths (routes with no timing margin for the route including the longest route) into high-speed mode, and consumes non-critical paths with low power consumption.
  • the circuit configuration information A is generated by automatically setting the mode.
  • the circuit configuration information A is equivalent to that generated by a known optimization method as described in Patent Document 1.
  • the circuit configuration information A indicates static operation speed and power consumption.
  • the optimized circuit configuration information is obtained.
  • the dynamic control is further determined for the circuit configuration information A by two processing flows, that is, whether dynamic control is automatically determined or determined by circuit designer setting information.
  • Circuit configuration information B for performing control is obtained.
  • the processing flow that is automatically determined will be described.
  • the circuit configuration information A is analyzed, the condition for activating the critical path is found, and the insertion position of the signal state detection circuit 12 is determined.
  • the driven control area 14 is determined. Specifically, for example, as shown in FIG. 3, when a five-stage pipeline processor is realized as a logical function, when the division instruction becomes a critical path, the division instruction is read out in the instruction read (IF). In this case, the signal path detection circuit 12 is inserted into the instruction read (IF). Next, the division circuit portion of the operation execution (EX) phase, which is a critical path, is set as the driven control area 14.
  • EX operation execution
  • the signal state detection circuit 12 is inserted into the circuit configuration information A, and automatic wiring is performed from the signal state detection circuit 12 to the driven control area 14 to generate a path for transmitting the state change signal 13. Then, the time required for the operation mode to be changed in the driven control area 14 is calculated, and timing information is generated. If the time required to change the operation mode according to the generated timing information does not satisfy the timing requirement desired by the circuit designer, the driven control area 14 is reduced based on the timing information, and automatic wiring and timing are again performed. Analyze. If the timing requirement is satisfied, and if the power consumption desired by the circuit designer is satisfied, circuit configuration information B based on the circuit configuration is generated. If not, the signal state detection circuit 12 is again or newly generated. And the driven control area 14 are determined, and this process is repeated until the required power consumption is satisfied.
  • the processing flow determined by the circuit designer is the same as the processing flow automatically determined as described above. Only the procedure for determining the insertion position of the signal state detection circuit 12 and the initial region of the driven control region 14 is different.
  • the signal state detection circuit 12 provided in the region 11 in which the logic function on the reconfigurable integrated circuit 10 is realized monitors the change of the critical path signal, and when the state changes, the driven control region 14
  • the circuit is configured so that the operation speed and the power consumption can be controlled dynamically by transmitting the state change signal 13 to.
  • FIG. 4 is a diagram for explaining a configuration example of the reconfigurable integrated circuit 10.
  • 12 is a signal state detection circuit
  • 15 is a circuit configuration circuit
  • 16 is a circuit wiring circuit
  • 17 is a circuit wiring
  • 18 is a state change signal wiring circuit
  • 19 is a state change signal wiring
  • 20 is an operating speed consumption. It is a power setting circuit.
  • the circuit configuration circuit 15 is composed of circuits constituting basic logic function gates such as flip-flops, inverters, AND gates, OR gates, look-up tables, and the like, and each circuit configuration circuit constitutes the basic logic gate. Set the power supply voltage, the input voltage to the second gate of the double-gate MOS transistor, the body voltage to the SOI (Silicon On Insulator) structure and the bulk structure MOS transistor for each circuit to be configured or each of the transistors constituting them.
  • the circuit configuration controls the operating speed and power consumption.
  • the circuit wiring circuit 16 includes a plurality of circuit wirings 17 and a switch circuit that connects the circuit wirings 17 and the circuit configuration circuit 15, and is a connection switch circuit that performs connection between the circuit configuration circuits 15.
  • a power supply voltage, an input voltage to the second gate of the double gate MOS transistor, for each circuit wiring circuit, for each switch circuit constituting the circuit wiring circuit, or for each transistor constituting the circuit wiring circuit A body voltage is set to the SOI structure and bulk structure MOS transistors to control the operation speed and power consumption.
  • the state change signal wiring circuit 17 is a switch circuit that connects the plurality of state change signal wirings 18, the state change signal wiring 18, the signal state detection circuit 12, the state change signal wiring 18, and the operation speed power consumption setting circuit 20. And a connection switch circuit for performing connection between each signal state detection circuit 12 and the operation speed power consumption setting circuit 20.
  • the circuit configuration described in FIG. 1 is realized by the configuration example in FIG. This will be described.
  • the circuit configuration circuit 15, the circuit wiring circuit 16, and the circuit wiring 17 set the region 11 in which the logic function is realized as a circuit configuration.
  • the state change signal wiring circuit 18 and the state change signal wiring 19 are used.
  • a state change signal is transmitted to each operation speed power consumption setting circuit 20 to be described later in the driven control area 14.
  • the operating speed and power consumption are dynamically controlled by the transmitted state change signal.
  • the operation speed power consumption setting circuit 20 has an operation mode storage device that can hold, for example, the operation characteristics of a transistor in a high-speed operation mode or a low power consumption mode. Set the operating speed and power consumption in the circuit.
  • FIG. 5 is a diagram showing another configuration example of the reconfigurable integrated circuit 10.
  • 12 is a signal state detection circuit
  • 15 is a circuit configuration circuit
  • 20 is an operation speed power consumption setting circuit
  • 21 is a circuit wiring / state change signal wiring circuit
  • 22 is a circuit / state change signal wiring.
  • the circuit wiring / state change signal wiring circuit 21 includes a plurality of circuits / state change signal wirings 22, circuit / state change signal wirings 22, circuit configuration circuit 15, circuit / state change signal wirings 22, and signal state detection circuit 12.
  • the circuit / state change signal wiring 22 and the operation speed power consumption setting circuit 20 are connected to each other, and the circuit state circuit 15 and the signal state detection circuit 12 and the operation speed power consumption setting circuit are connected. This is a connection switch circuit for connecting 20 connections.
  • FIG. 5 it will be described next that the embodiment of the circuit configuration of FIG. 1 can be realized as in FIG.
  • the circuit configuration circuit 15, the circuit wiring / state change signal wiring circuit 21 and the circuit / state change signal wiring 22 realize the region 11 in which the logic function is realized, and the signal state detection circuit 12 is provided in the circuit configuration circuit 15.
  • the signal state detection circuit 12 generated or provided in the circuit configuration circuit 15 is activated.
  • the state change signal generated by the signal state detection circuit 12 is supplied to each operation speed power consumption setting circuit 20 in the driven control region via the circuit wiring / state change signal wiring circuit 21 and the circuit / state change signal wiring 22.
  • a state change signal is transmitted to.
  • a circuit configuration in which the operation speed and power consumption are dynamically controlled is obtained.
  • FIG. 6 is a diagram for explaining an implementation example of the signal state detection circuit.
  • FIG. 6A shows a signal state detection circuit in a sequential circuit.
  • a signal to be detected (a signal indicating a state where a specific instruction is read in FIG. 3) is input to “Data In”.
  • the upper D-type flip-flop circuit (hereinafter referred to as “D-FF”) reads the state change at the falling edge of the clock, and a signal is transmitted from “Data Out” to the subsequent circuit.
  • D-FF D-type flip-flop circuit
  • FIG. 6B shows a signal state detection circuit in the combinational circuit.
  • the operation is similar to that of the circuit of FIG. 6A, but a delay circuit is inserted instead of the absence of a clock for synchronization,
  • the signal input to “Data In” and the signal delayed by the delay circuit are compared by an exclusive OR circuit, and if the input signal changes, a pulsed state change signal is generated, and “State Change” Is output from.
  • FIG. 7 is a diagram illustrating an implementation example of an operation speed power consumption setting circuit.
  • FIG. 7A is a circuit for setting the input voltage to the second gate of the double gate MOS transistor, the body voltage to the SOI structure and the bulk structure MOS transistor, and controlling the threshold voltage of the MOS transistor. .
  • the pulse-like state change signal transmitted by the signal state detection circuit is “State Change” in FIG. 7A via the state change signal wiring circuit and the state change signal wiring, or the circuit wiring circuit and the circuit wiring. Arrives at the terminal.
  • the “State Change” signal is input to a T-type flip-flop circuit (hereinafter referred to as T-FF), and the output of the T-FF is switched.
  • T-FF T-type flip-flop circuit
  • the output is transmitted to the multiplexer via the level shifter (LS), and the N-type transistor
  • the level shifter (LS) is not necessarily required if the output voltage of the T-FF is the same as the voltage level switched by the multiplexer.
  • two sets of voltages are switched, but two or more sets of voltages can be switched. In that case, it can be realized by combining a plurality of T-FFs in series, increasing the number of inputs of the multiplexer, and inputting the output of each T-FF to the multiplexer.
  • the T-FF has an initialization function for setting the output to a specified value. In this example, when the “Reset” terminal is enabled, the T-FF is initialized.
  • FIG. 7B is a circuit for setting the power supply voltage of a CMOS circuit composed of MOS transistors having a double gate structure, an SOI structure, or a bulk structure, and controlling the performance of the CMOS circuit.
  • the pulse-like state change signal transmitted by the signal state detection circuit is transmitted to the “State Change” terminal in FIG. 7B via the state change signal wiring circuit and the state change signal wiring, or the circuit wiring circuit and the circuit wiring. Arrive at.
  • the “State Change” signal is input to the T-FF, and the output of the T-FF is switched.
  • the output is transmitted to the multiplexer via the level shifter (LS), and a set of power supply voltages for the CMOS circuit is switched. Supply to transistor.
  • LS level shifter
  • the level shifter is not necessarily required if the output voltage of the T-FF and the voltage level switched by the multiplexer are the same. In this example, one set of voltages is switched, but one or more sets of voltages can be switched. In that case, it can be realized by combining a plurality of T-FFs in series, increasing the number of inputs of the multiplexer, and inputting the output of each T-FF to the multiplexer.
  • the T-FF has an initialization function for setting the output to a specified value. In this example, when the “Reset” terminal is enabled, the T-FF is initialized.
  • FIG. 8 is a diagram for explaining another implementation example of the operation speed power consumption setting circuit shown in FIG. FIG. 8A is a circuit for setting the input voltage to the second gate of the double gate MOS transistor and the body voltage to the SOI structure and the bulk structure MOS transistor to control the threshold voltage of the MOS transistor. is there.
  • the pulse state change signal transmitted by the signal state detection circuit is transmitted to the “State” of the circuit of FIG. 8A via the state change signal wiring circuit and the state change signal wiring, or the circuit wiring circuit and the circuit wiring. Arrives at the “Change” terminal.
  • the “State Change” signal is input to the T-FF to switch the output of the T-FF, and the output is sent to the SRAM selection multiplexer to switch the outputs of the two SRAMs.
  • the voltage is transmitted to two sets of multiplexers in the subsequent stage via the level shifter (LS), and two sets of voltages for the N-type transistor and the P-type transistor are supplied to the switching transistor.
  • the level shifter (LS) is not necessarily required as long as the output voltage of the SRAM and the level of the voltage to be switched by the subsequent multiplexer are the same.
  • two sets of voltages are switched, but two or more sets of voltages can be switched.
  • a plurality of T-FFs are combined in series, the number of SRAMs is increased as appropriate, the number of multiplexer inputs is increased, and the output of each T-FF is input to the SRAM multiplexer.
  • the T-FF has an initialization function for setting the output to a specified value. In this example, when the “Reset” terminal is enabled, the T-FF is initialized.
  • FIG. 8B is a circuit for setting the power supply voltage of a CMOS circuit composed of MOS transistors having a double gate structure, an SOI structure, or a bulk structure, and controlling the performance of the CMOS circuit.
  • the pulse-like state change signal transmitted by the signal state detection circuit is sent to the “State Change” terminal in FIG. 8B via the state change signal wiring circuit and the state change signal wiring, or the circuit wiring circuit and the circuit wiring. Arrive at.
  • the “State Change” signal is input to the T-FF, the output of the T-FF is switched, the output is sent to the SRAM selection multiplexer, and the output of the two SRAMs is switched.
  • the T-FF has an initialization function for setting the output to a specified value. In this example, when the “Reset” terminal is enabled, the T-FF is initialized.
  • FIG. 9 illustrates a circuit in which the operation speed power consumption setting circuit of FIG. 7A is applied to a CMOS inverter circuit.
  • FIG. 9A shows a CMOS inverter circuit composed of double gate MOS transistors. Two sets of voltages for the N-type transistor and P-type transistor input to the operating speed power consumption setting circuit are switched by the state change signal, and the second gate of the N-type transistor and the P-type transistor of the CMOS inverter circuit, respectively. Is applied.
  • Vb_p1 is a voltage for operating the P-type transistor in the high-speed mode
  • Vb_p2 is a voltage for operating the P-type transistor in the low power consumption mode
  • Vb_n1 is a voltage for operating the N-type transistor in the high-speed mode
  • Vb_n2 Is a voltage for operating the N-type transistor in the low power consumption mode
  • the outputs Vb_p and Vb_n of the operation speed power consumption setting circuit are set to the high-speed mode (Vb_p1 and Vb_p1 and Vb_p) every time the “State Change” signal is input.
  • Vb_n1 and the low power consumption mode (Vb_p2 and Vb_n2) are switched, the current drive capability and leakage current of the CMOS inverter circuit are controlled, and the operation speed and power consumption are similarly controlled.
  • a circuit configuration using a double gate MOS transistor is shown, but as another circuit configuration, the substrate potential of a MOS transistor having an SOI structure or a bulk structure is changed as in the circuit configuration of FIG. 9B. It may be configured as follows.
  • FIGS. 10A and 10B illustrate an example of a circuit adapted to a power supply circuit of a CMOS inverter circuit in which the operation speed power consumption setting circuit of FIG. 7B is configured by a double gate MOS transistor. Yes.
  • Two sets of voltages input to the operating speed power consumption setting circuit are switched by a “State Change” signal and connected to the power supply terminal Vdd of the CMOS inverter circuit.
  • Vdd1 is a voltage for operating the CMOS circuit in the high speed mode
  • Vdd2 is a voltage for operating the CMOS circuit in the low power consumption mode
  • the output Vdd of the operation speed power consumption setting circuit is “State Change”.
  • the mode is switched between the high speed mode (Vdd1) and the low power consumption mode (Vdd2).
  • Vdd1 the high speed mode
  • Vdd2 the low power consumption mode
  • FIGS. 11 (a) and 11 (b) an SOI type or bulk type MOS transistor is used.
  • a circuit configuration for changing the power supply voltage may be used.
  • FIG. 12 is a schematic diagram of an island style FPGA.
  • the FPGA is mainly composed of three types of CLB (Configurable Logic Block) tiles in the reconfigurable logic circuit block in the central part, IOB (Input / Output Block) tiles in the peripheral I / O circuit block, and NULL tiles in the empty circuit block. Is done.
  • FIG. 13 shows the basic structure of the CLB tile.
  • the CLB tile includes a vertical circuit wiring channel, a horizontal circuit wiring channel, a reconfigurable logic circuit CLB constituting a logic function, and a wiring channel for these two circuits and a reconfigurable logic circuit (CLB).
  • CLB reconfigurable logic circuit
  • FIG. 14 is a diagram illustrating an example of a basic structure of an IOB tile.
  • An input / output circuit block IOB that performs input / output between the vertical circuit wiring channel and the horizontal circuit wiring channel and the outside of the chip, and a switch circuit that connects the two circuit wiring channels and the input / output circuit block IOB. It consists of block SB.
  • FIG. 15 shows an example of the basic structure of the NULL tile of the empty circuit block. Only the switch circuit block SB for connecting the vertical circuit wiring channel, the horizontal circuit wiring channel, and the two circuit wiring channels is formed.
  • FIG. 16 shows a basic structure example of a general reconfigurable logic circuit CLB.
  • the reconfigurable logic circuit CLB includes a basic logic circuit element BLE (Basic Logic Element), a local multiplexer LMUX (Local Multiplexer), an input signal multiplexer IMUX (Input Multiplexer), and an output signal multiplexer OMUX (Output Multiplexer).
  • the basic logic circuit element BLE corresponds to the circuit configuration circuit 15 of the reconfigurable integrated circuit in FIGS. 4 and 5, and a general structure is a look-up table (LUT) and a flip-flop ( D-FF) is a circuit constituting a logic gate.
  • LUT look-up table
  • D-FF flip-flop
  • the local multiplexer LMUX is a switch circuit that connects the basic logic circuit elements BLE and the input signal multiplexer IMUX and the basic logic circuit element BLE, and the input signal multiplexer IMUX is a switch circuit that connects inputs from the switch circuit block SB, and an output signal
  • the multiplexer OMUX is a switch circuit for connecting the output to the switch circuit block SB.
  • FIG. 18 shows a basic structure example of a general switch circuit block SB.
  • the switch circuit block SB is composed of a plurality of switch matrices SM (Switch Matrix), and each switch matrix SM has a vertical circuit wiring channel and a horizontal circuit wiring channel and a reconfigurable logic circuit block CLB or an input / output circuit. It is composed of a switch circuit for connecting the block IOB.
  • switch Matrix switch Matrix
  • FIG. 19 shows an example of the basic structure of a reconfigurable logic circuit block CLB tile according to the present invention.
  • PSB Power Switch Block
  • a power wiring switch circuit block PSB for transmitting a state change signal (State Change signal) is added, and the state generated from the reconfigurable logic circuit block CLB
  • the change signal can be transmitted to the entire FPGA via the power wiring switch circuit block PSB and the power wiring channel, and the state change signal arriving at the power wiring switch circuit block PSB is transmitted to the switch circuit block SB and the reconfigurable logic circuit. Sent to block CLB.
  • FIG. 20 and 21 are diagrams showing examples of the basic structure of the reconfigurable logic circuit block CLB in the present invention.
  • a power supply output multiplexer POMUX Power
  • POMUX Power
  • Output Multiplexer a power supply input multiplexer PIMUX (Power Input Multiplexer) that receives a state change signal from the power wiring switch circuit block PSB is provided, and the state change signal selected by the power supply input multiplexer PIMUX is sent to the operation speed power consumption setting circuit.
  • PIMUX Power Input Multiplexer
  • the operation mode of the entire reconfigurable logic circuit block CLB is controlled, and in the case of FIG. 21, the operation mode is controlled for each element in the reconfigurable logic circuit block CLB.
  • FIG. 20 and FIG. 21 two operation speed and power consumption control methods are shown, but it is not necessary to fix to this and it is also possible to control in various ranges.
  • the switch circuit block SB includes a supply power input multiplexer PIMUX that receives a state change signal from a plurality of switch matrices SM and a power wiring switch circuit block PSB and an operation speed power consumption setting circuit.
  • Each switch matrix SM is for a vertical circuit.
  • the wiring channel, the lateral circuit wiring channel, and the switch circuit for connecting the reconfigurable logic circuit block CLB or the input / output circuit block IOB.
  • the state change signal selected by the supply power input multiplexer PIMUX is sent to the operation speed power consumption setting circuit.
  • the operation mode of the entire SB is controlled, and in the case of FIG. 23, the operation mode is controlled for each SM in the SB.
  • FIG. 22 and FIG. 23 two control methods for the operation speed and the power consumption are shown, but it is not necessary to fix to this and the control can be performed in various ranges.
  • FIG. 24 shows an example of the basic structure of the power wiring switch circuit block PSB in the present invention.
  • the power wiring switch circuit block PSB is composed of a plurality of power wiring switch matrices PSM (Power Switch Matrix), and each power wiring switch matrix PSM includes a vertical power wiring channel, a horizontal power wiring channel, and a reconfigurable logic circuit block. It is composed of a switch circuit connecting the CLB or the switch circuit block SB.
  • PSM Power Switch Matrix
  • FIG. 25 is a diagram showing a basic structure example of another reconfigurable logic circuit block CLB tile according to the present invention.
  • a vertical circuit wiring channel, a horizontal circuit wiring channel, a reconfigurable logic circuit block CLB constituting a logic function, and a switch for connecting the two circuit wiring channels to the reconfigurable logic circuit block CLB It consists of a circuit block SB.
  • the state change signal (State Change signal) can be transmitted to the entire FPGA via the switch circuit block SB and the circuit wiring channel, and the state change signal arriving at the switch circuit block SB is reconfigurable logic circuit block CLB. Sent to.
  • 26 and 27 show an example of the basic structure of another reconfigurable logic circuit block CLB in the present invention.
  • a supply power input multiplexer PIMUX that receives a state change signal from the switch circuit block SB is provided, and the state change signal selected by the supply power input multiplexer PIMUX is an operation speed.
  • the operation mode of the entire reconfigurable logic circuit block CLB is controlled
  • the operation mode of each element in the reconfigurable logic circuit block CLB is controlled. Control is performed.
  • FIG. 26 and FIG. 27 two control methods for operating speed and power consumption are shown, but it is not necessary to be fixed to this and it is also possible to control in various ranges.
  • the switch circuit block SB includes a plurality of switch matrices SM and a supply power input multiplexer PIMUX that receives a state change signal (State Change signal) output from the switch matrix SM, and an operation speed power consumption setting circuit.
  • the circuit includes a directional circuit wiring channel, a lateral circuit wiring channel, and a switch circuit that connects the reconfigurable logic circuit block CLB or the input / output circuit block IOB.
  • the state change signal selected by the supply power input multiplexer PIMUX is sent to the operation speed power consumption setting circuit.
  • the operation mode of the entire switch circuit block SB is controlled.
  • the operation mode is controlled for each switch matrix SM in the block SB.
  • FIG. 28 and FIG. 29 two control methods of the operation speed and power consumption are shown, but it is not necessary to fix to this and it is also possible to control in various ranges.
  • FIG. 30 and 31 are diagrams showing examples of the basic structure of another CLB tile according to the present invention.
  • the state change signal from the power wiring switch circuit block PSB is not the reconfigurable logic circuit block CLB, but directly supplied power input multiplexer PIMUX.
  • the state change signal from the switch circuit block SB is not directly transmitted via the supply power input multiplexer PIMUX but the reconfigurable logic circuit block CLB. It is connected to the operating speed power consumption setting circuit. As a result, the operation mode is controlled in units of tiles.
  • FIG. 32 is a diagram showing an example of the structure of the basic logic circuit element BLE in the present invention.
  • 32A outputs a normal data signal or a state change signal (State Change signal) by inserting a demultiplexer after the last stage (two-input multiplexer) of the basic logic circuit element BLE shown in FIG. can do.
  • FIG. 32B is obtained by incorporating the state detection circuit shown in FIG. 6A in the subsequent stage of the D-FF of the basic logic circuit element BLE shown in FIG.
  • the state detection circuit can be activated or disconnected by the memory (SR).
  • SR memory
  • FIG. 33 is a diagram showing a reconfigurable logic circuit block CLB in which the basic logic circuit element BLE of FIG. 32A is applied to the basic logic circuit element BLE of the reconfigurable logic circuit block CLB of FIG. 20 or FIG. .
  • the illustration relating to the supply power input multiplexer PIMUX and the operation speed power consumption setting circuit is omitted.
  • FIG. 34 is a diagram for explaining a method for realizing a signal state detection circuit equivalent to FIG. 6A in the reconfigurable logic circuit block CLB of FIG.
  • the path through which the data has passed is indicated by a solid arrow, and the path through which the clock has passed is indicated by a dashed arrow.
  • the portion “A” corresponds to the D-FF to which the first “Data In” signal in FIG. 6A is input.
  • the state change is read at the falling edge of the clock from the “B” point.
  • Data is output to the SB as “Data Out”, and at the same time, the “C” point lookup table (LUT) is set to pass the data as it is, and “A” to the D-FF at the “D” point.
  • LUT point lookup table
  • the output of the point arrives as it is, and the output of the “A” point is held at the rising timing of the clock. Since the output of the D-FF at the “D” point holds the output of the D-FF at the “A” point of the previous generation, the output of the D-FF at the “D” point and the output of the “A” point.
  • the exclusive OR of the outputs of the D-FF is taken by the LUT at the “E” point, and the output is switched to the supply power output multiplexer POMUX by the demultiplexer at the “F” point. (State Change signal) can be output.
  • FIG. 35 is a diagram showing a reconfigurable logic circuit block CLB in which the basic logic circuit element BLE of FIG. 32B is applied to the basic logic circuit element BLE of the reconfigurable logic circuit block CLB of FIG. 20 or FIG. .
  • the illustration relating to the supply power input multiplexer PIMUX and the operation speed power consumption setting circuit is omitted.
  • FIG. 36 is a diagram for explaining a method for realizing a signal state change detection circuit equivalent to FIG. 6A in the reconfigurable logic circuit block CLB of FIG.
  • SR memory
  • FIG. 6A By turning on the output of the memory (SR) at the “H” point, a signal state detection circuit equivalent to that in FIG. 6A is configured in one BLE, and the state is set via the supply power output multiplexer POMUX.
  • a change signal (State Change signal) is output.
  • a reconfigurable logic circuit includes a system LSI having a reconfigurable integrated circuit such as an FPGA as one core, and mobile terminals, digital home appliances, communication devices, servers, storages, which are major application fields thereof. Available for supercomputers.

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  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

L'invention porte sur un circuit intégré reconfigurable formé par un transistor à effet de champ (FET) ayant une caractéristique d'opération qui est commandée de manière appropriée lors d'un fonctionnement de circuit, permettant ainsi de réaliser simultanément une haute vitesse et une faible consommation de puissance. Le circuit intégré reconfigurable comprend : une pluralité de circuits de constitution de circuit qui constituent un circuit pour calculer une fonction logique par utilisation d'informations de configuration de circuit; un circuit de câblage de circuit qui réalise des connexions entre les circuits de constitution de circuit; un circuit de détection d'état de signal qui détecte un changement d'un signal interne des circuits de constitution de circuit ou du circuit de câblage de circuit; un circuit de câblage à changement d'état qui transmet le signal de changement d'état détecté par le circuit de détection d'état de signal aux circuits de constitution de circuit ou au circuit de câblage de circuit; et un circuit de configuration de vitesse de fonctionnement qui configure la caractéristique de fonctionnement du FET pour chacun des circuits partiels des circuits de constitution de circuit ou du circuit de câblage de circuit.
PCT/JP2009/056451 2008-03-31 2009-03-30 Circuit intégré reconfigurable WO2009123090A1 (fr)

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JP2013236082A (ja) * 2012-05-08 2013-11-21 Altera Corp 抵抗スイッチアレイのためのルーティングおよびプログラミング
JP2018007167A (ja) * 2016-07-07 2018-01-11 日本電気株式会社 スイッチ回路およびこれを用いた半導体装置
CN117236254A (zh) * 2023-11-13 2023-12-15 中科芯磁科技(珠海)有限责任公司 可配置逻辑块控制方法、可配置逻辑块及存储介质

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JPH0945785A (ja) * 1995-07-24 1997-02-14 Motorola Inc 高速・低電力用しきい電圧選択方法
JP2001156261A (ja) * 1999-09-13 2001-06-08 Hitachi Ltd 半導体集積回路装置
JP2004335686A (ja) * 2003-05-07 2004-11-25 National Institute Of Advanced Industrial & Technology 高速低消費電力論理装置
JP2005109179A (ja) * 2003-09-30 2005-04-21 National Institute Of Advanced Industrial & Technology 高速低消費電力論理装置

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JPH0945785A (ja) * 1995-07-24 1997-02-14 Motorola Inc 高速・低電力用しきい電圧選択方法
JP2001156261A (ja) * 1999-09-13 2001-06-08 Hitachi Ltd 半導体集積回路装置
JP2004335686A (ja) * 2003-05-07 2004-11-25 National Institute Of Advanced Industrial & Technology 高速低消費電力論理装置
JP2005109179A (ja) * 2003-09-30 2005-04-21 National Institute Of Advanced Industrial & Technology 高速低消費電力論理装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013236082A (ja) * 2012-05-08 2013-11-21 Altera Corp 抵抗スイッチアレイのためのルーティングおよびプログラミング
JP2018098514A (ja) * 2012-05-08 2018-06-21 アルテラ コーポレイションＡｌｔｅｒａ Ｃｏｒｐｏｒａｔｉｏｎ 抵抗スイッチアレイのためのルーティングおよびプログラミング
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JP2018007167A (ja) * 2016-07-07 2018-01-11 日本電気株式会社 スイッチ回路およびこれを用いた半導体装置
CN117236254A (zh) * 2023-11-13 2023-12-15 中科芯磁科技(珠海)有限责任公司 可配置逻辑块控制方法、可配置逻辑块及存储介质
CN117236254B (zh) * 2023-11-13 2024-03-15 中科芯磁科技(珠海)有限责任公司 可配置逻辑块控制方法、可配置逻辑块及存储介质

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